The invention comprises an interface for switching control of a memory management unit (MMU) between a central processing unit (CPU) having a register stack for storing data, and one or more coprocessors (COP) each having register stacks for storing data. The COP is operative when actuated to perform selected functions, not normally performed by the CPU, utilizing information in memory.

A memory management system for minimizing I/O data transfer latency during the resolution of page faults. A page protection register having a mask with validity bits corresponding to each data line of the page in local memory is implemented in the memory controller. The mask bits are set when the corresponding data line has been input via the memory controller and is ready for access. When a page fault is received by the microprocessor, the desired page is read into the microprocessor's local memory, and the mask bit corresponding to the critical line which caused the page fault is checked. Processing of the process which requested the critical data line proceeds as soon as the mask bit for the critical data line is set, thereby preventing the microprocessor from having to wait for the entire page to be transferred into local memory before processing continues. In addition, the invention provides a mechanism whereby the address of the critical data line is identified and provided to the external memory so that the data lines in the page may be sent out of order. In particular, the critical data line may be sent first so that it is the first data line stored in the local memory during memory I/O. The mask bits corresponding to the critical line are thus set first, thereby allowing the microprocessor to be quickly reactivated so that processing may proceed in parallel with I/O to the microprocessor's local memory. When the present invention is implemented for a page having N data lines, the data transfer latency time may be reduced by as much as a factor of N.

A data communication method provides management and control functions to allow access to a shared radio frequency communication device by multiple concurrently executing software applications. A predetermined set of commands common to all of the software applications enable a consistent, high-level software interface to the communication device. A single computer program controls the communication device and permits simultaneous independent interface to each of the software applications.

A method of controlling an input/output (I/O) device connected to a computer to facilitate fast I/O data transfers. An address space for the I/O device is created in the virtual memory of the computer, wherein the address space comprises virtual registers that are used to directly control the I/O device. In essence, control registers and/or memory of the I/O device are mapped into the virtual address space, and the virtual address space is backed by control registers and/or memory on the I/O device. Thereafter, the I/O device detects writes to the address space. As a result, a pre-defined sequence of actions can be triggered in the I/O device by programming specified values into the data written into the mapped virtual address space.

A system and method for sharing a resource (e.g., buffers) among multiple queues (e.g., InfiniBand send queues). Each queue has a local context indicating the Current amount of the resource allocated to the queue, the Minimum it is guaranteed, and a Maximum amount. A context may also include one or more pointers for managing the queue. Global Available and Reserve values indicate, respectively, the amount of the resource not currently allocated and the amount of the resource being reserved to guarantee each queue its Minimum. When an element is posted to a queue, a Full signal is raised for every queue to prevent further activity while the global values and the affected queue's context are updated. Then, if Available>0, the signal is de-asserted for any queue for which Current<Minimum or, if Available>Reserve, for any queue for which Current<Maximum.