In a memory system having a main memory and a faster cache memory, a cache memory replacement scheme with a locking feature is provided. Locking bits associated with each line in the cache are supplied in the tag table. These locking bits are preferably set and reset by the application program/process executing and are utilized in conjunction with cache replacement bits by the cache controller to determine the lines in the cache to replace. The lock bits and replacement bits for a cache line are "ORed" to create a composite bit for the cache line. If the composite bit is set the cache line is not removed from the cache. When deadlock due to all composite bits being set will result, all replacement bits are cleared. One cache line is always maintained as non-lockable. The locking bits "lock" the line of data in the cache until such time when the process resets the lock bit. By providing that the process controls the state of the lock bits, the intelligence and knowledge the process contains regarding the frequency of use of certain memory locations can be utilized to provide a more efficient cache.

A method and apparatus for cache lock control are designed for use with a cache memory. The cache memory contains a number of data entries, each divided into segments for storing address information, data, and a cache lock bit, respectively. The cache lock bit, when set in a data entry, prevents updating the address and data in that data entry. An address translator is provided for converting virtual memory addresses to physical addresses. The address translator includes address entries which include at least one segment for storing cache lock information, and cache lock information is transferred from the address translator to the cache memory.

A method and an apparatus for cache lock control are designed for use with a cache memory. The cache memory has divided entries each for storing data and cache lock information. Updating of data in each of the entries of the cache memory is controlled in response to cache priority order information in each of the entries of the cache memory.

Virtual addresses from multiple address spaces are translated to real addresses in main memory by generating for each virtual address an address space identifier (AID) identifying its address space. Then, the virtual address and its AID are used to obtain the real address. The address spaces include a shared address space, from which the processor can provide a virtual address at any time, as well as switched address spaces, from one of which the processor can provide a virtual address at a given time. If the processor's local cache does not have data for the virtual address and cannot translate the virtual address to a real address, the local cache provides the virtual address on a bus. A dedicated VLSI map cache is connected for receiving virtual addresses from the bus and for providing real addresses on the bus. The bus is also connected for providing real addresses to access memory. The map cache, which can handle address translation for multiple processors connected to the bus, translates by keeping the most recently accessed mapping entries, each of which associates a virtual address and its AID with a real address. If the virtual address is from the shared address space, the map cache uses the shared AID, but if not, the map cache uses the current switched AID for the processor providing the virtual address.

A microprocessor architecture that includes capabilities for locking individual entries into its integrated instruction cache and data cache while leaving the remainder of the cache unlocked and available for use in capturing the microprocessor's dynamic locality of reference. The microprocessor also includes the capability for locking instruction cache entries without requiring that the instructions be executed during the locking process.