Disclosed is a semiconductor memory device. The memory device includes a plurality of memory cells, and a write control unit for controlling voltages applied to the memory cells to write data in the memory cells. The memory device further includes a current detector, connected to the write control unit. The current detector being implemented for detecting a cell current flowing in each of the memory cells and controlling the write control unit based on the detected cell current value. In this manner, writing to the memory cells is permitted until desired data is rewritten in each memory cell.

A flash EEPROM has a memory cell array of memory cells. Each memory cell includes a floating gate electrode, a source, a drain and a control gate electrode. A data value is stored in a memory cell by storing a charge in its floating gate electrode. A control circuit controls voltages applied to the control gate electrode, the source and the drain of the memory cells. A charge which is greater than a charge amount corresponding to a desired data value is stored in the floating gate electrode of a memory cell. In the write mode, charge is drained from the floating gate electrode. A write determining circuit checks the amount of charge remaining in the floating gate electrode after charge has been drained from it. The write determining circuit disables the write operation when the amount of charge remaining in the floating gate electrode reaches the charge amount corresponding to the desired data value.

A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and includes a source region, a drain region and a channel region located between the source and drain regions. The channel region has a plurality of regularly arranged tips thereon. The first dielectric layer is disposed on the poly-silicon island. The trapping layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the trapping layer. The control gate is disposed on the second dielectric layer. The memory cell mentioned above can be integrated into the LTPS-LCD panel or OLED panel.

Split gate type transistor made by the steps of: forming a semiconductor substrate; forming a floating gate electrode over the semiconductor substrates the floating gate electrode having at least one lateral face portion; and nitrating the at least one lateral face portion to form a nitrogen-containing layer.

According to the present invention, a method for producing a nonvolatile semiconductor memory device is provided. The method includes the steps of: forming stripe-shaped silicon portions including a plurality of first portions to be used as a plurality of floating gates and a plurality of second portions interposed between two adjacent portions of the plurality of first portions by patterning a silicon film; forming a conductive film so as to cover an insulating film; forming a control gate so as to cover the plurality of first portions of the stripe-shaped silicon portions by patterning the conductive film; converting the plurality of second portions of the stripe-shaped silicon portions into a silicon oxide film, and forming the plurality of floating gates from the plurality of first portions by thermally oxidizing the plurality of second portions; and implanting impurity ions through the silicon oxide film into the active region on the semiconductor substrate by using the control gate as a mask, thereby forming a source region and a drain region in the active region.