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Claims  |
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Having thus described my invention, what I claim as new and desire to
secure by Letters Patent is as follows:
1. A double-rate oversampled interpolative modulator for analog-to-digital
conversion comprising:
a switched capacitor integrator having at least one input and at least one
output;
analog-to-digital conversion means coupled to the output of said switched
capacitor integrator for generating a digital output signal; and
digital-to-analog conversion means coupled to receive the digital output
signal of said analog-to-digital conversion means and to generate a
quantized analog voltage proportional to said digital output signal, said
switched capacitor integrator including an operational amplifier, a
feedback capacitor, and sampling means, said sampling means comprising:
first and second switch means for alternately sampling an analog input
signal and said quantized analog voltage proportional to said digital
output signal,
first and second input capacitors adapted to be alternately charged by said
analog input signal and said quantized analog voltage, and
third and fourth switch means for alternately coupling said first and
second capacitors to ground and to an input of said operational amplifier,
said switch means being operable by predetermined phases of a clock in
order to enable said integrator to perform an integration twice per clock
cycle so as to double an effective operating rate of the oversampled
modulator.
2. The double-rate oversampled interpolative modulator of claim 1 wherein
said analog-to-digital conversion means comprises first and second
analog-to-digital converters and said digital-to-analog conversion means
comprises first and second digital-to-analog converters, the output of
said first analog-to-digital converter being coupled to said first
digital-to-analog converter and the output of said second
analog-to-digital converter being coupled to said second digital-to-analog
converter, and further comprising:
fifth and sixth switch means for alternately coupling the output of said
integrator to said first and second analog-to-digital converters; and
multiplexer means connected to the outputs of said first and second
analog-to-digital converters for selecting one of said outputs as the
output of said oversampled modulator.
3. The double-rate oversampled interpolative modulator of claim 2 wherein
the analog-to-digital converters and digital-to-analog converters each
have a quantization level of 1, said first and second analog-to-digital
converters each comprise an auto-zeroed comparator, respectively, and said
first and second digital-to-analog converters each comprise first and
second switched voltage reference sources, respectively.
4. The double-rate oversampled interpolative modulator recited in claim 1
wherein each of said analog-to-digital conversion means and said
digital-to-analog conversion means comprises a respective converter for
operating twice per clock cycle to perform conversions during said
predetermined phases of the clock.
5. The double-rate oversampled interpolative modulator of claim 1 wherein
said analog-to-digital conversion means comprises an analog-to-digital
converter operable at twice per clock cycle to perform conversions during
said predetermined phases of the clock and said digital-to-analog
conversion means comprises first and second digital-to-analog converters,
said modulator further comprising fifth switch means for alternately
coupling an output of said analog-to-digital conversion means to said
first and second digital-to-analog converters during a clock cycle.
6. The double-rate oversampled interpolative modulator of claim 1 wherein
said switched capacitor integrator includes balanced inputs and balanced
outputs, said operational amplifier being a differential amplifier having
inverting and noninverting inputs and inverting and noninverting outputs,
and said first and second input capacitors each comprise a pair of
balanced capacitors.
7. The double-rate oversampled interpolative modulator of claim 6 further
comprising chopper means coupled to the inputs and outputs of said
differential amplifier for stabilizing operation of said modulator, said
chopper means operating at a rate that is an integral multiple rate of an
output conversion rate.
8. The double-rate oversampled interpolative modulator of claim 6 further
comprising dynamic element matching means for periodically interchanging
the two capacitors of each input pair of capacitors, so as to cause errors
due to size mismatches to alternate in polarity and cancel.
9. A double-rate second-order oversampled interpolative modulator for
analog-to-digital conversion comprising:
first and second switched capacitor integrators each having at least one
input and at least one output, an input of said second switched capacitor
integrator being coupled to an output of said first switched capacitor
integrator;
L-bit analog-to-digital conversion means coupled to the output of said
second switched capacitor integrator for generating an L-bit digital
output signal; and
L-bit digital-to-analog conversion means coupled to receive said L-bit
digital output signal of said L-bit analog-to-digital conversion means and
to generate a quantized analog voltage proportional to said L-bit digital
output signal, wherein L is the quantization level of said
analog-to-digital and digital-to-analog conversion means, each of said
first and second switched capacitor integrators includes an operational
amplifier, a feedback capacitor, and sampling means, respectively, and
each said sampling means comprises:
first and second switch means for alternately sampling an input signal and
said quantized analog voltage proportional to said L-bit digital output
signal,
first and second input capacitors adapted to be alternately charged by said
input signal and said quantized analog voltage, and
third and fourth switch means for alternately coupling said first and
second capacitors to ground and to an input of said operational amplifier,
said switch means being operable by predetermined phases of a clock in
order to enable the integrator that includes said each sampling means to
perform an integration twice per clock cycle so as to double an effective
operating rate of the oversampled modulator.
10. The double-rate second-order oversampled interpolative modulator of
claim 9 wherein said L-bit analog-to-digital conversion means comprises
first and second analog-to-digital converters and said L-bit
digital-to-analog conversion means comprises first and second L-bit
digital-to-analog converters, the output of said first analog-to-digital
converter being coupled to said first digital-to-analog converter and the
output of said second analog-to-digital converter being coupled to said
second digital-to-analog converter, and further comprising:
fifth switch means for alternately coupling the output of said second
switched capacitor integrator to said first and second analog-to-digital
converters; and
multiplexer means coupled to the outputs of said first and second
analog-to-digital converters for selecting one of the outputs of said
analog-to-digital converters as the output of said oversampled modulator.
11. The double-rate second order oversampled interpolative modulator of
claim 10 wherein L equals 1, said first and second analog-to-digital
converters each comprise an auto-zeroed comparator, respectively, and said
first and second digital-to-analog converters each comprise first and
second switched voltage reference sources, respectively.
12. The double-rate second-order oversampled interpolative modulator of
claim 9 wherein each of said L-bit analog-to-digital conversion means and
said L-bit digital-to-analog conversion means comprises a respective
converter for operating twice per clock cycle to perform conversions
during said predetermined phases of the clock.
13. The double-rate second-order oversampled interpolative modulator of
claim 9 wherein said L-bit analog-to-digital conversion means comprises an
analog-to-digital converter operable at twice per clock cycle to perform
conversions during said predetermined phases of the clock and said L-bit
digital-to-analog conversion means comprises first and second L-bit
digital-to-analog converters, said modulator further comprising fifth
switch means for alternately coupling an output of said analog-to-digital
conversion means to said first and second digital-to-analog converters
during a clock cycle.
14. The double-rate second-order oversampled interpolative modulator of
claim 9 wherein each of said first and second switched capacitor
integrators includes balanced inputs and balanced outputs, each of said
operational amplifiers being a differential amplifier having inverting and
noninverting inputs and inverting and noninverting outputs, and said first
and second input capacitors of each of said switched capacitor integrators
comprises a pair of balanced capacitors, respectively
15. The double-rate second-order oversampled interpolative modulator of
claim 14 further comprising chopper means coupled to the inputs and
outputs of the differential amplifier of said first switched capacitor
integrator for stabilizing operation of said modulator, said chopper means
operating at a rate that is an integral multiple rate of an output
conversion rate.
16. The double-rate second-order oversampled interpolative modulator of
claim 14 further comprising dynamic element matching means for
periodically interchanging the two capacitors of each input pair of
capacitors of said first and second switched capacitor integrators,
respectively, so as to cause errors due to mismatch to alternate in
polarity and cancel.
17. A double-rate third-order oversampled interpolative modulator for
analog-to-digital conversion comprising:
first, second and third switched capacitor integrators each having at least
one input and at least one output, an input of said second switched
capacitor integrator being coupled to an output of said first switched
capacitor integrator and an input of said third switched capacitor
integrator being coupled to an output of said second switched capacitor
integrator;
L-bit analog-to-digital conversion means coupled to the output of said
second switched capacitor integrator for generating an L-bit digital
output signal;
L-bit digital-to-analog conversion means coupled to receive said L-bit
digital output signal of said L-bit analog-to-digital conversion means and
to generate a first quantized analog voltage proportional to said L-bit
digital output signal;
M-bit analog-to-digital conversion means coupled to the output of said
third switched capacitor integrator for generating an M-bit digital output
signal;
M-bit digital-to-analog conversion means coupled to receive said M-bit
digital output signal of said M-bit analog-to-digital conversion means and
to generate a second quantized analog voltage proportional to said M-bit
digital output signal, wherein L and M each represents a quantization
level of said L-bit analog-to-digital and digital-to-analog conversion
means and said M-bit analog-to-digital and digital-to-analog conversion
means, respectively, each of said first, second and third switched
capacitor integrators includes an operational amplifier, a feedback
capacitor, and sampling means, respectively, and each said sampling means
comprises:
first and second switch means for alternately sampling an input signal and
said first quantized analog voltage, said first and second switch means of
said first and second switched capacitor integrators being coupled to
sample said first quantized analog voltage and said first and second
switch means for said third switched capacitor integrator being coupled to
sample said second quantized analog voltage,
first and second input capacitors for being charged alternately by said
input signal and said first quantized analog voltage, and
third and fourth switch means for alternately coupling said first and
second capacitors to ground and to an input of said operational amplifier
of said first and second switched capacitor integrators, respectively,
each of said switch means being operated by a predetermined clock phase,
respectively, to enable said switched capacitor integrator in which it is
included to perform an integration twice per clock cycle so as to double
an effective operating rate of the oversampled modulator; and
digital canceler means coupled to receive output signals from said second
and third switched capacitor integrators for providing an output signal
from said modulator.
18. The double-rate third-order oversampled interpolative modulator of
claim 17 wherein said L-bit analog-to-digital conversion means and said
M-bit analog-to-digital conversion means each comprises first -and second
L-bit analog-to-digital converters and first and second M-bit
analog-to-digital converters, respectively, said L-bit digital-to-analog
conversion means comprises first and second L-bit digital-to-analog
converters, the output of said first L-bit analog-to-digital converter
being coupled to said first L-bit digital-to-analog converter and the
output of said second L-bit analog-to-digital converter being coupled to
said second L-bit digital-to-analog converter, and said M-bit
digital-to-analog conversion means comprises first and second M-bit
digital-to-analog converters, the output of said first M-bit
analog-to-digital converter being coupled to said first M-bit
digital-to-analog converter and the output of said second M-bit
analog-to-digital converter being coupled to said second M-bit
digital-to-analog converter, further comprising:
fifth switch means for coupling the output of said second switched
capacitor integrator alternately to said first and second L-bit
analog-to-digital converters;
first multiplexer means coupled to the outputs of said first and second
L-bit analog-to-digital converters for selecting one of the outputs of
said L-bit analog-to-digital converters as the output of said second
switched capacitor integrator;
sixth switch means for coupling the output of said third switched capacitor
integrator alternately to said first and second M-bit analog-to-digital
converters; and
second multiplexer means coupled to the outputs of said first and second
M-bit analog-to-digital converters for selecting one of the outputs of
said M-bit analog-to-digital converters as the output of said third
switched capacitor integrator.
19. The double-rate third-order oversampled interpolative modulator of
claim 18 wherein L equals 1, each of said analog-to-digital converters
respectively comprises an auto-zeroed comparator and each of said
digital-to-analog converters respectively comprises a switched voltage
reference source.
20. The double-rate third-order oversampled interpolative modulator of
claim 17 wherein each of said analog-to-digital conversion means and said
digital-to-analog conversion means is comprised of converters operating
twice per clock cycle to perform analog-to-digital and digital-to-analog
conversions on said predetermined clock phases.
21. The double-rate third-order oversampled interpolative modulator of
claim 17 wherein each of said L-bit and said M-bit analog-to-digital
conversion means respectively comprises first and second analog-to-digital
converters operating twice per clock cycle to perform conversions on said
predetermined clock phases and each of said L-bit and said M-bit
digital-to-analog conversion means respectively comprises first and second
digital-to-analog converters, and further comprising:
fifth switch means for coupling the output signal of said second switched
capacitor integrator alternately through said first and second
analog-to-digital converters of said L-bit analog-to-digital conversion
means to said first and second digital-to-analog converters of said L-bit
digital-to-analog conversion means during a clock cycle; and
sixth switch means for coupling the output signal of said third switched
capacitor integrator alternately through said first and second
analog-to-digital converters of said M-bit analog-to-digital conversion
means to said first and second digital-to-analog converters of said M-bit
digital-to-analog conversion means during a clock cycle.
22. The double-rate third-order oversampled interpolative modulator of
claim 17 wherein each of said first, second and third switched capacitor
integrators includes balanced inputs and balanced outputs, the operational
amplifier of each said sampling means comprises a differential amplifier
having inverting and noninverting inputs and inverting and noninverting
outputs, and the first and second input capacitors of each said sampling
means comprise a pair of balanced capacitors.
23. The double-rate third-order oversampled interpolative modulator of
claim 22 further comprising chopper means coupled to the inputs and
outputs of the differential amplifier of said first switched capacitor
integrator for stabilizing operation of said modulator, said chopper means
being adapted to operate at a rate that is an integral multiple of an
output conversion rate for said modulator.
24. The double-rate third-order oversampled interpolative modulator of
claim 23 wherein each respective one of said first, second and third
switch capacitor integrators further comprises dynamic circuit element
matching means for periodically interchanging the two capacitors of each
input pair of capacitors of said first, second and third switched
capacitor integrators, respectively, so as to cause errors due to circuit
element mismatch to alternate in polarity and thereby cancel. |
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Claims |
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Description |
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CROSS-REFERENCE TO RELATED APPLICATION
This application is related in subject matter to the copending U.S. patent
application Ser. No. 07/505,384 of David B. Ribner entitled "Third Order
Sigma Delta Oversampled Analog-to-Digital Converter Network with Low
Component Sensitivity" filed Apr. 6, 1990, and assigned to the assignee of
this application. The subject matter thereof is hereby incorporated by
reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to oversampled analog-to-digital converters and,
more particularly, to a technique for doubling the effective operating
rate of an oversampled modulator to realize an increase in performance
either in the form of an increase in resolution or an increase in
conversion rate, without any reduction in resolution of oversampled
analog-to-digital converters. The principles of the invention are
generally applicable to any oversampled network, including second- and
third-order oversampled modulators.
2. General Description of the Prior Art
High resolution analog-to-digital signal conversion can be achieved with
lower resolution components through the use of an oversampled
interpolative (or sigma delta) modulator followed by a digital low pass
decimation filter. Oversampling constitutes operation of the modulator at
a rate many times above the signal Nyquist rate, whereas decimation
constitutes reduction of the clock rate down to the Nyquist rate.
Sigma delta modulators (sometimes referred to as delta sigma modulators)
have been used in analog-to-digital (A/D) converters for some time.
Detailed general information can be obtained from the following technical
articles which are hereby incorporated by reference.
(1) "A Use of Limit Cycle Oscillators to Obtain Robust Analog to Digital
Converters", J. C. Candy, IEEE Transactions on Communications, Vol.
COM-22, No. 3, pp. 298-305, March 1974
(2) "Using Triangularly Weighted Interpolation to Get 13-Bit PCM from a
Sigma-Delta Modulator", J. C. Candy et al., IEEE Transactions on
Communications, Vol. COM-24, No. 11, pp. 1268-1275, November 1976
(3) "A Use of Double Integration in Sigma Delta Modulator", J. C. Candy,
IEEE Transactions on Communication, Vol. COM-33, No. 3, pp. 249-258, March
1985
Oversampled analog-to-digital converters perform a coarse quantization of
their input signal at a sampling rate that is much higher than the Nyquist
rate. Using a combination of feedback and integration, the resulting
quantization noise is forced to high frequency so that its removal can be
effected by low pass filtering and decimation. Enhanced resolution is
obtained after these operations, but only at the expense of a reduction in
throughput from the initial conversion rate. This type of converter offers
the flexibility of allowing a tradeoff between resolution in time and
resolution in amplitude. As an example, it is possible to achieve 16-bit
conversions starting with only a 1-bit quantizer.
The ratio of the initial to final conversion rates, referred to as the
oversampling ratio, governs the increase in resolution that is obtained
for a given design of oversampled analog-to-digital converter (ADC). For a
second-order modulator design, for instance, resolution improves by 2.5
bits for each doubling of the oversampling ratio, and increases to 3.5
bits for a third-order modulator. It would be desirable to operate with as
high an oversampling ratio as possible; however, for a specified final
conversion rate, circuit speed will impose a limitation on any given
technology. A method that doubles the sampling ratio without increasing
the circuit speed requirements would be useful in offering either improved
resolution, e.g., 3.5 bits for a third-order modulator, or a doubling of
the conversion rate without any reduction in resolution for higher
frequency applications.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to double the effective
operating rate of any oversampled modulator, without any increase in clock
rate or circuit speed requirements, in order to improve ADC resolution or
conversion rate.
The invention contemplates a circuit transformation applicable to any
switched capacitor (SC) oversampled modulator, regardless of its order,
that doubles its effective sampling rate. The circuit transformation
consists of adding a second input capacitor and switches to each
integrator operating on alternate clock phases. The switches employed in
the circuitry are typically field effect transistor (FET) switches. In
addition, each quantizer in the network is replaced by two quantizers,
again operated on opposite clock phases. Alternatively, the quantizers can
be simply operated at twice the normal rate if feasible for the particular
circuit.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other objects, aspects and advantages will be better
understood from the following detailed description of a preferred
embodiment of the invention with reference to the drawings, in which:
FIG. 1 is a schematic diagram of a first-order oversampled modulator;
FIG. 2 is a schematic diagram of a double-rate oversampled m according to
the invention;
FIG. 3 is a timing diagram showing the clock waveforms for operating the
switches in the double-rate oversampled modulator shown in FIG. 2;
FIG. 4 is a schematic diagram of a first-order oversampled double-rate
modulator according to the invention;
FIG. 5 is a timing diagram showing the clock waveforms for operating the
switches in the modulator shown in FIG. 4;
FIG. 6 is a schematic diagram of a double-rate second-order oversampled
modulator according to the invention;
FIG. 7 is a schematic diagram of a double-rate third-order oversampled
modulator according to the invention;
FIG. 8 is a schematic diagram of a double-rate oversampled modulator using
a single double-rate analog-to-digital converter and a single double-rate
digital-to-analog converter;
FIG. 9 is a timing diagram showing the clock waveforms for the modulator
shown in FIG. 8;
FIG. 10 is a schematic diagram of a double-rate oversampled modulator using
a single double-rate analog-to-digital converter but two digital-to-analog
converters;
FIG. 11A and 11B are a schematic diagram of a double-rate third-order
modulator using differential amplifiers with chopper stabilization for the
first stage; and
FIG. 12 is a timing diagram showing the clock waveforms for operating the
switches in the modulator shown in FIG. 11A and 11B.
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a simple first-order modulator 10 that switches alternately
between clock phases .phi..sub.1 and .phi..sub.2, using two
phase-nonoverlapping clocks. The modulator comprises a stray-free switched
capacitor integrator 18 along with an analog-to-digital converter (ADC) 16
and a digital-to-analog converter (DAC) 17.
During clock phase .phi..sub.1, the modulator analog input signal V.sub.i
is sampled by an input capacitor 12 as a switch 11 is connected to the
input and switch 13 is connected to ground. Also during this clock phase,
an operational amplifier 14, acting as a sample and hold circuit due to a
feedback capacitor 15 of capacitance C.sub.f, provides a constant signal
for ADC 16 to convert to a digital format. The output signal of ADC 16 is
supplied to the digital input of DAC 17 so as to provide a quantized
analog signal as a feedback signal to integrator 18.
On the subsequent clock phase .phi..sub.2, switches 11 and 13 alternate to
connect input capacitor 12 between the output of DAC 17 and the inverting
input of operational amplifier 14. This causes a charge equal to the
difference between the input voltage and the DAC output voltage V.sub.DAC
times the value of the input capacitance C.sub.i to be injected into the
operation amplifier feedback capacitor 15. As a result, the operational
amplifier output voltage V.sub.o changes in the discrete time domain
according to the following equation:
##EQU1##
where n represents the discrete time instant nT (T being the sampling
period of the two phase clocks). Taking the Z transform of the above
equation results in the following equation:
##EQU2##
Z the discrete time frequency variable. The integrator in this
configuration therefore integrates the difference of the analog input
signal and the DAC output signal in the feedback loop.
At low frequencies, the gain of the integrator is very high so that the
output signal of the modulator approximates the input signal of the loop
with little error. Furthermore, quantization noise introduced by ADC 16 is
attenuated by the loop gain and is thereby attenuated at low frequency and
becomes prominent at frequencies where the loop gain is low. The output of
ADC 16 is connected to a digital lowpass filter and a decimator (not
shown) to attenuate high frequency quantization noise and produce a high
resolution digital output signal.
The new double-rate oversampled modulator 20 according to the invention is
shown in FIG. 2 and the switch timing clock phases are shown in FIG. 3.
The invention applies, for the first time, high frequency switched
capacitor techniques to oversampled modulators. Such techniques have been
used in ladder filters as described by Tat C. Choi and Robert W. Bordersen
in "Considerations for High-Frequency Switched-Capacitor Ladder Filters",
IEEE Trans on Circuits and Systems, Vol. CAS-27, No. 6, June 1980, pp.
545-552. The technique used in the present invention permits the sample
rate to be twice the clock rate.
Referring now to FIG. 2, a switched capacitor integrator 30 comprises two
input switches 21a and 21b connected to alternately sample the analog
input voltage during clock phases .phi..sub.1 and .phi..sub.2,
respectively. However, there is a nonoverlapping of the sampling of the
analog input signal, as indicated by the time spacing between the
.phi..sub.1 and .phi..sub.2 clocks in FIG. 3. This avoids any overlap of
the connection of input capacitors 22a and 22b by switches 23a and 23b,
respectively, to the inverting input of an operational amplifier 24. Thus,
while a feedback capacitor 25 is being charged by one of the input
capacitors, the other input capacitor is sampling the input voltage. A
switch 28 is connected to the output of integrator 30 to alternately
connect the output at the clock rate to L-bit individual ADC and DAC. The
outputs of the L-bit ADCs 26a and 26b are connected to an L-bit 2-to-1
multiplexer 29 which provides the L-bit digital output. The L-bit output
signals of ADCs 26a and 26b are respectively supplied to L-bit DACs 27a
and 27b which, in turn, generate analog feedback voltages to the sampling
switches 21a and 21b.
Operation at twice the original speed is achieved by the action of the
second set of capacitors and switches, allowing integrator 30 to update
its output signal on both clock phases In addition, the dual ADCs 26a, 26b
and dual DACs 27a, 27b facilitate quantization to be carried out on both
clock phases. Matching of the two quantizers is not critical, although
each DAC 27a and 27b must have an accuracy comparable with the required
resolution of the oversampled system after decimation and filtering. When
this is the case, relative gain and offset errors of the two DACs average
together to determine the overall gain and offset after decimation. Also,
in a preferred embodiment, one bit ADCs and DACs are used, due to their
inherent linearity.
A specific implementation of the double-rate technique applied to a
first-order oversampled modulator 40 is shown in FIG. 4 for the case of a
one-bit quantizer, and the associated clock waveforms are shown in FIG. 5.
Elements which are identical to those of FIG. 2 are identified by the same
reference numerals in FIG. 4. The one-bit ADCs 41a and 41b respectively
comprise operational amplifiers 42a and 42b having input capacitors 43a
and 43b alternately connected to the output of operational amplifier 24
and ground by switches 44a and 44b, respectively. Feedback loops between
the outputs and the negative inputs of operational amplifiers 42a and 42b
are provided with switches 45a and 45b which are alternately opened and
closed. Thus, the ADCs 41a and 41b comprise autozeroed comparators. The
outputs of the operational amplifiers 42a and 42b are connected by
respective inverting amplifiers 46a and 46b to multiplexer 29 and to
respective DACs 47a and 47b. Each of DACs 47a and 47b is just a
singlepole, double-throw (SPDT) switch that connects to either the
reference voltage V.sub.ref or to -V.sub.ref.
The two-phase switching sequence of the auto-zeroed comparators adds a
one-half cycle delay to the feedback loops that is necessary for stable
operation of the modulator. The two-level DACs 47a and 47b are
advantageous since mismatch in their levels can only introduce an offset
error and cannot add any nonlinearity. Offset can usually be tolerated and
often calibrated out; however, nonlinearity is a severe problem to
overcome once introduced. Those skilled in the art will recognize that a
dither signal is needed for the case of a first-order modulator, but this
detail is not indicated in FIGS. 1 or 4.
To demonstrate that this double-rate circuit technique is applicable to
virtually any oversampled network, second and third-order implementations
are shown in FIGS. 6 and 7, respectively.
FIG. 6 shows a double-rate second-order oversampled modulator 60 which
incorporates the modulator 20 of FIG. 2 preceded by an additional
double-rate integrator 31 substantially identical to integrator 30. The
input to second-order modulator 60 is via switches 61a and 61b of
integrator 31 which alternately sample the input analog voltage and the
output signal of the L-bit DACs 27a and 27b, respectively. The sampled
analog voltage charges input capacitors 62a and 62b when the capacitors
are connected to ground via switches 63a and 63b, respectively.
Alternately, the capacitors are connected to the inverting input of a
second operational amplifier 64. The output of operational amplifier 64 is
alternately sampled by switches 21a and 21b .
The aforementioned application Ser. No. 07/505,384 is directed to a
third-order oversampled modulator. FIG. 7 shows a modification of that
modulator to form a double-rate third-order oversampled modulator 70. This
modulator incorporates the structure of double-rate second-order modulator
60 of FIG. 6 with the addition of a double-rate first-order modulator 21
substantially identical to modulator 20 of FIG. 2, and therefore like
reference numerals identify identical elements in the two figures. In FIG.
7, modulator 21 includes a switched capacitor integrator 32 having
switches 71a and 71b which alternately sample the output signal of
integrator 30, and the sampled output signal is alternately applied to the
inverting input of a third operational amplifier 74. The output signal of
integrator 32 is supplied via a switch 78 to M-bit ADCs 76a and 76b, the
output signals of which are supplied to an M-bit 2-to-1 multiplexer 79.
The output signals of M-bit ADCs 76a and 76b are also supplied to
corresponding M-bit DACs 77a and 77b, the outputs of which are alternately
connected to input capacitors 72a and 72b by switches 71a and 71b,
respectively. Switches 73a and 73b function analogously to switches 23a
and 23b, respectively, in modulator 20 of FIG. 2.
The output signal of M-bit multiplexer 79 is multiplied by a gain factor G
in a digital multiplier 81. The output signal of multiplier 81 is supplied
to a digital subtractor 82. The output signal of L-bit multiplexer 29 is
delayed one cycle by a delay register 83, and the output signal of this
register is supplied to the subtrahend input of digital subtractor 82. The
difference output signal of digital subtractor 82 is supplied to a pair of
cascaded digital differentiators 84, each comprised of a one-cycle delay
register 85 and a digital subtractor 86. Finally, the output signals of
delay register 83 and the second of cascaded differentiators 84 are summed
in a digital adder 87 to produce the digital output signal of modulator
70.
The circuit elements 81 to 87 comprise a digital canceler. That is, the
difference between the two digital output signals from modulators 60 and
21 is exactly equal to minus the quantization noise of second-order
modulator 60. A double differentiated signal from cascaded differentiators
84 is added to the digital output signal of second-order modulator 60 to
effect the cancellation of the quantization noise of modulator 60. A more
detailed description of this canceler is set forth in the aforementioned
Ribner application Ser. No. 07/505,384 filed Apr. 6, 1990. This is but one
form of digital canceler and other implementations are possible.
In both FIGS. 6 and 7, L-bit quantizers are shown for generality; however,
it will be understood by those skilled in the art that for the case L=1
(i.e., 1-bit quantization), the auto-zeroed comparator circuit and
single-pole double-throw switch scheme shown in FIG. 4 would be
substituted for each ADC and DAC combination as shown in FIGS. 6 and 7.
Also in FIG. 7, M-bit ADCs 76a, 76b and M-bit DACs 77a, 77b are employed
in the event a different number of bits (or a different quantization
level) is used in each of the two cascaded modulators 60 and 70.
Where sufficiently fast quantizers (i.e., ADC and DAC combination) are
available, then double-rate operation can be achieved as illustrated in
FIG. 8 which shows, by way of example, a first-order double-rate
oversampled modulator 90. This modulator is similar to that shown in FIG.
2, except for the use of a double-rate L-bit ADC 96 and a double-rate
L-bit DAC 97. Use of the double-rate L-bit ADC eliminates need for the
2-to-1 multiplexer employed in the modulator of FIG. 2, the L-bit digital
output signal being taken directly from L-bit ADC 96. The clock waveforms
for the modulator shown in FIG. 8 are shown in FIG. 9. Since ADC 96 and
the DAC 97 are operated at double rate, they perform conversions on both
clock phases.
A further variation is introduced in FIG. 10 for situations where the ADC
is faster than the available DAC. In this embodiment, a double-rate ADC 96
is used, but a pair of single-rate DACs 97a and 97b are employed in the
feedback loops. A multiplexer, illustrated as a switch 98, alternately
couples the output of ADC 96 to DACs 97a and 97b. It will be understood
that operation of the modulator circuit shown in FIG. 10 is essentially
similar to operation of the modulator shown in FIG. 2. Also, it will be
understood that either of the approaches of FIGS. 8 and 10 can be
incorporated in the context of the modulator networks of FIGS. 6 and 7.
Although the modulator components, i.e., the integrators, ADCs and DACs,
have so far been illustrated with single-ended outputs, the third-order
sigma delta analog-t | | |
