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CROSS REFERENCE TO RELATED APPLICATION
This application is related to copending Gaudenzi et al U.S. patent
application Ser. No. 07/198,981, filed May 26, 1988, entitled
Bidirectional Buffer With Latch And Parity Capability, and assigned to the
instant assignee.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to memories employed in computer systems
and, more particularly, to accessing data stored in page mode memories
employed in such systems.
2. Description of Related Art
The demands on computer systems to achieve ever greater operating speeds,
increased effective processing power and greater overall performance
continue. One trend has been to increase the clock frequency of the
central processing unit (CPU) of the computer. This, of course, results in
a greater number of instructions being processed per unit time. However,
as clock frequency is increased, the access time associated with memory
must somehow be correspondingly shortened if the full benefit of the clock
frequency increase is to be realized. Otherwise, the access time
associated with reading data out of memory becomes a prominent limiting
factor constraining the effective performance of the CPU.
One approach to decreasing the effective access time required to read data
from memory is to use page mode memory. That is, memory is divided into a
plurality of pages, each page consisting of a row having a common row
address for the entire row. Each row of a page includes a plurality of
columns having corresponding column addresses. To access a particular
piece of data stored in such a page mode memory, the row address of that
data is supplied to the memory to enable selection of the page in memory
where the data is located. Then, the column address associated with the
data is supplied to the memory to enable selection of the particular piece
of data within the addressed row or page. Typically, the addressed data is
then read out to the data bus.
One example of a page mode memory is found in the IBM Personal System/2,
Model 80 computer. (Personal System/2 is a trademark of the International
Business Machines Corporation.) A simplified block diagram generally
representative of such a page mode memory computer system is shown in FIG.
1 as system 10. System 10 includes a central processing unit (CPU) 20 or
microprocessor to which an address bus 30 and a data bus 40 are coupled.
System 10 further includes a memory controller 50 to which address bus 30
and data bus 40 are coupled. A control bus 60 is coupled between CPU 20
and memory controller 50 such that control signals may be passed
therebetween. Memory controller 50 is coupled to at least one memory
module 70 which consists of random access memory (RAM). In this example,
memory module 70 is divided into pages which are 2K bytes long
(512.times.32 plus parity), each page by definition having the same row
address. Each page thus includes 2K column addresses. A data bus 80 is
coupled between memory controller 50 and memory module 70 to permit the
transfer of data therebetween.
A multiplexed MUX address bus 90 is coupled between memory controller 50
and memory module 70 so that row and column address information may be
passed from memory controller 50 to memory module 70. Multiplexed address
bus 90 has fewer lines than address bus 30 due to the multiplex nature of
bus 90 on which a row or page address is first supplied to memory module
90 during a memory access cycle and then, second, a column address is
supplied to memory module 90 later in that cycle. Memory controller 50
supplies Row Address Strobe (RAS) signals and Column Address Strobe (CAS)
signals to memory module 70 as seen in FIG. 1. The nature of the RAS and
CAS signals is described in the following discussion of the timing diagram
of FIG. 2.
FIG. 2 shows a timing diagram of a typical memory cycle associated with
computer system 10. For purposes of this example, it is assumed that CPU
20 desires to access or retrieve a first piece of data from memory 70 at a
predetermined data address therein. To actually access such information,
CPU 20 sends the data address to memory controller 50. Memory controller
50 effectively divides the data address into two portions, namely, the row
address (also known as the page address) and the column address. The row
address and the column address are multiplexed onto MUX ADDRESS bus 90.
That is, the row address is first provided to such MUX ADDRESS bus at 100.
The RAS signal is initially HIGH or OFF. It is noted that since negative
logic is employed in the timing diagram of FIG. 2., HIGH corresponds to an
OFF state and LOW corresponds to an ON state. The RAS signal goes ON at
105 to select the row address portion presently supplied to MUX ADDRESS
bus 90. In this manner, memory module 70 selects the particular page (row)
in which the addressed data is stored. RAS remains ON for the duration of
the first memory cycle and the following second memory cycle.
After RAS goes ON and the row address is selected in the first memory
cycle, the column address portion of the desired data is supplied to the
MUX ADDRESS bus at 110. The CAS signal is then driven ON at 115 to select
the column address portion presently supplied to MUX ADDRESS bus 90. At
this point the address is complete since both the row and column address
portions corresponding to the desired data have been supplied to memory
module 70. Memory module 70 then accesses the data thus addressed and
provides such data to memory data bus 80. The data on the memory data bus
80 becomes valid at 120 after a predetermined time delay, T.sub.D, occurs
after completion and selection of the address at 115. Microprocessor 20
then picks up the addressed data from data bus 40 of FIG. 1. Those skilled
in the art use the term T.sub.CAS to define the time delay between the
time at which CAS becomes active to the time at which the data becomes
valid on the memory data bus 80. The term T.sub.RAS refers to the time
delay between the time at which RAS becomes active to the time at which
the data becomes valid. More commonly, T.sub.RAS is referred to as the
"access time" exhibited by a particular memory device. For example, a
memory device with an 80 nanosecond access time exhibits a T.sub.RAS of 80
nanoseconds.
For purposes of this example it is assumed that a second piece of data
located in the same page or row as the above first piece of data is to be
accessed from memory module 70. Those skilled in the art use the term
"pipelining" to describe the act of changing the address, for example the
column address portion, prior to the end of the current memory cycle in
preparation for the next memory cycle. Pipelining itself saves time since
it permits address decoding circuitry in memory controller 50 to start
processing the address earlier than would otherwise be possible. An
example of such pipelining is seen in FIG. 2 where subsequent to the data
becoming valid at 120 and prior to the end of the first memory cycle at
125, the column address is changed to a new column address at 130, such
column address corresponding to the second piece of data. Since the second
piece of data to be accessed in the second memory cycle is in the same
page as the data accessed in the first memory cycle, the column address
portion changes at 130 while the row address portion remains the same.
This situation is referred to as a "page hit". Since it is not necessary
to resend the row address portion to memory module 70 when a "page hit"
occurs, valuable time can be saved in a page mode memory arrangement.
Before memory module 70 can select and actually use the column address
information now present on MUX ADDRESS bus 90, it is necessary to drive
the CAS signal OFF for a predetermined period of time referred to as the
CAS precharge 135. Those skilled in the art refer to the CAS precharge
time as T.sub.CRP. For a memory device with an 80 nanosecond access time,
a typical value of T.sub.CRP would be 15 nanoseconds. Once the CAS
precharge is completed, CAS is driven ON again at 140 such that the column
address portion of the second piece of data is selected by memory module
70. The address of the second piece of data is thus completed and the data
on memory address bus 80 becomes valid at 145 after a predetermined time
delay, T.sub.D, from completion and selection of the address at 140.
Microprocessor 20 then picks up the addressed data from data bus 40 of
FIG. 1. The second memory cycle ends at 150.
For purposes of this example it is assumed that a third piece of data
located in a different page or row than the first and second pieces of
data is accessed in a third memory cycle commencing at 150, a portion of
such third memory cycle being shown in FIG. 2. This situation is referred
to as a "page miss". That is, a new row address portion corresponding to
the location of the third piece of data must be provided to memory module
70. Such new row address portion appears on the MUX ADDRESS bus via
pipelining at 155. At the beginning 150 of the third memory cycle, RAS is
driven OFF in preparation for the new row address. The new row address is
actually selected when RAS is driven ON at 160. The remainder of the third
memory cycle is substantially similar to the first memory cycle in FIG. 2
with CAS precharge being provided at 165 near the beginning of the third
memory cycle.
From the above discussion it is seen that in the situation where a "page
hit" occurs in a page mode memory, a substantial amount of time is
consumed (reference the second memory cycle in FIG. 2) in conducting the
CAS precharge before the new column address portion can be used to
complete the new address and select the corresponding data.
As mentioned above, computer systems are being designed with higher and
higher clock speeds. Given that a memory cycle consists of a predetermined
number of clock pulses which become correspondingly shorter as the clock
speed increases, the time required for such memory set-up activities as
CAS precharge tends to occupy an ever increasing proportion of the memory
access cycle as the clock speed increases. One way to accommodate a
microprocessor which is operating at a very fast rate with respect to the
speed or access time of memory is to add wait states to the computer
system to effectively slow down the microprocessor to wait for data to be
accessed from memory. This course of action is generally undesirable
because it negates some of the benefits of increasing the clock speed of
the microprocessor.
BRIEF SUMMARY OF THE INVENTION
One object of the present invention is to provide a computer system which
is capable of operating at high clock speeds without resorting to
additional wait states while accessing memory.
Another object of the present invention is to decrease the access time
associated with page mode memories.
In accordance with one embodiment of the invention, a computer system is
provided including a page mode memory having an address bus and a data bus
coupled thereto. A processor, for example a microprocessor, is coupled to
the address bus and the data bus. The processor processes data in the
system and provides the memory with a first address signal during a first
memory cycle, such first address signal corresponding to a location in
memory of data to be accessed. The system includes a first control circuit
coupled to the memory for supplying the memory with a row address strobe
(RAS) signal during the first memory cycle and further includes a second
control circuit coupled to the memory for supplying a column address
strobe (CAS) signal to the memory during the first memory cycle and
subsequent to the RAS signal. A latching circuit is coupled between the
memory and the data bus for latching the data thus addressed for later
transfer on the data bus. The computer system includes a CAS precharge
circuit coupled to the memory for subjecting the memory to a CAS precharge
subsequent to latching the memory and prior to the end of the first memory
cycle.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified block diagram of a conventional computer system with
a page mode memory.
FIG. 2 is a timing diagram associated with one typical conventional page
mode memory.
FIG. 3 is a simplified graphic representation of the computer system of the
present invention.
FIG. 4 is a block diagram of the computer system of the present invention.
FIG. 5 is a timing diagram showing the timing of the memory portion of the
computer system of FIG. 3 as compared with timing of the memory portion of
the conventional system of FIG. 2.
FIG. 6 is a flowchart showing how memory accesses are implemented in the
computer system of the present invention.
FIG. 7 is a block diagram of the bi-directional latching circuit employed
in the computer system of FIG. 4.
FIG. 8 is a block diagram of the complete data buffer of FIG. 7.
FIG. 9 is a representation of the pin-out of the data buffer of FIG. 8.
DETAILED DESCRIPTION OF THE INVENTION
FIG. 3 shows a simplified representation of the computer system of the
present invention as including a computer system unit 200 to which a
monitor 205, a keyboard input device 210, a mouse input device 215 and a
printer output device 220 are coupled.
FIG. 4 is a block diagram of computer system unit 200. System unit 200
includes a processor 225, for example a 32 bit processor such as the Intel
80386 processor. A CPU local bus 230 is formed by a 36 bit address bus, a
32 bit data bus and a 10 bit control bus which are coupled between
processor 225 and a buffer 240 as shown in FIG. 4. A math coprocessor 245
such as the Intel 80387 coprocessor is coupled to CPU local bus 230 to
perform floating point operations to enhance system throughput.
System unit 200 includes a system local bus 250 coupled between buffer 240
and a buffer 253. The system local bus 250 includes a data bus, an address
bus and a control bus as shown in FIG. 4. Buffer 240 acts to buffer the
address bus of CPU local bus 230 with respect to the address bus of system
local bus 250. Buffer 240 also buffers the data bus and control bus of the
CPU local bus 230 with respect to the data bus and control bus of system
local bus 250. A CPU data cache 255, for example a data cache including
64K of memory, is coupled to the address and data busses of CPU local bus
230. A cache controller 260 such as the Intel 82385 cache controller, for
example, is coupled to the address and control busses of CPU local bus
230. Cache controller 260 controls the storage and access of frequently
used data which is stored in data cache 255 to effectively speed up the
operation of system unit 200. Cache controller 260 is also coupled to the
address bus of system local bus 250.
System unit 200 includes a bus control and timing circuit 265 coupled to
the address, data and control busses of the system local bus 250. The
system local bus 250 is coupled via a latch/buffer/decoder 267 to an
input/output (I/O) bus 270 which includes a 10 bit address bus, an 8 bit
data bus and a control bus. Buffer/decoder 267 provides I/O address latch
and I/O data buffer steering control. Buffer/decoder 267 decodes the
system local bus address and control signals, and provides "chip select"
and I/O command signals to the I/O bus 270. It will be appreciated that
"chip select" refers to selecting the particular device coupled to I/O bus
270 at which an operation is to be performed. I/O bus 270 is coupled to a
display adapter 275, a CMOS clock 280, a CMOS RAM 285, an RS232 adapter
290, a printer adapter 295 and, a 4 channel timer 300 for general
timekeeping functions. I/O bus 270 is further coupled to a diskette
adapter 305, an interrupt controller 310 and a read only memory (ROM)
which contains the system Basic Input Output System (BIOS).
A Micro Channel (TM) bus 320 having address, data and control buses therein
is coupled to system local bus 250 via buffer 253. The architecture of the
Micro Channel bus is described in more detail in the IBM PS/2 Model 80
Technical Reference Manual. In accordance with the Micro Channel
architecture, a central arbitration control point (CACP) 325 is coupled to
Micro Channel bus 320 and bus control and timing circuit 265 for purposes
of managing the Micro Channel multi device bus arbitration mechanism. The
connection of such central arbitration control point 325 and bus control
and timing circuit 265 actually forms part of the Micro Channel bus 320.
A plurality of Micro Channel sockets 330 are coupled to Micro Channel bus
320 as shown in FIG. 4 for receiving feature cards such as memory cards,
video adapters, DASD adapters, SCSI adapters and communications adapter
cards. One or more hardfile/floppy disk sockets 335 are coupled to Micro
Channel bus 320 to facilitate connection of a hard disk or floppy disk
(not shown) to bus 320. A direct memory access (DMA) controller 337 is
coupled to the address, data and control busses of system local bus 250
for the purpose of permitting peripherals such as hard files, floppy disk
drives and any Micro Channel DMA slave devices to have direct access to
main memory (described below) to avoid having to directly involve
processor 225 in data transfers between such peripherals and main memory.
A memory control circuit 340 is coupled to system local bus 250 as shown in
FIG. 4. The operation of memory control circuit 340 is fully described and
specified in the timing diagram of FIG. 5, described later. However, to
enhance understanding of memory control circuit 340, it is noted that
memory control circuit 340 actually includes three portions, that is, a
RAS/CAS decoder 345, an address decoder/multiplexer 350 and a data buffer
355. RAS/CAS decoder 345 is coupled at its input to the control bus of
system local bus 250. RAS/CAS decoder 345 takes address and bus cycle
definition signals from processor 225 and decodes them to extract memory
select and memory timing signals. RAS/CAS decoder 345 decodes RAS and CAS
signals. The RAS signal decoded by decoder 345 specifies which memory
bank, of 8 memory banks, (each bank including 1 megabyte organized as
256K.times.36 bits) is to be accessed during the current memory cycle. The
arrangement of these 8 memory banks into a memory 370 including modules
371, 372, 373 and 374 is described later. The CAS signal decoded by
decoder 345 specifies which byte or bytes of a 32 bit word stored in
memory 370 are to be accessed during the current memory cycle.
Memory control circuit 340 is coupled to the aforementioned memory 370 in
the manner described subsequently. Memory 370 includes 4 modules of random
access memory (RAM), namely modules 371, 372, 373 and 374 each of which
accommodates 2 megabytes of memory. In FIG. 4, modules 371-374 are
designated as dynamic random access memory (DRAM) single inline packages
(SIP) or DRAM SIP. Module 371 is populated with 2 Megabytes of memory and
is labelled "BASIC 2MB". The remaining modules 372-374 are fillable with
memory at the user's option and are thus labelled "OPTIONAL 2MB". The
RAS/CAS decoder 345 includes an output bus 380 having 13 separate lines on
which the RAS, CAS and WE signals are transmitted to each of memory banks
371-374 of which 8 lines are dedicated to RAS, 4 lines are dedicated to
CAS and 1 line is dedicated to WE. RAS/CAS decoder 345 generates a write
enable (WE) signal which designates whether a particular memory cycle is a
read cycle or a write cycle and provides that information to memory 370.
Each of modules 371-374 includes 2 megabytes of memory each megabyte of
which is divided into 512 pages or rows which are 2K bytes long each. That
is, banks 371-374 are configured as page mode memories.
Address multiplexer (ADDR MUX) 350 is coupled at its input to the 36 line
data bus of system local bus 250. When processor 225 desires to access a
piece of data stored in a location in memory 370, processor 225 transmits
the 36 bits of the address of that memory location to address multiplexer
350. Address multiplexer 350 derives the page address (row address) and
column address from the 36 bit address information and provides the page
address and column address to memory 370 via a multiplexed address (MUX
ADDR) bus 390 which couples address multiplexer 350 to memory 370. A 36
bit memory data bus 400 couples memory modules 371-374 of memory 370 to
data buffer 355. After memory 370 is addressed as above, the data at the
specified memory address is transferred to a memory data bus 400 which
supplies the data to data buffer 355 as shown in FIG. 4. On memory data
bus 400, 32 bits (D.sub.0 -D.sub.31) are dedicated to data and 4 parity
bits (P.sub.0 -P.sub.3) are dedicated to parity. Once the addressed data
reaches memory data bus 400, the data is buffered by data buffer 355 and
is then placed on the data bus of system local bus 250. Subsequently, the
data is passed to processor 225 via buffer 240 and CPU local bus 230.
The following discussion of the timing diagram of FIG. 5B describes in
detail the operation of memory control circuit 340 and memory 370. For
convenience and to permit ready comparison, the prior art timing diagram
of FIG. 2 has been repeated in the upper portion of FIG. 5 as FIG. 5A. For
purposes of discussion of the timing diagram of FIG. 5B, it is assumed
that processor 225 desires to access a piece of data stored at a selected
address or location in memory 370. This piece of data is referred to as
the first selected piece of data. It also assumed that after accessing the
first selected piece of data, processor 225 desires to access a second
selected piece of data at another memory location.
Processor 225 outputs the selected address at which the first piece of data
is stored to the data bus of CPU local bus 230. The selected address
consists of 32 address bits A.sub.0 -A.sub.31 and 4 byte enable bits
(BE.sub.0 -BE.sub.3) bits thus forming a 36 bit address in total. The 4
byte enable bits BE.sub.0 -BE.sub.3 are used to indicate which bytes (from
1 to 4) are to be retrieved from the (4 byte, 32 bit) data stored at a
particular address. After arriving on the address bus of the CPU local bus
230, the selected address is buffered by buffer 240. The selected address
is then transferred to the address bus of system local bus 250 and
provided to memory control circuit 340 and address multiplexer 350.
System unit 200 is arranged in this embodiment such that 9 bits of that 36
bit selected address correspond to the page address or row address (RAS
address) 410 of the data to be accessed. That is, bits A.sub.11 -A.sub.19
correspond to the RAS address. Page address 410 is timed to begin at the
start of the first memory cycle as indicated in FIG. 5B. Address
multiplexer 350 extracts this 9 bit page address 410 from the 36 bit
address and provides this 9 bit page address 410 to memory 370 via a 9
line MUX ADDR (multiplexed address) bus 390 which couples address
multiplexer 350 to memory 370.
At the beginning of the first memory cycle, the RAS signal from memory
control circuit 340 is high which corresponds to an OFF state in the
negative logic convention employed in FIG. 5B. After the page address 410
appears on MUX ADDR bus 390, memory control circuit 340 (via RAS/CAS
decode circuit 345) drives RAS low or ON at 415 as seen in FIG. 5B. In
this manner the page address to be used by memory 370 to access the
specified data is provided to memory 370.
After RAS has gone ON, memory control circuit 370, via address multiplexer
350, extracts the 9 bit column address 420 of the data from the 36 bit
address and provides that 9 bit column address 420 to memory 370 via MUX
ADDR bus 390.
That is, bits A.sub.2 -A.sub.11 correspond to such column address or (CAS)
address. As seen in the timing diagram of FIG. 5B, after the column
address 420 appears on MUX ADDR bus 390, memory control circuit 340 (via
RAS/CAS decode circuit 345) drives CAS low or ON at 425. In this manner
the column address to be used by memory 370 to access the specified data
is provided to memory 370. The page address and the column address of the
data are thus multiplexed onto the same 9 line MUX ADDR bus 390. The
remaining bits A.sub.17 -A.sub.31 are employed by the RAS decoder 345 to
indicate which one of modules 371-374 contains the first piece of data
which is being addressed.
At this point both the page address 410 and the column address 420
specifying the location in memory of the selected data have been provided
to memory 370. After a predetermined time delay T.sub.CAS from the time
CAS is activated or goes low, the data on memory data bus 400 becomes
valid at 430. The data is then immediately latched at 435 by bidirectional
latches (described later in more detail) contained in data buffer 355.
After the buffering/latching action of data buffer 355 has occurred, the
latched data (the first selected piece of data) is provided at 437 to the
data bus of system local bus 250 for transfer to processor 225.
Subsequent to latching the data at 435 in the first memory cycle (current
memory cycle) and prior to the commencement of the second memory cycle
(next memory cycle), a CAS precharge is conducted at 440. Once the CAS
precharge is commenced at 440, the data on memory data bus 400 becomes
invalid at 442 after a predetermined period of time has passed from the
commencement of CAS precharge. The latching circuits in data buffer 355
latch the data before it becomes invalid, that is, before 442 on the
memory data bus timing diagram of FIG. 5B. Those periods of time during
which the data on memory data bus 400 is invalid are indicated by
cross-hatching on FIG. 5B. The end of the CAS precharge defines the end of
the first memory cycle.
Processor 225 transmits the address of the second selected piece of data to
memory control circuit 340 along the same data path as that over which the
first selected piece of data travelled thereto. If memory control circuit
340 determines that the second selected piece of data to be fetched from
memory 370 is in the same page as the first selected piece of data, then
as seen in the timing diagram of FIG. 5B, during the CAS precharge at 440,
the column address supplied to MUX ADDR bus 390 is changed to the column
address of that second piece of data at 445. This column address change
occurs before the end of the first memory cycle.
Subsequent to this column address change, the CAS precharge is finished and
CAS is driven ON thus starting the second memory cycle at 450. The column
address corresponding to the second selected piece of data is thus
provided to memory 370. After a time delay T.sub.CAS, the data
corresponding to that column address and the already prescribed page
address becomes valid at 455 on memory data bus 400.
The data is then immediately latched at 460 by the bidirectional latches
contained in data buffer 355. After the buffering/latching action of data
buffer 355 has occurred, the latched data (now the second selected piece
of data) is provided at 465 to the data bus of system local bus 250 for
transfer to processor 225.
As will be described in more detail subsequently in the discussion of data
buffer 355, when the memory data latch control signal (LEAB0-3) is low,
buffer 355 operates in a transparent or passthrough mode. When the memory
data latch control signal is high, buffer 355 is storing data by latch
action.
The above discussion has described memory access in the situation where the
second selected piece of data is in the same page as the first selected
piece of data. However, if memory control circuit 340 determines that the
second selected piece of data is not in the same page as the first
selected piece of data, then the memory addressing process must start all
over again at the beginning of the first memory cycle. That is, since the
row address or page address is not the same for the second piece of data
as it was for the first piece of data, the new row address corresponding
to the second piece of data must be transmitted to memory 370 followed by
the new column address in a manner similar to that shown in the first
memory cycle of the timing diagram for the invention shown in FIG. 5B.
FIG. 6 is a flowchart which summarizes the process by which memory accesses
are conducted in system unit 200. A memory access begins when processor
225 employs address pipelining to output a current address at which data
is to be retrieved as per block 500 in the flowchart. The current address
is transferred to memory control circuit 340 by the bus structure in
system unit 200 in the manner already described. The current address is
decoded by memory control circuit 340 as per block 505. That is, a page
address and a column address are extracted from the current address.
The page address is then multiplexed onto the MUX address bus 390 as per
block 510, this event signifying the start of the current memory cycle as
per block 515. The RAS is then activated or turned on at block 520 such
that memory 370 selects the page address which is presently provided
thereto on MUX address bus 390. The column address is then multiplexed
onto the MUX address bus 390 as per block 525. The CAS is activated or
turned on at block 530 such that memory 370 selects the column address
which is presently provided thereto on MUX address bus 390. At this point
the address of the desired data stored in memory 370 is completely
specified and memory 370 transfers the data at the specified address to
memory data bus 390 as per block 535. The data is latched by the
bidirectional latches in data buffer 355 as per block 540 to preserve such
data momentarily. After the data is latched, the data is transferred to
system local data bus 250 as per block 545. A CAS precharge is then
conducted as per block 550 prior to the end of the current memory cycle.
The next address to be accessed is then decoded as per block 555.
A test is conducted in decision block 560 to determine if the next address
is located in the same page as that in which the prior address (formerly
the current address above) was located. If the next address is not in the
same page as the prior address, then process flow continues back to block
510 of FIG. 6 at which the next page address is multiplexed onto MUX
address bus 390. However, if the next address is located in the same page
as the prior address, then process flow continues to block 565 at which
the column address of the next address is multiplexed onto MUX address bus
390. Subsequently, the next memory cycle or second memory cycle is started
at block 570 once the CAS precharge has ended. That is, at the beginning
of the second memory cycle, CAS is activated or turned on as per block 575
such that memory 370 selects the column address which is presently
provided thereto on MUX address bus 390. At this point the address of the
desired data stored in memory 370 is once again completely specified and
memory 370 transfers the data at the specified address to memory data bus
390 as per block 580. The data is latched by the bidirectional latches in
data buffer 355 as per block 585 to preserve such data momentarily. After
the data is latched, the data is transferred to system local data bus 250
as per block 590. A CAS precharge is then conducted as per block 595 prior
to the end of the current memory cycle. The next address to be accessed is
then decoded as per block 600 after which flow continues back to decision
block 560 at which a decision is again made to determine if the next
address is in the same page as the last address.
One high speed latching type data buffer which may be employed as data
buffer 355 is shown in FIG. 7 in block diagram form. For clarity of
illustration, FIG. 7 shows one of four substantially identical modules
employed in data buffer 355 as module 610. Buffer module 610 includes an 8
bit port 615 which is coupled to data lines D.sub.0 through D.sub.7 of the
memory data bus 400. Buffer module 610 includes a data receiver 620
designated A REC which is coupled to port 615 as shown. Data receiver 620
is a buffer which acts as an interface between the 0 to 5 volt TTL signal
environment present on memory data bus 400 and the 0 to approximately 3
volt environment characteristic of the internal workings | | |
