According to the invention, a JTAG-compliant chip having a controller that receives data provided on the TDI input pin and forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip is able to verify whether the data was correctly received by the non-JTAG chip by reading back the data and comparing to the original data. A status bit or bits are shifted out on a TDO pin and used to determine what data will be shifted in next.

An interface allowing to transfer serial test data from a Test Access Port (TAP) to controllers located in several clock domains is described. The clock frequencies can be different from each other and do not need to be related in phase to each other or with the clock of the TAP. The interface is proven to work reliably as long as the clock frequencies used for the test controllers and registers is 3 times higher than the one of the TAP used to source the serial test data.

A boundary scan test circuit that includes Y scan flip-flops serially connected in a sequence from a first scan flip-flop to a Y.sup.th scan flip-flop and clocked with a system clock signal, and circuitry for providing scan input data to the first scan flip-flop synchronously with a test clock signal and for receiving scan output data from the Y.sup.th scan flip-flop synchronously with the test clock signal, wherein the test clock signal and the system clock signal have a test clock period to system clock period ratio that is equal to any fixed integer ratio M.

A data processing system (10) implements state machine (82) and register logic (80) such that no external control or data is required during execution of a dual scan path test operation. Prior to execution of the dual scan path test operation, a user of data processing system (10) initializes a system with a plurality of values which will be used during execution of the dual scan path test operation. After initialization, data processing system (10) executes the dual scan path test operation automatically and requires no additional information from the user.

The instant invention relates to complex integrated circuits incorporating circuits for internal testing. The test controller has: a finite-state machine or status register (RE1 to RE4), the parallel outputs of which are looped back to the parallel inputs via a logic (LCB) which is also able to receive external control signals (TMS, TCK, TRST); multiplexers (MU1 to MU4) associated with the cells of the status register to allow for operation of the status register either in series or parallel; and a control signal generating stage (GSC) connected to the output of the register to supply control signals for other elements of the test: circuitry depending on the state defined by the status register. According to the instant invention, it is proposed that the multiplexers be provided with additional inputs making it possible to store the state of at least certain control signals in these cells for the purpose of transmitting them later for observation. It thus becomes possible not only to test the states of the status register (to verify that the finite-state machine accepts all the states it is supposed to accept) but: also to test the control signals emitted by the controller in order to verify that the control signals emitted are the desired signals. Possible faults in the test circuitry itself are thus detected more rapidly.