There is disclosed a graphics display controller for controlling a display memory, which includes a display address register temporarily storing an address which is changed in a predetermined cycle during a display period, a first circuit for producing a first signal each time less significant bits of the address becomes the same value as each other, a second circuit for producing a second signal each time a horizontal scan line to be displayed changes, and a third circuit for producing a display memory access request signal in response to the first or second signal. The controller further includes a flag register and a mask circuit, this mask circuit masking the second signal to prevent it from being transferred to the third circuit when the flag register stores first information, and allowing the second signal to be transferred to the third circuit when the flag register stores the second information.
An image display system is provided with a difference calculator for calculating, when interlacing video signals are entered, differences between fields from the input interlacing video signals and non-interlacing video signals, into which the interlacing signals are converted when they are read out of a frame buffer, and a brightness controller for controlling the brightness of video signals in the after image field on the basis of the differences calculated by the difference calculator.
An improved VGA Controller with Arbitration Logic and method therefor is provided to enhance system performance by efficiently using the minimum amount of bus bandwidth required. This Controller includes a bus to the Frame Buffer that either the system CPU or the Display Controller may access and control. The Display Controller includes a Display FIFO which stores display data from the Frame Buffer for the Display Controller to use. This Display FIFO coupled with the Arbitration Logic makes it possible for the Display Controller to continue to output display data even when the system CPU is accessing the display data in the Frame Buffer. The Arbitration Logic attempts to keep the Display FIFO as full as possible such that a bus request by the system CPU can be immediately granted when received.
A display scaler of the present invention typically includes (a) a memory for sending data, (b) a first variable length buffer for receiving the data from the memory, (c) a first scaler for scaling the data in a first direction, (d) a buffer controller for controlling the first buffer, (e) a memory controller for controlling sending of the data from the memory to the first variable length buffer, and (f) a main display controller for sending control signals to the first scaler, the buffer controller, and the memory controller. The display scaler may further include (g) a second buffer for receiving the scaled data from the first scaler and (h) a second scaler for scaling the scaled data in a second direction. The present invention provides a method of generating a first image on a first display window and a second image on a second display window. The method may include the steps of: (a) sending first data corresponding to a portion of the first image; (b) storing the first data in a first storage; (c) sending second data corresponding to a portion of the second image; (d) storing the second data in a second storage; (e) scaling some of the first data vertically and horizontally; (f) transmitting the scaled first data for display; (g) scaling some of the second data vertically and horizontally; and (h) transmitting the scaled second data for display.
