A DRAM cell structure having a capacitance electrode with a tapered end surface is disclosed. The tapered end surface eliminates prior art structures formed during fabrication of the cell structure that decreased yield. The cell structure of this invention provides increased yield without increasing the number of process steps required to form the cell structure. A unique process for forming the capacitance electrode with a tapered end surface is also provided.
An upper electrode of a capacitor is structured to have its end surface recessed from an end surface of an interlayer insulating layer covering a surface of said electrode layer, at a position where the upper electrode faces a bit line contact portion. The upper electrode layer and the first interlayer insulating layer are patterned to have the same end surface shape. Subsequently, only a side surface of the upper electrode layer is etched and recedes by isotropic etching. The receding surface of the upper electrode layer and a side surface of said interlayer insulating layer are covered with a sidewall insulating layer. The bit line contact portion or a pad layer for a bit line contact is formed along a surface of the sidewall insulating layer. The sidewall insulating layer is formed thick by an receding amount of the upper electrode of the capacitor from the first interlayer insulating layer. Thus, distance between the upper electrode of the capacitor and the bit line contact portion is increased, and therefore a dielectric breakdown voltage therebetween to is also increased.
The semiconductor memory device with a stacked capacitor is disclosed. When the mis-align is generated in forming contact region 42 for contact between the storage electrode of the stacked capacitor and the source region 34, the ion-implantation process, with the same conductive type as that of the source region, is carried out, to form the another source region 48 under the bottom surface of the contact region 42, wherein the polysilicon layer on the substrate is used as the mask. The successive ion-implantation provides the diffusion region 58 capable of wholly surrounding the another source region 48, wherein the diffusion region 58 contains higher concentration than that of the substrate and simultaneously lower than that of the source region, with the same conductive type as that of substrate. On the other hand, when no mis-align is generated, the semiconductor memory device further comprises another diffusion region 58a formed below the source region 34a, the diffusion region 58a having the opposite conductive type to that of the source region. Thereby the memory device is provided with the improvement of the refresh characteristic and with decrease of the soft error rate.
A manufacturing method for a DRAM cell provided with a stacked capacitor is disclosed. The method including: (1) defining a switching transistor region by forming a field oxide layer upon a first conduction type semiconductor substrate; (2) forming source and drain regions of a second conduction type; (3) forming respective first conductive layers on a part of said field oxide layer and on a gate oxide layer over a channel region within the switching transistor region; and forming a first insulating layer; (4) forming a second conductive layer and removing parts of the second conductive layer which are over the channel region and the drain region; (5) forming an opening for exposing a part of the source region; (6) forming a third conductive layer on the substrate and overlapping the remaining portions of the second conductive layer, to provide a portion thereof having a saddle structure providing a gentle slope; (7) etching to remove portions of the second and third conductive layers; (8) forming a dielectric layer; and (9) forming a fourth conductive layer.
An upper electrode of a capacitor is structured to have its end surface recessed from an end surface of an interlayer insulating layer covering a surface of said electrode layer, at a position where the upper electrode faces a bit line contact portion. The upper electrode layer and the first interlayer insulating layer are patterned to have the same end surface shape. Subsequently, only a side surface of the upper electrode layer is etched and recedes by isotropic etching. The receding surface of the upper electrode layer and a side surface of said interlayer insulating layer are covered with a sidewall insulating layer. The bit line contact portion or a pad layer for a bit line contact is formed along a surface of the sidewall insulating layer. The sidewall insulating layer is formed thick by a receding amount of the upper electrode of the capacitor from the first interlayer insulating layer. Thus, distance between the upper electrode of the capacitor and the bit line contact portion is increased, and therefore a dielectric breakdown voltage therebetween is also increased.
A method for non-destructively determining the amount of undercutting in a hidden layer of material disposed on a substrate after device patterning by etching. The method involves forming at least two lines of etch resistant material of increasing width over the hidden layer of material of the substrate and inspecting the lines after etching for a given time period to determine how many lines have been removed. The width dimension of the largest removed line corresponds approximately to the amount of undercut for two sides in the hidden layer of material after etching for the given time period.
