A capacitance storage trench for a DRAM cell includes a trench having at least one sidewall, a bottom wall and a plurality of rods extending away from the bottom wall. The at least one sidewall, the bottom wall and the rods are coated with a capacitive dielectric layer. A layer of semiconductive material is disposed over the dielectric layer. The plurality of rods expand the overall surface area of the trench and thus, provide a significant increase in capacitance storage of the storage trench. The capacitance storage trench is formed in a method which includes the steps of forming a plurality of buried oxygen precipitates in a selected region of a substrate and using the oxygen precipitates as micromasks during a conventional trench etch process.

A MOS capacitor has a p-type silicon substrate, an n-type impurity diffusion area formed by implanting an impurity into a region of the silicon substrate, a silicon oxide layer formed on the diffusion area, and a polysilicon electrode formed on the silicon oxide layer. An impurity profile is formed in the region such that the concentration of the impurity increases from a surface common to the diffusion area and the silicon oxide layer towards the inside of the silicon substrate. The concentration of the impurity at the interface is less than or equal to 1.times.10.sup.20 cm.sup.-3, and a peak concentration lies at a depth of more than 0.05 .mu.m under the interface. This controls accelerated oxidization during the thermal oxidization and also controls the dependence of the capacitance on the voltage.

Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between two conductive layers. Other embodiments measure misalignment between diffusion regions and conductors and between diffusion regions and windows through which other diffusion regions are to be formed. A circuit in accordance with one embodiment includes row and column decoders for independently selecting mask-alignment detection structures to reduce the number of test terminals required to implement the detection structures.

An electrical alignment test structure enables monitoring and measuring misalignment between layers (or associated masks) of an IC. The alignment test structure comprises a target region and an alignment feature in different layers. The target region and the alignment feature may be formed in diffusion and polysilicon layers, respectively or in well and diffusion layers, respectively. In both embodiments, the alignment feature controls the size of a conductive channel in the target region. Misalignment can be checked by comparing channel resistance with a baseline (no misalignment) resistance. In another embodiment, the target region and alignment feature are formed in the diffusion and polysilicon layers, respectively, wherein the alignment feature controls the relative widths of the source and drain regions. Misalignment can be checked by comparing current flow with a baseline current. In another embodiment, the target and alignment regions are formed in the well and diffusion layers, respectively, to form a diode, wherein misalignment can be checked by comparing current flow through the alignment feature with a baseline current. Multiple test structures can be combined in an array in accordance with an embodiment of the invention. By configuring the test structures in two mirror-image sets, the array can measure the amount of misalignment between the well and diffusion layers.