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We claim:
1. A method for use in each channel (10) of a redundant channel control
system for gathering and communicating redundant data signals between
channels over cross-channel data links (64, 69), the method comprising the
steps of:
gathering one or more data signals (36, 48, 56 or 30) by means of one or
more corresponding devices (42, 46, 54 or 28);
storing the gathered data signals as data words in input/output (I/O)
memory (18) under the control of a Direct Memory Access Controller (14)
for transmission over the cross-channel data link (64);
transferring data words from the I/O memory (18) to a link transmitter (62)
under the control of a link interface controller (22) for said
transmission;
formatting the data words in data blocks, each block having an initial
command word having a command word identifier protocol followed by an
origination code and a starting address, the command word followed by a
variable number of other words, the first other word having a data word
identifier protocol followed by a word count, the second and remaining
other words each having a data word identifier protocol followed by data
words;
transmitting the transferred data words in the formatted blocks from the
link transmitter to link receivers (24) in all of the channels over the
cross-channel data links;
receiving the transmitted data word blocks in the link receiver;
providing, by means of the link interface controller, memory address
signals for storing the received data words in link memory (26) allocated
according to the channel from which the associated block of data words
originated and for storing the starting address in link memory in the next
available sequential memory location after the end of the previously
received block for providing a stop address according to the starting
address plus the word count and for storing in link memory the stop
address at the starting address and for storing, in link memory, each
subsequently received data word of the block sequentially after the
starting address.
2. A method for use in each channel (10) of a redundant method control
system for communicating redundant data between a plurality of channels,
comprising the steps of:
gathering channel-related data by means of one or more types of devices
(42, 46, 54, Or 28) for transmission in blocks of data words;
transmitting said blocks to the other ones of the plurality of channels by
means of a link transmitter (62) over cross-channel data links (64);
receiving transmitted blocks from other channels by means of a link
receiver (24);
storing received blocks in channel memory, allocated by channel, by means
of a link controller (22) wherein each received block has one or more
initial word signals at least having a group of channel origination code
signal bits ("origination code"), a number of start address signal bits
("start address pointer") and a series of word count signal bits ("word
count"), all remaining data words of each block each having a group of
data signal bits, wherein said step of storing a received block comprises:
storing the "start address pointer" obtained from each received data block
at the next available memory location following the last block stored in a
subsection of memory corresponding to the origin of the data block
received as indicated by the "origination code";
generating a stop address pointer by adding the magnitude of the "start
address pointer" to the "word count";
storing the stop address pointer at the address ("start address") pointed
to by the "start address pointer"; and
storing subsequently received data words in the corresponding data block at
sequential memory locations after the "start address".
3. A memory storage method for use in a redundant channel control system
for storing received data words grouped in blocks transmitted from a
channel to other channels, comprising the steps of:
receiving, by means of a link receiver (24) in each channel, a data block
transmitted from any of the redundant channels;
determining, in a link controller (22), the channel from which the received
data block originated; and
storing, by means of the link controller (22), the received block of data
words in a link memory (26) allocated according to the determination of
channel original wherein each block has one or more initial word signals
at least having a group of channel origination code signal bits
("origination code"), a number of start address signal bits ("start
address pointer") and a series of word count signal bits ("word count"),
all remaining data words of each block each having a group of data signal
bits, wherein said step of storing comprises the substeps of:
storing the "starting address pointer" obtained from each received data
block at the next available link memory (26) location following the last
bock stored in a subsection of link memory (26) corresponding to the
origin of the data block received as indicated by the "origination code";
generating a stop address pointer by adding the magnitude of the "start
address pointer" to the "word count";
storing the step address pointer at the address ("start address") pointed
to by the "start address pointer"; and
storing subsequently received data words in the corresponding data block at
sequential link memory locations after the "start address".
4. Memory storage apparatus for use in each channel (10) of a redundant
channel control system for storing asynchronously received digital words
grouped and transmitted serially in blocks from any channel to other
channels, comprising:
a link receiver (24), responsive to a block having a start address word, a
word count word, and a plurality of data words from the transmitting
channel, for storing the words of the block, for providing a transfer
request signal for each word and for providing the words in a series in
response to a corresponding series of transfer demand signals;
a link interface controller (22), responsive to said transfer request
signals for providing said transfer demand signals, for storing said
words, for determining the identity of the transmitting channel, for
providing a sequence of addressing signals for storing said start address
in the next available sequential memory location after the end of the
previously stored block, for providing a stop address by adding the start
address to the word count, for storing said stop address at the start
address, and for storing said data words starting at the next available
location after the start address and each subsequent data word in
sequential memory locations; and
a link memory (26), responsive to said sequences of addressing signals and
words, for storing said words at the addressed memory locations, the
memory thus being allocated for storage of blocks according to said
identity of the transmitting channel.
5. The apparatus of claim 4, wherein alteration or storage of words in the
link memory (26) is achieved only by receiving words from the link
receiver (66) through the link interface controller (22).
6. The apparatus of claim 4, wherein said link receiver is responsive to a
block transmitted from all of the redundant channels, including the
channel of said link receiver.
7. Apparatus comprising a plurality of channels, each channel comprising:
a plurality of data signal input means (42, 46, 54, 28);
a link memory (26);
a Direct Memory Access (DMA) memory (18);
a DMA controller (14) for transferring data signals received by any of said
input means to said DMA memory;
link transmitter means (62);
link receiver means (24);
a plurality of cross-channel links (64, 69) for interconnecting said link
transmitter means with said link receiver means and with similar link
receiver means in each other one of said plurality of channels; and
a link interface controller (22) for transferring data signals from said
DMA memory to said link transmitter means in data blocks for transmission
to all of said link receiver means over said cross-channel data link, said
link interface controller for formatting said blocks with a start address,
a word count, and data words, and for storing data blocks received by said
link receiver means of the related channel in said link memory by storing
the start address in the next available location after the end of the last
stored block, by storing at the start address a stop address and by
storing the data words at sequential locations, all within a segregated
portion of said link memory corresponding to the one of said channels from
which said data block was transmitted over said cross channel links. |
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Claims |
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Description |
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CROSS REFERENCE TO RELATED APPLICATIONS
The invention described herein may employ some of the teachings disclosed
and claimed in commonly owned co-pending applications filed on even date
herewith by Tulpule et al, entitled ACCESS ARBITRATION FOR AN INPUT/OUTPUT
CONTROLLER Ser. No. 06/924,647, now U.S. Pat. No. 4,959,782, and Ser. No.
06/924,643, entitled GENERIC MULTIMODE INPUT/OUTPUT CONTROLLER, which are
hereby expressly incorporated by reference.
1. Technical Field
This invention relates to digital communication systems and, more
particularly, to an input/output controller for gathering and distributing
data in a digital control computer system.
2. Background Art
In most digital control computer systems, the gathering and distributing of
data is a necessary activity that must be performed during each phase of
computations. This activity is usually delegated and controlled by an
Input/Output Controller (IOC). The IOC function contributes significantly
to the system's overhead since its associated hardware and/or software
elements diminish the overall performance and other capabilities of the
system available for performing the primary control computer functions.
The performance and other operational requirements of IOCs are usually
quite demanding and vary widely from application to application.
Consequently, there is a critical need in most digital control computer
systems for a generic, efficient and flexible IOC that can meet the
demanding and varying requirements of multiple applications with a low
overhead.
The implementation of an IOC function may take on many forms. For example,
an IOC might be constructed as a rather inflexible state machine
microprogrammed in PROM and designed to perform the gathering of inputs
and distribution of outputs in a predefined and repetitive manner. Such a
state machine could then be specifically tailored, i.e., microprogrammed,
to a particular mode of operation of the control computer system.
The resulting IOC, which would be simple to design, will operate in a
predictable manner and meet the needs of most single mode operations.
However, such an IOC would not meet the flexibility needs of a multimode
control computer system in which the data elements and the gathering and
distribution process itself must change either statically or dynamically.
Hence, there is a need for more flexible input/output controllers which
can retain some of the simplicity of the state machine approach.
At the other extreme, an IOC function might be implemented entirely in
software, in an embedded software programmable microprocessor. However, it
might be noted that the basic tasks of an IOC, namely, the movement of
data between a set of sources and destinations and the control of I/O
devices do not demand the complexities and complete flexibilities offered
by a micro-processor in such a completely software based approach.
Furthermore, the arithmetic and data manipulation capabilities of a
microprocessor are not essential for the data transfer operation of an
IOC. Thus, such a microprocessor-based IOC software tends to under utilize
the microprocessor and, for this reason, the microprocessor in such an IOC
usually ends up performing some of the primary control computing functions
which, in turn, can tend to interfere with the IOC's primary I/O control
capabilities.
The debate over which approach is better has been going on for some time
and is not expected to be resolved here.
However, in many applications requiring extremely rapid control of devices,
a microprocessor based approach is unsuitable. Some of the other
difficulties associated with a microprocessor based IOC approach in this
context are: (i) the need for design and verification of complex, high
performance software, such as required by a real time system, (ii) the
lack of autonomous, repeatable operations, and (iii) the usually larger
failure rates of the associated hardware.
A state machine sequencer based IOC, on the other hand, can be easily
microprogrammed in PROM and verified to perform a given set of data
transfer and device control operations autonomously. However, as mentioned
above, a state machine IOC is very inflexible and may not be cost
effective in terms of hardware, particularly if it is designed using
off-the-shelf I/O controller components.
In many systems, the IOC's are required to manage a special type of
interface, namely, digital links. The management of these data links
between many subsystems involves special capabilities unlike those
required for managing localized analog or discrete signals and interfaces.
In a redundant control computer system, for example, a common task
performed by an IOC involves the transfer of data over a serial data link
to and from a set of redundant channels and (sub)systems which may or may
not be computational frame or task synchronized. These transfers are
required to be error free. The transfers are required to occur at certain
specific times depending on events and usually involve a large number of
input and output signals such as voting plane signals and signals
indicative of intermediate results of computations.
An IOC, unlike a control processor, is not required to perform any
sophisticated handling of data, in terms of command response protocol,
data redundancy or consistency. What is required, in the context of
redundant data links, is an autonomous internal bus between the IOC and a
local processor's memory involving no control processor overhead in the
transmission and reception of data to and from other channels and systems
which may or may not be synchronized. Such a link interface IOC cannot be
used for managing sophisticated data buses such as the MIL-STD-1553, LAN,
etc., because they are always asynchronous and require sophisticated
protocol and data consistency management which are best performed by a
dedicated bus controller function embedded in a processor. Such
sophisticated links also involve considerable hardware overhead.
The gathering and distribution of data by any IOC requires access to memory
which is also being used by the control processor. This is most commonly
done in a direct memory access (DMA) mode where the processor is requested
access to the data/address buses and the data is transferred on receipt of
a bus grant signal. During this transfer interval, the processor is
essentially idle. This loss of real time by the processor linearly
increases with the number of data transfers by the IOC, to a point where
it can significantly affect the overall throughout capability of the host
processor. Another difficulty with this DMA approach is that the bus grant
signal is essentially asynchronous and may take more or less time
depending upon the processor and its current activity. If the bus grant
signal is held off for a long time, it can lead to loss of rapidly
arriving internal bus messages, particularly if they are asynchronous in
nature. A common solution to this problem is to buffer the incoming bus
data. However, this approach has a significant hardware penalty and can
only provide limited relief. Another, new approach, disclosed herein,
involves the use of dual port RAMs which can internally arbitrate between
two asynchronous data buses for memory accesses. However, this also has a
significant hardware penalty and, though it fulfills the need for an
autonomous bus between the IOC and the control processor's memory, it is
not always affordable.
In summary, there is a need for an Input/Output Controller function by
which data may be gathered and distributed and by which input/output
devices including data links, synchronous or asynchronous in nature, are
controlled in a flexible, autonomous and predictable manner without real
time penalty to the host control computer in the channel.
DISCLOSURE OF THE INVENTION
An object of the present invention is to provide the control of data links,
asynchronous or synchronous in nature, for the distribution and gathering
of digital data to redundant or other elements of a system in a manner
designed to provide flexibility, independence of communication format and
detectability of signals, messages and events.
Another object of the present invention is to provide a generic multimode
input/output controller (IOC) state machine which provides flexibility,
autonomy, predictability and simplicity in the gathering and distributing
of data.
According to a first aspect of the present invention, data is communicated
between redundant channels formatted in blocks having an initial command
word followed a code indicating its source or its intended destination in
a memory bank partitioned according to source channel, a starting address
and a variable number of data words. The blocks are transmitted between
each channel and all of the channels over cross-channel data links. Upon
reception, a stop address is generated for each block received for storage
at the start address or its equivalent. Memory addresses are also
generated for each data word received for storage in sequence starting
immediately after the start address. The next block received has its start
address placed immediately at the end of the previously received block.
According further to this first aspect of the present invention, an
appropriate communication link such as a simple serial link, e.g., using
Manchester or NRZ encoding, provides a sufficient degree of signal or
protocol error detection capability built into the transmitter and
receiver elements. Such buses are the ideal solution for an internal bus
between redundant channels and systems because they provide some degree of
error detection without the need for general purpose interfaces as in the
case, e.g., of a MIL-STD-1553 bus. The transfer operations are controlled
by the IOC which can be frame synchronized, if needed. However, these
links, such as the Manchester link, do not provide the flexibility of a
sophisticated link, such as MIL-STD-1553, in terms of distinguishing the
sources and destinations or controlling and monitoring the number of data
words sent in a message. In other words, each transmitted data item is
received by all connected receivers in a redundant system.
The data link disclosed herein may be embodied in a serial, Manchester type
link that significantly expands the capabilities of internal buses in
terms of these and other difficulties. However, the control of the link
transmitter and receiver functions by the IOC described in the patent does
not depend on the specific protocol of the Manchester or any other links
and is used here only to illustrate the concepts. The link provides the
capability of sending a block message containing a variable number of
words to a channel and placing them in desired locations. Each block of
words begins with a command word (distinguished from data words by a
different synchronizing pattern at the beginning of the word) to specify
the destination identification and the starting (sub)address for the
subsequent data words in the destination memory. The destination address
may also be compared and validated using the local channel address before
the message is considered acceptable. The starting address is then used by
the receiver, in combination with the IOC, to generate the memory
addresses for all subsequent data words within the memory address space
(Link RAM) allocated for the source channel. As each new data word is
received, the current address initialized to the starting address is
updated and the data is placed in sequential locations pointed to by the
value of the current address. The process is continued until all the data
words have been deposited. When a new command word is received the process
is then repeated starting at the location pointed to by the new starting
address. The starting address is deposited immediately after the last data
word of the last block.
The expected number of words in a block may also be placed in the block as
the first data word and used to determine the valid reception of the
complete block. Reception of an invalid block then freezes the link
receiver operation and causes an interrupt which can then be used by the
processor to identify and discard the invalid block by using the starting
address and the block count.
This very powerful ability to selectively update a desired portion of
another processor's memory in a fault-tolerent, asynchronous manner is a
key teaching of the IOC disclosed herein. When utilized in conjunction
with the menu select mode of the second aspect of the present invention,
disclosed below, it in effect permits the host CPU to be decoupled from
I/O processing so that there is no time relation between sequential memory
locations and the reception of messages at memory locations of particular
blocks.
In still further accord with this first aspect of the present invention,
the IOC controller described herein is capable of mapping the data
received from all redundant channels and other subsystems. This, for
example, may involve use of a unique channel ID code (discrete inputs)
which changes the RAM bank number to which each receiver's incoming data
is mapped by the link controller.
The present invention satisfies, for redundant systems, the need for an
autonomous internal bus requiring no control processor overhead in the
transmission and reception of data between channels or systems which may
or may not be synchronized. For example, a simple serial link using
Manchester or NRZ encoding provide sufficient error detection capability
which may be built into transmitter and receiver elements. Although the
present invention is not limited thereto, this will, according to the
present invention, in most cases, be the preferred internal bus between
redundant channels and systems.
The throughput capabilities of each of the control processors are
significantly enhanced without loss of flexibility, according to the
present invention by performing some of each's tasks via the IOC and by
eliminating the real time overhead associated with the DMA approach. The
present invention provides an IOC that can operate synchronously or
asynchronously in multiple modes using an autonomous internal bus
requiring no control processor overhead in the transmission and reception
of data to and from other channels and systems which may or may not be
synchronized.
These and other objects, features and advantages of the present invention
will become more apparent in light of the detailed description of a best
mode embodiment thereof, as illustrated in the accompanying drawing.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a functional block diagram of an input/output controller (IOC),
according to the present invention;
FIG. 2 is a block diagram illustration of an IOC Arbitration unit, such as
is illustrated in FIG. 1;
FIG. 3 is another block diagram illustration of an arbitration unit such as
is shown in FIG. 1;
FIG. 4 is a block diagram illustration of a DMA controller, such as is
shown in FIG. 1;
FIG. 5 is one example of a microcode word format and the types of fields
that can be used for bit mapping each of the categories selected to meet
the needs of a particular application;
FIG. 6 is a block diagram illustration of a link interface controller, such
as is shown in FIG. 1;
FIG. 7 is a pictorial representation of the manner in which data may be
stored in Link RAM;
FIG. 8 is a simplified flow chart illustration of the manner in which data
is received and handled by the Link Interface Controller of FIGS. 1 and 6;
and
FIG. 9 is an illustration of three clock periods, corresponding to one
machine cycle of a particular signal processor.
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a functional block diagram of an input/output controller (IOC)
10, according to the present invention. An IOC Data/Control Bus 12 is
shown connected to various components of the IOC including a Direct Memory
Access (DMA) controller 14 for controlling transfers between a DMA RAM
Bank 18, within an IOC RAM 16 and a number of input/output devices 20 via
the IOC Data/Control Bus 12; a link interface controller 22 for
controlling transfers between a number of link receivers 24 and a
partitioned link RAM Bank 26 via the IOC Data/Control Bus 12; an IOC
Arbitration unit 28 for arbitrating access to the IOC RAM 16 as between a
host CPU (not shown, which gains access to the IOC RAM via a CPU
Data/Control Bus 30) and the controller portions of the IOC, i.e., either
the DMA Controller 14 or the link interface controller 22. The CPU is
always granted access priority and, in fact, the operation of the IOC,
according to the present invention, is transparent to the CPU as described
in more detail below.
The IOC 10 of FIG. 1 also include one or more Health/Status and control
registers 32 for storing information concerning the present health, status
and control of the IOC operations.
The DMA controller can control a variety of input/output devices such as
those shown in FIG. 1. The devices 20 controlled by the DMA Controller 14
may include an input Multiplexer 34 responsive to a plurality of analog
input signals from internal subsystems on an input line 36; an output
Multiplexer 38 which provides analog output signals on a line 40 for use
by external subsystems; a converter 42 responsive to analog input signals
on a line 44 from the input Mux 34 for providing Analog/Digital,
Synchro/Digital, or Frequency/Digital conversions; a Disk/Terminal
Controller 46 for receiving digital data words signals on a line 48 from
an external terminal/controller, and for providing digital data signals on
the line 48 from the host CPU for the purpose of controlling the external
subsystem; a Digital/Analog Converter 50 for converting digital signals
from the IOC Data/Control Bus 12 into analog signals on a line 52 for
distribution to external subsystems via the output Mux 38 for the purpose
of controlling them; a discrete input signal conditioner 54 responsive to
a plurality of discrete input signals on a line 56 from external
subsystems for the purpose of monitoring their activities; a discrete
output unit 58 for providing discrete signals on a line 60 to the external
subsystems for the purpose of controlling them; one or more link
transmitters 62 for providing serial output data on a plurality of serial
output lines (links) 64 to the other channel(s) or subsystems in the
system; one or more link receivers 24 responsive to a plurality of input
signals 68 from links 69 from the various channels or other subsystems and
as conditioned by interface 70. The interface unit 70 may be provided in
conjunction with the link receiver(s) 24 for the purpose of conditioning
the serial input data on lines 69 constructing the data words.
The IOC Link RAM Banks 26 may be partitioned into several memory spaces,
each corresponding to one of the redundant channels or subsystems in the
control system. The Link RAM Bank 26 shown in FIG. 1 has 6 such areas,
indicating that there may be redundant channels or subsystems in the
control system. The IOC DMA RAM Banks 18 may likewise be partitioned into
an A/D & D/A section for storing the incoming and outgoing digital words,
respectively; a discrete I/O section for storing the discrete words
gathered and distributed; and, a CPU deposited section for the purpose of
storing intermediate digital words to be transmitted to other subsystems.
As mentioned, the block diagram of FIG. 1 is merely a functional diagram
and does not necessarily depict, nor should it be interpreted as limiting
the IOC of the present invention to the exact interconnections or devices
pictured in the IOC 10 of FIG. 1. For example, referring now to FIG. 2,
the IOC Arbitration unit 28 may be set up such that the CPU Data/Address
Bus 30 interfaces with a Multiplexer 74 and an Arbitration Logic unit 76
which arbitrates access to the DMA RAM Banks 18 as between the DMA
Controller 14 and the host CPU. As mentioned above, the host CPU is always
granted access. However, any CPU accesses which might consume more than
one machine cycle are disallowed. When the DMA Controller 14 requests an
access on a line 16, it is granted access to the DMA RAM Banks 18 only if
the Arbitration Logic 76 is certain that the CPU will not be requesting
access during the time that it takes for the DMA Controller 14 to gain the
requested access and complete its task.
Similarly, the IOC Data/Control Bus 12 of FIG. 1 can be thought of slightly
differently, as shown in FIG. 3 with respect to the Link RAM Banks 26,
while still retaining functional equivalency to the arrangement shown in
FIG. 1. Thus, the Link Interface Controller 22 receives data from Link
receivers 24 and requests access by means of a request signal on a line 78
of the IOC Arbitration unit 28. If the CPU Data/Address Bus 30 is not
requesting access to the Link RAM Banks 26 and will not be doing so during
the time that it will take for the Link Interface Controller 22 to gain
access and complete its task, then Arbitration Logic 80 will grant access
via a multiplexer 82.
Thus, it will be observed that the functional block diagram of FIG. 1 may
be arranged and rearranged in various ways to accomplish the same ends.
Therefore, it will be understood by those skilled in the art, that the
teachings contained herein may be implemented in a wide variety of IOC
structures and architectures. The basic teachings disclosed herein,
however, will still be present. In connection with this thought, it will
be observed at this time that the architectures disclosed in FIGS. 4 and 6
for, respectively, a DMA Controller and a Link Interface Controller are
similarly merely two examples of many such architectures which could be
constructed using the teachings of the present invention.
Referring now to FIG. 4, a DMA Controller 14 is there illustrated in
simplified block diagram form. A DMA RAM 18 is illustrated interfacing
with the DMA Controller 14, as in FIGS. 1 and 2, except with a different
architecture. Of course, as mentioned above, the teachings contained
herein will be broadly applicable to a wide variety of DMA controller
architectures not necessarily restricted to those disclosed in FIGS. 1, 2
and 4.
The main function of the DMA Controller 14, or "PROM Sequencer," is the
transfer of data between I/O devices over an I/O data bus 86 and the DMA
RAM 18 and/or the Link Transmitter(s) 62. Thus, it will be understood that
the I/O data bus 86 of FIG. 4 is functionally comparable to the
input/output lines 36, 40, 44, 48, 52, 56, 60 and 64 of FIG. 1. Thus, the
bus transceiver 88 in FIG. 4 will be connected to the devices 20 of FIG.
1. The IOC Data/Control Bus 12 of FIG. 1 is comparable to a data bus 90,
an address bus 92 and a number of control busses and signals including
lines 94, 96, 98, 100, 102, 104, 106, 108, and 110, to be described in
more detail below. A CPU address bus 30a and a CPU data bus 30b are
together comparable to the CPU Data/Address Bus 30 of FIGS. 1 and 2.
The DMA Controller 14, in the embodiment shown herein, is capable of
controlling up to 32 source and 32 destination devices as constrained, in
the particular embodiment shown, by the 5 bits (S0-4 and D0-4,
respectively) dedicated for this purpose (see FIG. 5) in the RAM READ and
RAM WRITE operations to be described below.
The PROM Sequencer or DMA Controller 14 is implemented as a state machine
that generates address and control signals from the microcode defined in
FIG. 5 which may be resident in PROM 120. Sequencer operations can be
organized into sequences of microcoded words of variable sizes. These
micro sequences can be chained together either sequentially (default
mode), selectively (menu mode) or individually (direct mode) to form
longer sequences of IOC operations. A default block occupies a fixed
address locations in the PROM 120.
Each microcoded operation may be defined by a 24-bit-wide word, as
described for but not limited by the particular embodiment disclosed. It
should also be noted that the format of the microcode word of FIG. 5 is an
example of the types of fields that can be used. The size, definition or
range of possible operations is certainly not limited to those disclosed
in FIG. 5 and can be tailored to meet the specific needs of the
application. There are 4 catagories of operations disclosed for the
particular embodiment illustrated:
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