An image information control apparatus includes a first system for recognizing scanning of a position of image information, and a first memory unit for, when the first system recognizes scanning of the position of image information, detecting and storing an address accessed to an image information storage with, the access being started by the recognition in units of lines in a scanning direction. In addition, a second memory unit stores a line address detected and stored for the first time, a second system compares contents of the first system for recognizing scanning of the position of image information with contents of the second memory unit, and a third system interrupts the function of the first system on the basis of the comparison result of the second system. A fourth system interrupts the function of the first system when drawing processing, control of which is started by scanning the position of image information, is ended.

A videographics display system includes a graphics processor and a video RAM memory including a first portion storing video information and a second portion which is utilized for non-video information such as program information, message buffers, font tables, etc. The second portion includes dispersed memory regions formed by row portions which are not used for video information. The system includes multiplexing means effective to address the second memory portion by contiguous addresses.

A Video-RAM semiconductor memory device comprised of a RAM army having an address input for inputting row, column, and target addresses, and a serial access array having a serial output port. The Video-RAM has address/control logic which detects a stimulus such as a RAS clock from an external controller indicating a coarse timing location for a data transfer between the RAM array and the serial access array. The control logic then provides control signals, that are internally synchronized with a serial clock, and that occur during a period that a tap pointer is equal to a value one less than a programmable target value or an input target address. This causes a row in the RAM array corresponding to an input row address to be transferred between the RAM array and the serial access array.

A random access memory has an access time which is longer than the period of read input signals, for example digital video data signals, such that it cannot respond directly to the input signals. The memory has two read address inputs and two outputs which are arranged as separate channels, each of which can access any location in the memory. The access time of the memory is shorter than two input signal periods. The input signals are applied alternatingly to the read address inputs, and output signals constituted by data stored at addresses corresponding to the input signals are produced at the memory outputs by an arrangement of clocked latches such that, although two input signal periods are used for accessing each memory location, the alternating accessing using two channels enables the memory to produce output signals having the same period (at the same frequency) as the input signals. Additional elements are provided to enable writing to the memory using the alternating channel arrangement, and also to enable memory locations to be unconditionally interrogated while responding to a stream of read input signals.

A random access memory has an access time which is longer than the period of read input signals, for example digital video data signals, such that it cannot respond directly to the input signals. The memory has two read address inputs and two outputs which are arranged as separate channels, each of which can access any location in the memory. The access time of the memory is shorter than two input signal periods. The input signals are applied alternatingly to the read address inputs, and output signals constituted by data stored at addresses corresponding to the input signals are produced at the memory outputs by an arrangement of clocked latches such that, although two input signal periods are used for accessing each memory location, the alternating accessing using two channels enables the memory to produce output signals having the same period (at the same frequency) as the input signals. Additional elements are provided to enable writing to the memory using the alternating channel arrangement, and also to enable memory locations to be unconditionally interrogated while responding to a stream of read input signals.