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BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of making and testing integrated circuits, and a device used to perform such testing.
2. Description of the Prior Art
Integrated circuits (ICs) comprise active and passive elements such as transistors, diodes, resistors, and capacitors, that are interconnected in a predetermined pattern to perform desired functions. The interconnections are effectuated by means
of metallization layers and vias. A "via" is a hole through an insulation layer in which conductor material is located to electrically interconnect one conductive layer to another or to an active or passive region in the underlying semiconductor
substrate. Present day technology generally employs two metallization layers that are superimposed over the semiconductor wafer structure. Integrated circuits and assemblies have become more complex with time and in a logic circuit, the number of
integrated circuit logic units (ICLUs) and interconnects on a given size die have been substantially increased reflecting improved semiconductor processing technology. An ICLU can be a device (such as a transistor), a gate (several transistors) or as
many as 25 or more transistors and other devices. As is well known in the art, these conductive contact points have a typical center-to-center spacing of about 6 to 15 microns (.mu.m).
Standard processing to make logic structures (e.g., gate arrays) includes first fabricating as many as half a million transistors comprising a quarter of a million gates per die. Each semiconductor wafer (typically silicon but sometimes of other
material such as gallium arsenide) includes many die, for example, several hundred. In one type of gate array, for example, the transistors are arrayed in rows and columns on each die, and each transistor is provided with conductive contact points
(typically metal but sometimes formed of other conductive material such as polycrystalline silicon), also arrayed in rows and columns.
In the prior art, the next step is to use fixed masks to fabricate the conductive layers (sometimes called "metallization layers"), to connect together the individual gate-array devices. Typically two or sometimes three metallization layers are
used.
After this, the completed die is tested. If any of the devices on the die are defective, that die will fail an exhaustive test and be scrapped. Therefore, the more transistors per die the lower the manufacturing yield. In some cases redundant
sections of a circuit are provided that can be substituted for defective sections of a circuit by fuses after metallization. Typically such redundant sections can be 5% to 10% of the total circuit.
SUMMARY OF THE INVENTION
An object of this invention is to provide an improved test procedure for integrated circuits to increase production yields, by testing a circuit at the ICLU level (hereinafter called "fine grain testing"), compared to conventional testing at the
functional IC or die level.
Another object is to permit the fabrication of very large integrated circuits, in terms of the number of ICLUs or devices per circuit.
The present invention improves on prior art by testing each ICLU prior to metallization. Redundant ICLUs are provided on the die to substitute for those found to have defects. Then the metallization layers are fabricated so as to exclude
defective ICLUs and substitute good ones from the redundant group and render the circuit operable. The present invention uses a fine grain testing approach, by testing at a low level of complexity.
One key to the present invention is a specially fabricated flexible test means made of flexible silicon dioxide in one embodiment and including multi-layer metal interconnects and microscopic test points. The flexible tester means includes a
tester surface, connected to test equipment, that permits testing of each device. Then by CAD (computer aided design) means, each die is metallized and the metal layer is patterned by suitable means, such as E-beam and Ion-Beam processing, to fabricate
discretionary metallization interconnect layers of individual gate array devices.
The tester surface is formed on a standard silicon wafer typically by means of a low stress chemical vapor deposition process. The tester surface includes its own metallization layers. On one side of the tester surface are thousands of probe
points to contact the contact points on the wafer under test. The tester surface is a special flexible form of silicon dioxide which can be pressed flexibly against the wafer under test to achieve good electrical contact.
By eliminating defects at the device level, process yield is vastly increased -- for example to about 90% regardless of die size, in contrast to much lower yields using prior art technology. The present invention also allows successful
fabrication of very large die compared to conventional technology.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 shows a section of a gate array wafer and the device contacts.
FIGS. 2--3 show a top and side view of part of the tester surface.
FIGS. 4(a) and 4(b) show the test procedure.
FIG. 5 shows the fluid pressure test assembly.
FIG. 6 shows an exploded view of the wafer and tester surface.
FIGS. 7-12 show the steps to fabricate the tester surface.
FIGS. 13-15 show the steps to fabricate another embodiment of the tester surface.
FIG. 16 shows how nine die can form one super die.
FIG. 17(a) shows a tester surface.
FIGS. 17(b) to 26 show various probe point structures.
FIGS. 27(a) to 27(h), 28(a) to 28(h), and 29 show fabrication of probe points.
FIGS. 30, 31 show tester surfaces.
FIG. 32 shows an active matrix probe point surface.
FIG. 33 shows a polysilicon film for a flexible tester surface.
FIGS. 34, 35 show tester head assemblies.
FIGS. 36 to 41 show discretionary patterning for IC fabrication.
FIGS. 42(a) to 42(d) show repair of IC traces.
Each reference numeral when used in more than one Figure refers to the same or a similar structure.
DETAILED DESCRIPTION
As state above, the prior art fabricates a plurality of transistors on a die, interconnects the transistors to form desired logic, tests the entire die, and scraps the die if the logic doesn't work. In the present invention, after fabricating
the transistors exactly as before, the transistors or ICLUs are tested individually. Then the interconnect scheme is modified, if necessary, by CAD means (of well known design) to bypass defective transistors or ICLUs and substitute, logically speaking,
replacement ICLUs. Then the metallization layers are deposited, and patterned in accordance with the modified interconnect scheme typically by E-beam (Electron-beam) lithography, instead of the masking process of the usual conventional technology. Thus
each die has its own unique interconnect scheme, even though each die is to carry out the same function as the other die.
The present invention in one embodiment begins with a gate array conventionally fabricated on a silicon or GaAs wafer. The gate array transistors are arrayed in columns and rows on the wafer surface 1, and the active regions of each transistor
are provided with contact points such as 2-1 to 2-32 which are in columns and rows also as shown in FIG. 1 (not all contact points are numbered). Redundant (or extra) devices are designed into each column, with a redundancy factor dependent on the
expected yield of the individual transistors or ICLUs being tested.
The surface of the wafer 1 is optionally planarized with a cured layer of polymide 0.8 to 1.5 micron thick if the step heights between contact points are greater than 0.5 microns. (The contact points 2-1 to 2-32 are masked from the polymide
layer, to create a via over each contact point free of polymide, and metal is deposited to fill the via.)
The fabricated (but not metallized) wafer 1 is now ready for testing. In the described embodiment, only one column of transistors on each die is tested at a time, although testing more than one column per step is possible. For a die of typical
complexity this requires making contact with all of the perhaps 10,000 or so contact points such as 2-1 to 2-4 in one column simultaneously, and then stepping across all 100 or 200 or more columns in each die, to totally test each die in step-and-repeat
fashion. Each contact point such as 2-1 is small -- usually 4.times.4 microns. Each wafer contains a plurality of die, the exact number depending on the size of the wafer but typically being in the hundreds.
The flexible tester of this invention includes a tester surface 10 (described in detail below) as seen in FIG. 2 which includes a series of tester surface contact points including 15-1, 15-2 (which are arranged to contact on a one-to-one basis
the corresponding contact points in a column on the die under test) and a complete wiring interconnection, including a testing array which includes contacts 16-1, 16-2 and 16-3 and interconnect pathways 17-1, 17-2 and 17-3 as seen in FIG. 3, at various
levels 22, 23, 24 in the tester surface. The tester array which includes contacts 16-1, 16-2 and 16-3 connects to a conventional tester signal processor as shown in FIG. 4a having line driver logic circuits for accessing serially or in parallel the
devices under test. The driver logic signals are programmed separately in a well known manner and are multiplexed between testing array contacts 16, providing programmable input/output means for supplying diagnostic signals to the transistors or ICLUs
under test. Therefore, all the wafer contact points in one column can be accessed in one physical contact step of the transistors or devices to be tested.
The wafer 1 under test and the tester surface 10 are disposed on a support 26, as shown schematically in FIG. 4(a), for test purposes, to electrically connect the contact points on the tester surface 10 and corresponding contact points on the
wafer 1. FIG. 4(b) shows the test procedure in process-flow format. A fluid well or bladder (not shown) is used to exert an uniform pressure over the flexible tester surface 10 (FIG. 4(a)) in order to conform it to the surface of the wafer 1 under test
and to ensure that the numerous corresponding contact points on the tester surface 10 and the wafer 1 come together and make firm electrical contact. This is possible due to the fact that the surface of the wafer 1 under test typically has a controlled
total runout flatness within 6 to 10 microns across its complete surface. Secondly, the tester surface 10 is less than 15 microns thick and typically 1.5 microns thick and of a very flexible material, such as low stress silicon dioxide. Thirdly, the
metal contact points are the highest raised surface features on either the tester surface 10 or the surface of the wafer 1 under test, and are of a controlled uniform height typically between 2 and 6 microns.
The wafer 1 under test as shown in FIG. 4(a) is mounted on an x-y motion table (not shown). Movement of the table in the x-y directions positions the wafer for test by alignment of the contact points such as 15-1 and 15-2 of the test surface 10
(FIG. 2) with the corresponding device contact points such as 2-1 and 2-2 of the wafer 1.
During the test procedure as shown in FIG. 4(a), the wafer 1 under test is retained by suction in a substantially planar fixed position, by means of the support 26 illustrated in FIG. 4(a) and in FIG. 5. Use of suction to hold a wafer in place
is well-known. Tester surface 10 is mounted on a support ring 36 (as described below) to provide mechanical support and electrical connections, as shown in FIG. 5. The tester surface 10 is urged uniformly toward the wafer 1 under test by a fluid well
or bladder 38 immediately behind tester surface 10. A solenoid (not shown) is provided for macro control of the pressure exerted by the fluid in the fluid well 38 on tester surface 10. The depth of fluid well 38 is less than 100 mils; this is the
distance between the back of tester surface, 10 and piezoelectric pressure cell 40.
Piezoelectric pressure cell 40 is a layer of material about five-hundredths of an inch (one millimeter) thick that will expand about one-half micron when voltage is applied to the piezoelectric material. The applied pressure on the back of the
tester surface 10 is only a few grams per square centimeter. Piezoelectric pressure cell 40 provides the last increment of pressure on the fluid and in turn on the back of tester surface 10 to achieve good electrical contact between the contact points
such as 15-1 and 15-2 on tester surface 10 and the contact points such as 2-1 and 2-2 on wafer 1. The fluid is provided to the assembly through fluid port 46 which is connected to a fluid reservoir (not shown). The support ring 36 includes computer
cabling attachment sites 48 and multiplexer circuits 50. The support ring structure is described in more detail below.
As described above, mechanical positioners (i.e., x-y table aligners and conventional mechanical vertical positioners, not shown) bring the wafer 1 to within a few mils of the tester surface 10 and make a first approximation of the alignment of
contact points through a conventional optical aligner (not shown). The optical alignment is performed in a manner similar to that used by present semiconductor mask aligners, by using alignment patterns in predetermined positions on both the wafer 1
being tested and the tester surface 10. Only the pressure of the fluid moves the tester surface 10 the one or two mil distance separating the tester surface 10 and the wafer 1 to be tested in order to gain physical contact. FIG. 6 illustrates in an
exploded view wafer 1 and tester surface 10 being moved by fluid pressure from fluid well 38 just before wafer contact points such as 2-1 and 2-2 make contact with corresponding tester surface contacts such as 15-1 and 15-2.
In an additional alignment method, a small area (not shown) with a pattern of alignment contact points of various sizes up to 1 mil (25 microns) square and positioned at two or three corresponding alignment sites on both the wafer 1 and the
tester surface 10 is then used as an electrical circuit feedback system. The feedback system, starting with the largest contact points at each site and moving progressively to the smallest, determines the accuracy of the alignment and makes appropriate
micron sized adjustments under computer control to within sub-micron x-y alignment accuracy.
In the described embodiment, the fluid in the test surface assembly is Florinert from DuPont. Any alternate fluid with similar nonconductive and nonreactive properties could be substituted.
After an entire wafer 1 has been tested, it is removed and another wafer moved into position to be tested.
The data resulting from the tester signal processor is a list of the location of each defective transistors or ICLUs. This list is automatically communicated to the conventional CAD means from the tester signal processor as shown in FIG. 4. The
CAD means then, by special software algorithms works out an interconnect strategy for each die. Therefore, the master placement scheme of the net list is modified in terms of the placement of the defective ICLUs so as to bypass the defective ICLUs and
interconnect defect-free ICLUs from the stock of redundant ICLUs.
The invention uses two alternative software algorithms: recomputation of metallization trace routing or a CAD rip-up router.
The first alternative is the well-known and commercially available recomputation of the metallization trace routing for all affected layers of a specific IC after it has been tested. The routing is performed automatically with CAD software.
This routing procedure requires that sufficient defect-free redundant ICLUs have been allocated in the master placement of ICLUs and that the redundant ICLUs can be routed into the circuit given the potential restrictions that the number of metallization
layers may present. The software that precedes this processing performs the entry into a CAD system of the placement net-list change commands that direct the substitution of the defective ICLUs with available redundant ICLUs. These change commands are
specific to the CAD system that is selected for use, and the commands issued are similar to those a circuit designer would enter if making an ICLU placement select in a design change when using a gate-array.
This recomputation routing approach makes substantial requirements on computing resources. However, super-minicomputers presently available are sufficient to meet the computational requirements.
The second software alternative, a CAD rip-up router, takes advantage of the knowledge that the defects occurring in current bulk silicon semiconductor processes are few in number and are localized (i.e., the defects only affect one or two ICLUs
at any particular defect site), and of the fine grain ICLU structure. The fine grain level of testing minimizes the area necessary for redundant ICLUs and the complexity of the placement and routing changes that must be effected to correct for defective
ICLUs. Wafer or large ICs that indicate larger than normal numbers of defects or defects that are large in affected area when tested by testing equipment will cause the wafer to be rejected as outside of the acceptable bulk manufacturing standards which
are typical of all existing IC lines. The number of defects to be expected with standard available silicon wafers is approximately five per cm.sup.2 currently. This means that approximately five or less ICLUs can be expected to be defective per
cm.sup.2. The number of defects per cm.sup.2 increase as device feature sizes decrease, but not dramatically, as indicated by the current industrial use of 0.8 micron geometries for 4 Megabit memory devices, which will soon be in limited production.
This rip-up router software process approach takes advantage of this wafer ICLU defect density characteristic by employing a CAD rip-up router. This CAD software tool has only become available recently and heretofore was only used during the
design phase of a large IC in an effort to conserve designer and computer time. The rip-up router attempts to make local changes to existing IC metallization layout and, therefore, avoiding the expense of recomputing the complete IC's metallization
trace routing. The rip-up router is an automatic tool; it accepts change commands to the ICLU placement net-list and then computes changes to the IC's metallization database. This modified IC metallization database is then processed for input to the
E-beam lithographic equipment; this processing software is the standard software used to drive the E-beam equipment. The computer processing time required to do local rip-up route changes has been measured and found to be typically 1 to 2 seconds on an
inexpensive 32-bit minicomputer.
The modified net list is next used to produce the database for the desired interconnect patterns on the wafer using E-beam means. The metallization process is in one embodiment a two layer metallization, although a single layer of metallization
or three or more layers of metallization can also be used. The process involves depositing a layer of insulation, such as silicon dioxide, typically of about one micron thickness over the wafer surface, and cutting vias by means of a mask to the contact
points on the wafer surface through the silicon dioxide layer. Then a layer of metal, typically aluminum, is deposited over the silicon dioxide. Then a layer of photoresist is deposited and patterned, for example using E-beam (maskless) lithography.
The E-beam is controlled by the CAD database means and its modified net list to make the desired interconnect pattern corrected in accordance with the test results. The photoresist is then developed and removed where not exposed to the E-beam, allowing
the patterning of the interconnects as desired.
The metallization process is then repeated for the second metallization layer and any subsequent metallization layers. The metallization process is generally well known technology, the innovation being that the net list is modified for each die
even though the function to be implemented on each die is identical.
At this point the wafer is complete, ready for scribing, packaging and final test as usual.
The tester surface as mentioned above is a key element of this invention.
The tester surface is specially fabricated using advanced semiconductor manufacturing methods. Starting as shown in FIG. 7 with typically a conventional 5" or 6" silicon wafer substrate 101 (without any circuitry on it), a layer of KBr or other
release agent 102 is deposited over the wafer 101 surface, followed by a layer of gold 103 about 1000.ANG. (0.1 micron) thick. Then a layer of silicon dioxide 104 of about one micron thickness is deposited on the wafer 101 surface by means of chemical
vapor deposition. This is a low stress layer, deposited at about 100.degree. F., using commercially available systems such as provided by Ionic Systems (Milpitas, CA) or ASM Lithography, Inc. (Tempe, AZ). The silicon dioxide layer 104 has a surface
stress of about 10.sup.5 dynes/cm.sup.2, making it very flexible. Then, using conventional mask methods and photoresist layer 106 as described above, vias such as 108 are etched, down to the gold layer, in the silicon dioxide layer 104 to define the
probe points. The vias such as 108 are 2 to 4 microns in diameter.
The tester surface, in the preferred embodiment, has two similar gold metallization layers on top of the wafer. The first metallization layer is formed by first depositing, over the KBr layer 102, a silicide layer (not shown) 1000.ANG. to
2000.ANG. (0.1 to 0.2 microns) thick to act as an etch stop. Then the silicide deposition is removed from all but the vias 108. A nichrome/gold metallization-I layer 112 is deposited, to a thickness of 1000.ANG. to 2000.ANG., and a first layer metal
mask and etch are used to define the interconnect lines by forming traces.
Then a second silicon dioxide layer 114, also about one micron thick, is deposited, followed by the second layer via 116 masking, second layer via etching, nichrome/gold metallization layer-II 118 and second layer metal mask and etch as shown in
FIG. 9.
Next, customized multiplexer circuits such as 120-1 and 120-2 as shown in side view in FIG. 10 are attached to the metallization-II layer 118. These multiplexers 120-1 and 120-2 are individual die that contact the metallization-II layer 118
traces as desired, to provide electrical connections to the tester signal processor. The multiplexers such as 120-1 and 120-2 are dispersed around the outer part of the metallization-II layer 118 on the wafer 101, and serve as programmable input/output
means.
Next a mechanical structure called a support ring 122, as shown in top view in FIG. 11, and in side view in FIG. 12, is bonded with epoxy adhesive to the metallization-II layer 118 on top of the wafer 101. The support ring 122 is typically a
quartz annulus (ring) of the same outer diameter as the wafer substrate 101 and an inner diameter of 1 to 2 inches.
The quartz support ring 122 is in one embodiment 0.1 inch thick. Its inner area 124 is the contact area of the test surface. The ring 122 thus supports the actual contact area 124 and provides electrical connections to the remainder of the test
system. The support ring 122 has holes such as 126-1 and 126-2 (FIG. 11, 12) machined into it to accommodate the multiplexer circuits including 120-1 and 120-2 as shown in FIG. 12.
The support ring 122 and its underlying silicon dioxide and metal layers are now released from the underlying silicon wafer 101 shown in FIG. 9. The release agent KBr (or similar material) was the material first deposited on the wafer 101. By
means of the release agent, scribing around the edge of the support ring and then dipping the assembly shown in FIG. 12 in water allows the silicon dioxide layers to be peeled off the wafer 101. Alternatively, without the use of KBr, release can be
achieved by etching the wafer 101 away in an ethylene-diamine solution
Next, with the tester surface free of the wafer 101, the first gold deposition layer 103 shown in FIG. 7 is stripped off, leaving the exposed gold-filled vias such as 108 on the released surface 130 as shown in FIG. 9.
To complete the tester surface, probe points are grown on the released surface, so that the probe points grow out from the vias such as 108. To grow the probe points, the support ring 122 and its attached layers are put in a float not shown),
and the float placed in an electrolytic solution containing gold with the exposed ends of the vias 108 as shown in FIG. 9 immersed in the solution. Voltage is applied and the probe points such as 132 grow by electrolyzation at the ends of the vias 108.
The probe points such as 132 are thus made of gold in the preferred embodiment and grow out of the central part 124 of the test surface as shown in FIG. 12. The probe points such as 132 are 2 to 4 microns in diameter, and about 4 microns high.
They connect with the metal in each via, and hence to the two metallization layers. The pattern of probe points such as 132 on the tester surface is unique, and corresponds to the contact test points on the wafer to be tested.
Several kinds of probe points 132 can be provided. In an alternative embodiment, probe point height is determined by a mask. To provide masked probe points, a mask containing vias is formed on surface 130 at the probe point locations, then the
points grown in the vias and then the mask removed. The probe points can be aluminum or other suitable metals or conductive materials.
The tester surface itself can be fabricated with elastomeric probe points such as conductive doped polyacetylene (personal contact with Professor Alan G. MacDiarmid, University of Pennsylvania and also see "Plastics that Conduct Electricity,"
Scientific American, Feb., 1988, pgs. 106-111, by Richard B. Kaner and Alan G. MacDiarmid) that compress on contact with the contact points of the device or ICLU under test, to allow closer probe point spacing or to make the tester surface more
flexible. Such elastomeric materials are applied and etched with established techniques.
In a slightly different method to fabricate the tester surface, the substrate wafer first has etched in its center a circular depression one to two inches in diameter and typically twenty mils deep. This depression will impart a gradual
extension to the outer part of the tester surface, so that the center part of the finished surface will extend slightly below the surrounding tester surface.
A different tester surface is illustrated in FIGS. 13-15. Here the multiplexer circuits and tester logic are integrated into the tester surface. FIG. 13 shows how, as before, starting with a standard semiconductor wafer 133, multiplexer and
tester logic circuitry 134 is fabricated on the surface of wafer 133. Then, as described above, a depression 135 is etched in the center of wafer 133. The depression 135 is again one to two inches in diameter and typically twenty mils deep. Then, as
shown in FIG. 14, several layers of silicon dioxide and metallization 136 are formed on the wafer over depression 135 and over the logic sites 134. In this embodiment, the tester probe point array sites such as 138 may (optionally) be etched into the
surface of the wafer 133 in the depression, to allow preformation of the probe points by filling the etched probe point sites 138 with metallization.
After the tester surface 136 (FIG. 14) is fully fabricated on wafer 133, the surface 136 is separated from wafer 133 as before by selective etching away of wafer 133. (Release agents cannot be used here since part of wafer 133 including logic
sites 134 must remain as part of tester surface 136). The tester surface 136 is attached to a support ring 150 before the step of selective etching as shown in FIG. 15, and used in the same manner as described above with a fluid well 152 and
piezoelectric pressure cell 154 provided.
Depending on their shape and material, the probe points such as 132 in the various embodiments will exhibit mechanical wear when in use to probe the wafer under test. When worn below tolerance, the points can be refurbished by dipping in aqua
regia to remove them, and then renewed with the electrolyzation process as before, to produce a remanufactured surface.
The above description of embodiments of this invention is intended to be illustrative and not limiting. For instance, very large circuits can be produced by testing and metallizing nine adjacent die 240 to 249 (in a 3.times.3 array) on a wafer
252 as shown in FIG. 16, and then interconnecting the nine die to form one super die 254.
Alternatively, the invention can be practiced not only at the transistor level, but at the ICLU level such as a standard gate or custom gates or memory devices. This involves fewer contact points, and requires redundancy to be provided in the
form of extra gates or groups of gates to replaced defective ICLUs. The invention is also not restricted to gate arrays, and could be practiced on any kind of integrated circuit (e.g., custom logic or DRAM).
If the tester surface probe points are enlarged to sizes of 2.times.2 mils to 4.times.4 mils, the tester surface would have an additional utility as a functional circuit tester for die-sorting purposes after the manufacturing of the circuit is
completed. This application would increase pin count density over the prior art.
The tester surface can be fabricated from flexible materials other than silicon dioxide, such as silicon nitride or polymers, so long as the materials physically support vias and conductive traces.
In another embodiment, the tester interconnections are formed on the surface of the wafer to be tested.
In this embodiment, instead of fabricating a tester surface of N.times.M test points in a grid with an interconnecting set of metallization layers fabricated in the tester surface, the interconnection metallization is fabricated on the surface of
the wafer (forming direct metallization contact to the ICLU contact points) and the probe points are arranged as a ring around this on-wafer tester interconnect structure. This process would form the same electrical connection path to the ICLUs to be
tested as in the previously described embodiments. The advantage here is that much smaller ICLU or contact points could be accessed, or alternatively this embodiment allows wider spacing of tester surface probe points and requires fewer of them, i.e.
only N+M points. This embodiment greatly increases the potential operable range of the invention with only a small increase in processing costs for the on-wafer metallization structure. The on-wafer metallization structure is temporary. It is
fabricated out of a metal such as aluminum and a separation dielectric layer of resist. Once the on-wafer interconnect structure has been used to test the ICLUs or devices by the tester surface, the interconnect structure is etched from the surface of
the wafer by normal wafer cleaning methods.
Probe Point Structure and Fabrication
In accordance with the invention, the diameter of the probe points varies from several mils to less than a micron. The larger probe points are typically used in the construction of functional IC testers where the electrode contact or pad size on
the IC to be tested is typically 2 mils to 5 mils in diameter. Use of the method in the construction of a functional IC tester allows 1 mil or less pad size diameter.
The various embodiments of the probe point design provide a vertical probe point contact adjustment of approximately 10% to 40% of the length of the probe point. This adjustment is provided due to the well-known flexibility of the low stress
silicon dioxide (SiO.sub.2) material in the probe point or the elastomeric properties of various conductive polymers such as polyacetylene, polythiophene or polypyrrole as examples. Thus these embodiments of the probe point are flexible structures which
recover to their original shape after being flexed. In one embodiment of the invention, flexibility of certain probe points allows the use of such probe points in a tester surface without the need for fluid back pressure as described above.
The adjustable probe point structure is applicable to both large probe point applications such as a functional IC wafer sorter system and for the manufacturing of large scale integrated circuits as practiced in accordance with the invention. The
adjustable probe points in use can be located on the tester surface at a very small center-to-center spacing (e.g., approximately 1.5 times to twice the diameter of the probe point's largest dimension) and thereby may contact pad sizes on the device to
be tested of the diameter of approximately 0.5 micrometer or less with center-to-center contact pad separation of 1 .mu.m or less. In other embodiments, the probe points have a diameter of approximately 0.25 micrometers. The probe point structure is
scalable in accordance with CVD (chemical vapor deposition) process, electroplating processes, and lithographic technology limitations, and therefore the fabrication of probe points as described below with diameters less than 0.1 .mu.m is supported.
In use, each probe point engages in a wiping action so as to engage and electrically contact the contact pads (electrodes) of the circuit device under test. The wiping action of the probe point at the contact pad of the device under test is
necessary to achieve ohmic contact when contact pads are made from metals that form overlying thin films of native oxides such as aluminum. The wiping action breaks through the thin film of native oxide overlaying the contact pad. This wiping action is
accomplished through mechanical vibration of the tester fluid which is provided behind the silicon dioxide supporting membrane. In the embodiment where the tester surface is without a fluid providing backpressure, a 5 micron to ten mil thick layer of a
conductive elastomeric polymer, such as conductively doped polyacetylene, is formed over a piezoelectric material layer on the side directly opposite the probe points of the tester surface. The elastomeric material absorbs shear stress experienced by
the tester surface brought about by loading during contact of the DUT and piezoelectric generated wiping action. The piezoelectric material is then made to vibrate by supplying it with an electrical voltage of a desired frequency, which in turn causes a
wiping action of the tip of the probe point on the surface of the substrate being tested.
In accordance with the invention also, a voltage input frequency to the piezoelectric material controlling the probe point pressure is used to cause a wiping action of the probe point tip. The appropriate voltage frequency results in vibration
of the piezoelectric material which in turn is transmitted to the probe points through the fluid in the bladder.
An additional layer of piezoelectric material, adjacent to the first layer but separated from the first layer by approximately 50 mils is used to measure the applied force on the tester surface. This optional piezoelectric layer generates a
small voltage when mechanical stresses are applied to it. These voltages are read and converted to load equivalent measurements on the tester's surface. These measurements are used to determine an over-load pressure on the tester surfaces as shown in
cross-section view of tester surface and support plate, FIG. 17(a). FIG. 17(a) shows in cross-section the tester surface membrane 270 and support plate 272 with the use of a piezoelectric material 274 as a pressure sensor in the fluid-filled bladder 276
of the tester surface. The fluid port 278 and piezoelectric generator 280 are also shown.
The physical placement orientation of the tester may be below (i.e., underneath) the DUT substrate. This would prevent any downward distortion of tester surface membrane 270 from the fluid 276 behind the membrane 270 due to gravity. Instead the
positions of tester surface 270 and the DUT substrate (not shown) are in reverse order from what one would intuitively expect, or the DUT substrate is held over tester surface 270 and tester surface 270 is raised to make contact with the DUT. In this
manner it is easier for tester surface 270 to maintain its originally formed shape while under internal fluid pressure. Incremental mechanical vertical adjustment means will be sufficient in many applications to bring all the probe points (not shown) of
the tester surface into full contact with the DUT without resorting to the application of additional piezoelectric generated pressure from pressure generator 280.
Probe Point Structure
The following describes two kinds of probe point structures and various probe point tip designs in accordance with the invention. These probe point structures and tip designs can be used in unrestricted combination on a Tester Surface.
Solid Probe Point
As seen in FIG. 17(b), in one embodiment a solid probe point, which bends (flexes) horizontally to adjust to vertical contact loading, is relatively thin and elongated with a length to diameter ratio of approximately 1-10 to 1-40. FIG. 17(b)
shows in cross-section a solid probe point structure with a central electrode 282 formed by CVD tungsten. Central electrode 282 provides contact between the metal probe point tip (preferably titanium or tungsten plated with gold) 284 and an interconnect
trace in tester surface 286. The shaft 288 of the probe point is low stress CVD silicon dioxide, as is tester surface membrane 290. Together, silicon dioxide layers 288, 290 form tester surface 292.
As seen in another embodiment in FIG. 18, the probe point 312 has a silicon dioxide core 314 with a thin metal cylinder 316 formed around core 314, and an external layer 318 of silicon dioxide. Also provided are metal tip 320, metal trace
electrode 322, and flexible SiO.sub.2 layers 324, 326. Layers 318, 324, 326 together form tester surface 328. Cylindrical electrode 316 provides greater current carrying surface area than does the solid central electrode of FIG. 17b.
Compressible Probe Point
A second probe point structure 330, which is compressible, is shown in FIG. 19a. Probe point 330 is hollow and uses a fluid back pressure acting against the interior 332 of the probe point 330 to cause the compressible probe point 330 to recover
its original shape after a load 334 (i.e., an IC contact point 336) which is compressing the probe point 330 has been removed. Probe point 330 includes a tip 338 of tungsten or titanium plated with gold, a wall 340 of silicon dioxide which is 100.ANG.
to 4000.ANG. thick, and an inner gold electrode 342 of tungsten or titanium 10.ANG. to 1000.ANG. thick plated with gold. Also shown is tester surface 344, which is 1.5 to 4.0 .mu.m thick. Probe point 330 is shown in its compressed (i.e.
"imploded.revreaction.) configuration under load 334 in FIG. 19(b).
As shown in FIG. 20(a), another probe point structure 348 has a diameter d of approximately 1 to 4 micrometers and a height h of approximately 4 to 12 micrometers. The wall or probe point 348 is composed of a layer of silicon dioxide 350, and an
embedded layer of metal 352, with a total thickness of approximately 100.ANG. to 4000.ANG.. The tester surface 354 is silicon dioxide, typically 1.5 to 4.0 .mu.m thick. The wall or the probe point may also be composed of a layer of metal and an
internal layer of silicon dioxide with a similar probe point 348 wall thicknesses in cross-section. The interior 356 of the probe point is hollow to allow a fluid to enter and fill the interior 356. The tip 358 of the probe point is preferably a
refractory metal with gold such as tungsten/gold or titanium/gold as described below.
Probe point 348 of FIG. 20(a) is shown in FIG. 20(b) wherein probe point 348 is compressed by contact with a contact pad 362 of a circuit device under test 360. As shown in FIG. 20(b), the probe point height is compressed by approximately 1 to 4
micrometers. The sidewalls 350, 352 of probe point 348 partially collapse due to the non-elastic nature of the silicon dioxide layer 350. However, the relative thinness of the sidewalls 350, 352 of probe point 348 and their low surface tension allow
the probe point 348 to recover its shape when the load is removed as in FIG. 20 (a). The fluid filling the interior portion 356 of probe point 348 is preferably commercially available Florinert. The sidewalls 350, 352 of probe point 348 are
substantially thinner than the supporting low stress silicon dioxide membrane 354, which has a thickness of typically 1.5 to 4 micrometers. The sidewall of the probe point 348 includes an embedded metal cylinder electrode 352 which connects the metal
probe point tip 358 with electrically conductive interconnect structures (not shown) interior to the silicon dioxide membrane 354 supporting probe point 348.
Optionally, in the case of compressible probe point 348, during fabrication (described below) the interior of the probe point 356 may be filled by metal deposition and selectively etched removed until only the metal at the interior tip 358
remains. This metal backing of the probe point tip 358 strengthens it.
Hybrid Probe Point Structure
FIG. 21 shows in cross-section a hybrid (both solid and compressible) probe point structure design. This structure provides stress minimization where the probe point attaches to the tester surface 363. The probe point is preferably fabricated
primarily from low stress silicon dioxide 364-1, 364-3, 364-4. The probe point has a metal (preferably CVD tungsten) core 364-2 with external silicon dioxide walls 364-1. Also shown is titanium or tungsten gold plated tip 365, and metal trace layer
364-5.
Other Probe Point Structures
FIG. 22 shows in cross-section three compressive-type probe points 366-1, 366-2, 366-3 with respectively blunt metal probe tips 368-1, 368-2, 368-3 on the tester surface 370. Tester surface interconnect trace 372 is shown making contact with the
cylinder shaped electrode 374 of a probe point such as 366-2 embedded in the low stress silicon dioxide tester surface 376 and side wall of probe point 366-2 and providing a connection between the tester surface interconnect trace 372 and probe point tip
368-2. An optional hard metal backing interior to the probe point and just behind probe point tip 368-2 is not shown.
Each probe point 366-1, 366-2, 366-3 has a similar diameter d and is compressible with a center-to-center spacing x between adjacent probe points. Distance x is typically 1 to 20 microns, but is preferably a distance of no less than
approximately 1.5 times distance d. This spacing allows the tester surface to probe integrated circuits of minimum feature sizes at the device (i.e. transistor) level. FIG. 22 shows probe points 366-1, 366-2, 366-3 in an unloaded configuration.
FIG. 23 shows in cross-section the same probe points 366-1, 366-2, 366-3 of FIG. 22 in contact (under load) with a DUT 380. The figure shows that the compressible probe points 366-1, 366-2, 366-3 each accommodate the height variances of the
various DUT contacts 380-1, 380-2, 380-3, thus showing the independent height adjustment capability of each probe point which can be as much as 40% of its length. As shown, each probe point 366-1, 366-2, 366-3 (exclusive of metal probe point tip 368-1,
368-2, 368-3) deforms approximately 1 micrometer for every 2 to 3 micrometers of probe point height. The surface thickness of the probe point wall 382 is approximately one quarter or less of the thickness of the supporting test structure membrane 370.
In the case of functional tester application where probe points may approach or exceed one mil diameter, the probe point wall (or sidewall) may be the same thickness as the supporting test structure membrane. A thinner wall of the probe point will
result in greater flexibility.
FIG. 24 shows another configuration of compressible probe points 386-1, 386-2, 386-3 with a pointed probe point tip 388-1, 388-2, 388-3. The shape of each probe point tip such as 388-1 contributes to the contact capability of the probe point
386-1 independently of the diameter of the probe point body 390 by providing a smaller probe point contact feature size and improving the efficiency for breaking through native metal oxides that may form on a contact pad to be probed. Various probe
point tip designs can be fashioned by the probe point fabrication process in accordance with the invention as described below.
As shown, the center-to-center x spacing between the probe points is approximately 3 to 6 micrometers. Each probe point is approximately 2 to 4 micrometers in diameter d. The height h of each probe point is approximately 4 to 10 micrometers. As
shown in FIG. 25, the same structure shown in FIG. 24 when under load from DUT 392 is deformed slightly. The side wall, which is approximately 1000.ANG. to 4000.ANG. .mu.m thick, is compressed by the load of DUT contacts 394-1, 394-2, 394-3. The
tester surface 396 is approximately 1.5 to 4 micrometers in thickness.
Tester surface 396 is preferably low stress silicon dioxide or silicon nitride. Each probe point tip 388-1, 388-2, 388-3 is constructed of a hard core such as titanium or tungsten (an appropriate barrier metal layer may be used to prevent the
formation of native oxide on the selected hard metal) which is optionally electroplated with pure gold The pointed probe point tips 388-1, 388-2, 388-3 of the probe point in this embodiment allows low pressure contact to be made to the device under test
392. The compressible probe point structure allows uniform pressure for all probe points and to provide independent vertical adjustment of closely spaced probe points 386-1, 386-2, 386-3.
FIGS. 26(a) and 26(b) show another configuration of hybrid probe points with a compressible probe point body portion 400 supporting an elongated solid probe point 402. The compressible portion 400 of the probe point as described above is hollow
and typically filled with a fluid 404. As shown in FIG. 26(b), the probe point configuration of FIG. 26(a) is compressed under a load 406. The solid portion 402 of the probe point has a diameter s of approximately 0.5 to 1.0 micrometers. The side
walls of the compressible probe point portion 400 are approximately 0.25-0.5 micrometers thick and formed of low stress silicon dioxide 408 with internal metal 410. The compressible portion 400 of the probe point has a diameter d of approximately 1-5
micrometers.
The probe point compressible portion 400 is formed on a tester surface 412 which is typically 1.5 to 4.0 .mu.m thick. The tip 414 of the solid portion 402 is tungsten or titanium plated with gold.
Probe Point Fabrication
In the above-described probe point structures, the probe point preferably has a hard metal tip in order to electrically contact the contact electrodes or pads of the device under test. The tip can have various shapes such as a flattened cone as
shown in FIGS. 22 and 20(a), or pointed as shown in FIGS. 19(a) and 24. The probe point tip as described above preferably has a hard metal core such as tungsten or titanium, and a gold plated surface which can be periodically replated as a maintenance
step. These probe point structures are dimensionally scalable in accordance with conventional semiconductor process technologies, and with the decreasing circuit device element minimum feature sizes, to allow electrical contact with various circuit
device contact pads (electrodes) of 1 .mu.m or less diameter. The fabrication of the probe points is accomplished as follows to produce a probe point of approximately one-half 29 to several micrometers in diameter. FIGS. 27(a) th | | |
