A first inverter circuit is coupled between a first voltage source and a reference potential by a plurality of cascaded transistors. Each of the cascaded transistors has a control gate which may be selected to bring the resistance of the transistor into circuit with the inverter circuit to control the charging rate of a distributed capacitance. An output circuit coupled to the first inverter circuit provides the distributed capacitance and an inverted buffered output. The output circuit also includes an output which may be connected to another circuit of the present invention to form a cascaded delay circuit and to receive a reset signal for resetting the cascaded delay circuit.
A variable delay circuit which includes a first power source line for supplying a first power source voltage, a second power source line for supplying a second power source voltage which is smaller than the first power source voltage, an input terminal for receiving an input signal, a selection terminal for receiving a selection signal, an output terminal for outputting an output signal which is delayed relative to the input signal, a pull-up circuit coupled between the first power source line and the output terminal for carrying out a pull-up operation based on the input signal which is received via the input terminal, and a pull-down circuit coupled between the output terminal and the second power source line for carrying out a pull-down operation based on the input signal which is received via the input terminal. The pull-up or pull-down circuit has a delay time which is variable in response to the selection signal which is received via the selection terminal.
A duty-cycle adjustable buffer and a method for operating such buffer can be applied to a clock tree circuit for providing an adjustable duty cycle. The duty-cycle adjustable buffer includes a first inverter and a second inverter connected with each other in series. Each of the first inverter and the second inverter includes a plurality of controlled current charging paths and a plurality of controlled current discharging paths, wherein at least one controlled current charging path and at least one controlled current discharging path of the first inverter and the second inverter are conducted. The timing of the rising edge and falling edge of a clock signal is dynamically adjusted so as to dynamically altering the duty cycle of the clock signal.
A variable delay circuit for controlling delay time includes P channel transistors connected in parallel, with respective source electrodes connected to a power supply, respective drain electrodes connected to an output terminal for providing delayed signal, and respective gate electrodes connected to respective control signal input terminals for receiving control signals. The circuit further includes N channel transistors with respective source electrodes connected to ground, respective drain electrodes connected to the output terminal, and respective gate electrode connected to the respective control signal input terminals. Identical or mutually inverted data signals or control signals are supplied to the respective gate electrodes of the P channel transistors and the respective gate electrodes of the N channel transistors.
A semiconductor delay circuit which can realize a fine delay time regulation pitch and can set a number of regulation steps is provided. A plurality of inverter tree circuit each having a plurality of propagation paths having delay times different with an equal pitch are connected in series and outputs of the propagation paths are selectively transmitted externally by a switch circuit.
An electronic, binary-controlled digital tapped delay line is realized by a plurality of like stages connected in cascade. Each stage comprises a differential amplifier circuit responsive to a pair of input signals for producing a pair of output signals and including a differential transistor pair. A first loading circuit formed by a plurality of load devices interconnected to produce a cumulative loading effect is connected to an input of a first transistor of the differential transistor pair for delaying turn-on of the first transistor. Similarly, a second loading circuit formed by a plurality of load devices interconnected to produce a cumulative loading is connected to an input of a second transistor of the differential transistor pair for delaying turn-on of the second transistor, the first and second loading circuits each being connected to a first circuit node. A delay control circuit is responsive to a binary control signal and connected to the first circuit node for causing turn-on of the first and second transistors to be delayed by a set amount of time when the binary control signal is asserted.
