The specification discloses a method and related system that allows hardware devices to participate in the coherency domain of a computer system. More particularly, hardware devices such as network interface cards, audio cards, input/output cards, and the like, are allowed to participate on at least a limited basis in the coherency domain by having cache memory that duplicates a FIFO buffer in main memory used to exchange information between software and the hardware. To exchange information, software writes to the FIFO buffer which invalidates the data in the cache-type memory of the hardware device, and the invalidation message acts to notify the hardware device of the availability of information in the FIFO buffer.

In a distributed network comprising a plurality of peer (as opposed to master-slave) computers, a method of file shadowing allows each peer computer to maintain copies of data entries originated by the other peer computers in near-real time. Each computer assigns a unique serial number to each entry, and forwards each entry with the serial number and an identification of itself to all the other computers. Each computer informs each other computer of the highest sequential serial number received from it, and each computer resends to each other computer all entries having serial numbers higher than that acknowledged by each other computer.

A method and apparatus for allowing two or more masters, such as central processing units (CPUs), to read a dynamic random access memory (DRAM) device which includes a cache connected to a main memory block. When a CPU provides a read request, the DRAM has a first logic circuit that compares addresses requested with addresses stored in the cache. If the addresses are the same, the DRAM sends an acknowledge (ACK) signal to that CPU and sends the data to the processor. If the addresses are not the same, the DRAM sends a no acknowledge (NACK) signal to the CPU and transfers the requested data from the main memory block to the cache. The DRAM has a second logic circuit that contains a latch which is set when the DRAM sends a NACK signal and reset when the DRAM sends a subsequent ACK signal. The second logic circuit is connected to the first logic circuit to disable the first logic circuit and prevent a cache fetch from main memory when the latch has been set. The second logic circuit is also connected to a refresh controller of the DRAM to prevent a refresh cycle when the latch is set. Both the first logic circuit and the refresh controller are enabled when the latch is reset.

One embodiment of the present invention provides an apparatus that selectively encodes bus grant lines to reduce I/O pin requirements. This apparatus includes a semiconductor chip with bus arbitration circuit. A number of grant lines emanate from the bus arbitration circuit. An encoder circuit encodes the grant lines into a smaller number of encoded grant lines. A selector circuit selects outputs from between the encoded grant lines and a first subset of grant lines. These outputs pass through output pins off of the semiconductor chip. During a first mode of operation, the first subset of grant lines is driven through the plurality of output pins. During a second mode of operation, the encoded grant lines are driven through the output pins. A variation on the above embodiment includes a number of bus request lines, which are divided into a first subset and a second subset. The first subset of request lines feeds through a number of input pins into the bus arbitration circuit. During the first mode of operation, the second subset of request lines feeds from off of the semiconductor chip through a number of I/O pins and bi-directional buffers into the bus arbitration circuit. During the second mode of operation, the second subset of grant lines feeds from the bus arbitration circuit, through the bi-directional buffers and I/O pins and off of the semiconductor chip.

One embodiment of the present invention provides a method for selectively encoding bus grant lines to reduce I/O pin requirements. The method includes receiving a number of grant lines emanating from a bus arbitration circuit and encoding the grant lines into a smaller number of encoded grant lines. The method selects outputs from between the encoded grant lines and a first subset of the grant lines. These outputs are driven off of a semiconductor chip through a number of output pins. During a first mode of operation, the first subset of grant lines is selected to be driven through the output pins. During a second mode of operation, the encoded grant lines are selected to driven through the output pins. In a variation on the above embodiment, the method additionally receives a number of bus request lines. These request lines are divided into a first subset and a second subset. The first subset of request lines is received through a number of input pins from off of the semiconductor chip. During the first mode of operation, the second subset of request lines is received from off of the semiconductor chip through a number of I/O pins and bi-directional buffers into the bus arbitration circuit. This first mode of operation allows more request lines to be used in conjunction with the plurality of encoded grant lines. During the second mode of operation, the second subset of bus grant lines feeds from the bus arbitration circuit through the bi-directional buffers and I/O pins and off of the semiconductor chip. This second mode of operation allows more pins to be used for grant lines when grant lines are not encoded.