An information processor includes a program memory for storing a data flow program having destination information and instruction information as one set. Destination information, instruction information and operand data included in an input data packet are latched in an input data latching portion. Only the operand data is transferred to an output data latching portion. An address is operated based on the destination information latched in the input data latching portion, and the program memory is accessed, so that the data flow program is read out. The destination information and the instruction information included in the read data flow program are latched in the output data latching portion. Paired data is detected by a paired data detection portion based on the data flow program latched in the output data latching portion. The detected data is operated by an operation processing portion.
A system for actualizing a process of a multi-generation packet by managing the generations of the packet inputted in a firing process module of a data driven type processor. The firing process module includes a generation management unit for rearranging the disk order of a sequence relationship associated with a periodic circulation of the generation numbers of a packet inputted. Further included is a subsystem for separating an address space in hashing when obtaining an address of a queuing memory of the firing process module.
A data-driven information processing device includes a program storage mechanism, a data pair generation mechanism, an operation processing mechanism, a circular pipeline for data transfer among the program storage mechanism, the pair data generation mechanism and the operation processing mechanism in a token format, and a data input/output control circuit connected to the circular pipeline. The data pair generation mechanism carries out a generation process of a data pair in a different manner depending upon whether the argument data companion to the argument data in an applied token is a constant or not. The data pair generation mechanism may include, for example, a constant data processing unit and a dynamic data pair generation mechanism. The data pair generation mechanism selects constant data output from the constant data processing unit when the argument data companion to the argument data in an applied token is a constant, and selects the argument data companion to an output of the dynamic data pair generation mechanism otherwise. The selected data is used to assemble a token. A plurality of dynamic data pair generation mechanisms are included, and an apparatus is disclosed for operating the dynamic data pair generation mechanism in an interleaving manner.
A data flow type information processor includes first and second program storing portions, a merging portion, a data pair detecting portion and first and second operation processing portions. Each of the first and the second program storing portions stores a data flow program and outputs a data packet including destination information and instruction information read from the data flow program based on an input data packet. The merging portion performs arbitration between data packets output from said first and second program storing portions. The data pair detecting portion receives a data packet output from the merging portion to detect two data packets having the same destination information. Each of the first and the second operation processing portions receives a data packet output from the data pair detecting portion and performs an operation processing based on the instruction information included in the data packet to output a data packet including the data indicative of the operation result to the corresponding program storing portion.
A data packet including a destination field, an instruction field and two data fields is outputted from a data pair detecting portion of a data flow type information processor. The data packet is divided into two data packets. The data packet including the destination field and an identification tag is sent to a program storing portion, and the data packet including the instruction field, the two data fields and the identification tag is sent to an operation processing portion. The program storing portion outputs a data packet including the destination field, the instruction field and the identification tag. The operation processing portion outputs a data packet including a result data field and the identification tag. These data packets are merged with each other, based on the identification tags and sent to the data pair detecting portion.
A VGA controller with a read-modify-write cycle implemented therein is provided. By implementing the read-modify-write cycle in hardware, and by reducing the data for such operations to a single address source, read-modify-write operations can be performed in a single cycle, as opposed to separate read and write cycles, with a consequent improvement in overall operating speed.
