An image processing system for extracting a plurality of local images each composed of m.times.n pixels, successively from a two-dimensional original image, to process the extracted local images and to convert the original imae into a second image composed of modified pixel data corresponding to the local images is disclosed which system includes a plurality of local image extracting circuits for temporarily storing time-sequentially applied pixel data in each local image extracting circuit while shifting the storage position thereof, to deliver m.times.n pixels having a predetermined positional relation on the original image, from each local image extracting circuit in parallel, a first data transfer circuit for allotting pixels extracted successively from the original image, to the local image extracting circuits, a local image reconstruction circuit for combining a plurality of pixels from the local image extracting circuits to reconstruct a plurality of local images deviated from each other by one pixel on the original image and to deliver the local images in parallel, a local image processing circuit for processing the local images from the local image reconstruction circuit in parallel, to convert the local images into a plurality of modified pixel data for forming the second image, and a second data transfer circuit for transferring the modified pixel data to an image memory.
An image processing apparatus has plural memories each capable of storing image data of a picture frame, and combines the image data of the plural memories. A data bus transmits the output resulting from the combining, to the input of the plural memories.
An image processing system for an image display comprising an image data producing device for producing image data corresponding to an image to be displayed and a display device for displaying the image on the basis of the produced image data. The image data producing device divides the image data into a plurality of data sections respectively corresponding to image areas constituting the image so that each of the plurality of data sections is produced as serial data and the plurality of data sections are outputted in parallel. The display device includes a number of pixel elements continuously arranged one-dimensionally or two-dimensionally and equally divided into a plurality of element sections respectively corresponding to the plurality of data sections. The display device is responsive to the image data from the image data producing device so that the plurality of data sections are inputted in parallel to the plurality of element sections, whereby the display device displays the image on a screen on the basis of the plurality of inputted data sections. This arrangement can speedily display a jointless high-grade image in real time.
An image processing apparatus is provided with a linear processor array which includes a plurality of linearly coupled processing elements. The apparatus further includes a plurality of local memories each of which takes a form of one-dimensional pixel data memories. The local memories are respectively assigned to the plurality of processing elements. Further, the local memories are arranged so as to store in combination a two-dimensional pixel image to be processed. A plurality of buffers are respectively assigned to the processing elements. Each buffer stores pixel location information of at least one center pixel from which a unique pixel value is to be propagated if the center pixel exists on a corresponding local memory. With the arrangement mentioned above, in order to accelerate pixel data propagation in the two-dimensional pixel image, a plurality of register units are respectively assigned to the plurality of processing elements. Each register can be accessed by the adjoining processing elements and has first to third memory fields. The first memory field receives the at least one center pixel from the associated buffer. The second memory field stores the unique pixel data. The third memory field stores pixel positions which surround the center pixel and to which the unique pixel data should be propagated.
A display module driving system wherein digital pixel data for an image to be displayed is provided to a plurality of column drivers on a row by row basis in serial format over a plurality of dedicated bus lines rather than a single parallel bus line. Digital pixel data for a complete image row is divided into segments, wherein the number of segments is each to the number of column drivers. Each segments is then serialized and transmitted to a corresponding column driver such that the digital pixel data for an entire row is transferred to each of the plurality of column drivers at the same time. The column drivers receive the segments and rearrange the data into parallel. The pixels are then transferred to a digital to analog converter, preferably two pixels at a time, where each pixel is converted into analog red, green and blue signals. An analog sample and hold module samples each analog signal for all of the pixels in a given row of the display and stores the signals in first capacitors of a plurality of sample and hold capacitor pairs. The sample and hold capacitor pairs allow analog signals to be sampled and held on a row by row basis such that when one capacitor in each pair stores one of the analog red, green and blue voltages for a subsequent row, the other capacitor transfers the analog voltage signal out for a current row to the column electrodes of the display.
A parallel-processor graphics architecture appropriate for multimedia graphics workstations that is scalable to the needs of a user. The graphics architecture includes one or more rendering processors and a graphics memory that is partitioned into blocks. Noncontiguous groups of the blocks are then assigned to different processors. The parallel-processor graphics architecture is scalable by the number of rendering processors utilized, and is configurable with respect to the allocation of the groups of the blocks to specific rendering processors.
