A FAST OE signal circuit generates FAST OE signals of high and low potential levels. A SLOW OE signal circuit generates SLOW OE signals corresponding to FAST OE signals. The SLOW OE signals have the same high or low potential level as the corresponding FAST OE signals and occur a specified time delay after the corresponding FAST OE signals. A tristate output buffer circuit operates in the bistate mode when enabled by high potential level OE signals for transmitting binary data signals, and operates in a high Z tristate mode when disabled by low potential level OE signals. The FAST OE signal circuit and SLOW OE signal circuit ae coupled in parallel to the tristate output buffer circuit for enabling and disabling the tristate output buffer circuit. The FAST and SLOW OE signals in combination skew the enable time relative to the disable time. The enable times tpZH and tpZL are substantailly longer than the disable times tpHZ and tpLZ, introducing "temporal" separation between active tristate output devices on a common bus to reduce bus contention. A DC Miller killer circuit is coupled to the pulldown transistor element of the tristate output buffer circuit for turning off and holding off the pulldown transistor element in response to high potential level DCMK signals. A DCMK signal circuit generates DCMK signals corresponding to inverted FAST OE signals. A DCMK signal enhancer circuit provides transient enhancement of high potential level DCMK signals in response to corresponding low potential level FAST and SLOW OE signals.
A low voltage 485-driver circuit that meets the standard leakage and 1.5 voltage differential output requirements of the TIA/EIA-485 specification while operating from a 3V supply. The circuit avoids the voltage drop across the series Schottky diodes in the output driver of a conventional 485-driver by moving the Schottky blocking diodes from the output stage signal path to the pre-driver stage so that the output stage is restricted to back-gate biasing only. In addition, the circuit uses stacked NMOS transistors to maintain lower voltage across each NMOS transistor in order to prevent hot-carrier injection. This allows lower voltage rated output NMOS transistors to be used, resulting in higher speed operation. The circuit will withstand excessive common mode voltages in the range of +12V to -7V applied to the output while in either signaling ON state or the disabled OFF state.
A circuit to be used with tristate output buffers as a means of diverting from the output pulldown transistor control nodes Miller Current arising while the output buffer is being switched from the low-active state L to the inactive state Z. The circuit complements a DC Miller Killer circuit, relieving the latter from having to deal with this transient, and hence permitting a down-sizing of the DCMK transistor. The net effect is a significantly faster L.fwdarw.Z transition for the tristate buffer and a slightly faster Z.fwdarw.L transition, all accomplished without degrading the DC Miller Killer protection against L.fwdarw.H bus transitions. The key to the present invention is its use of the time interval between the respective, sequential switching of the enable buffer outputs, E and EB following the application of a disable signal to this enable buffer. The present invention includes circuitry which ensures that its Miller Killer transistor is conducting only during the transient associated with the L.fwdarw.Z switching. One embodiment for accomplishing this is to connect the control node of an "LZ/ACMK" transistor to the high-potential power rail through two control transistors wired in series. Then, by arranging the circuitry so that both control transistors are conducting only when E and EB are both logic-low, a situation which arises only in the midst of a transition of the output buffer into its Z state, the desired AC operation of the present Miller Killer is achieved.
Power or ground voltage can fluctuate when many high capacitance terminals of an integrated circuit device move simultaneously from one logic state to another. This occurs particularly after release of a global high impedance state of output buffers where output signals have been passively driven to a selected logic state. To prevent supply and ground voltage variations, the buffers are provided with means for operating in a slow response (high slew) mode. A slew rate control circuit moves the buffer to slow response mode in response to the high impedance signal. When the slew rate control circuit receives a signal ending the high impedance state of the buffer, it applies a delay to this signal, and after the delay time allows the buffer to move to a fast response mode. The slow buffer response and resulting slow voltage change when high capacitance terminals move to a new logic state prevents fluctuation of power or ground voltage in response to simultaneous switching of many terminals.
A transceiver includes a first receiver having an input connected to a first I/O port of the transceiver and an output connected to an output port of the transceiver and a second receiver having an input connected to a second I/O port of the transceiver and an output connected to the output port of the transceiver. A first driver has an input connected to an input port of the transceiver and an output connected to the first I/O port, and a second driver has an input connected to the input port of the transceiver and an output connected to the second I/O port. The transceiver has a first state in which the first receiver and second driver are enabled and propagate signals from the first I/O port to the output port and from the input port to the second I/O port and the second receiver is disabled and presents a high impedance to the output port, and a second state in which the second receiver and first driver are enabled and propagate signals from the second I/O port to the output port and from the input port to the first I/O port and the first receiver is disabled and presents a high impedance to the output port.
A semiconductor device including a tristate buffer circuit, which includes, on an output stage, at least a first transistor (P1) for pull-up driving and a second transistor (N1) for pull-down driving, in which, when a control signal (EN) is of a value indicating an enable state, an output is set to a high level or to a low level, depending on a data signal, and in which, when the control signal is of a value indicating a disable state, the first and second transistors are turned off to set a high impedance state of the output. The semiconductor device further includes a control unit (120, P6, P7) for performing control for speeding up the transition from the on-state to the off-state of the first transistor (P1) at the time of switching the control signal (EN) from the enable state to the disable state.
