A method in which a variable sized segment of a memory array can be written in a single memory cycle is provided. A predetermined set of the column addresses or a combination of the column address and I/O field specify the starting location of a block of a memory array row to be written. The set of remaining column addresses specifies displacement from the starting location. Together the starting segment and the displacement define an area of memory which can be written in a single cycle.
The invention is the circuit and method for selecting a window of desired address locations to be written. A start address and a stop address activate a start and stop decoder output respectively. The active start and stop decoder output signals are rippled through start and stop ripple circuitry which enables the outputs electrically interposed between the start and stop addresses respectively. AND circuitry ensures that only the outputs interposed between the start and stop addresses are activated in addition to the start and stop decoder outputs. The activated outputs comprise the window of desired address locations to be written.
A programmable semiconductor memory system employs an EPROM. The system holds the start and end addresses of each write operation to completely use a data storage region of the EPROM with no redundancy and with no limitation on the quantity of data to be written if the quantity is within the capacity of the EPROM.
A method for encoding a data mask that consists of a given total number of bits and includes a selected group of contiguous bits within the total number, the selected group having a left end and a right end. The method includes dividing the data mask into a plurality of segments, and representing the segments by respective segment codes, each code indicating whether the bits in the respective segment fall entirely outside the selected group, entirely within the selected group, or include the left end or the right end of the group. The segment codes are combined so as to generate a mask code, which can be decoded to reconstruct the data mask.
In a method of write to a graphic memory where memory cells designated by a plurality of addresses selected simultaneously for one ROW address, the present method of write includes a first step of dividing the area corresponding to the column addresses designated by one row address of a memory cell array in to a plurality of segments each consisting of an arbitrary number of column addresses, a second step of designating a start address and an end address for each of the plurality of segments based on a first piece of information of column information, a third step of specifying the section designated by the start address and the end address as the candidate for the write object areas, and a fourth step of selecting segments having write object areas based on a second piece of information of the column address information, and writing specified data to the candidate for the write object areas of the segments having the write object areas.
As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.
