A memory device for storage of digitally formatted data can include a Digital to Analog Converter (DAC) circuit that is configured to convert digitally formatted data received from outside the memory device to analog formatted data. An Analog to Digital Converter (ADC) circuit is coupled to the DAC circuit and is configured to convert the analog formatted data to the digitally formatted data for storage in the memory device. Related methods are also disclosed.

A high speed analog to digital sampling system. The invention allows for decimation and optimal storage of samples from an interleaved analog to digital conversion system. The circuit architecture provides for switchable flip-flops at the outputs of a set of interleaved analog to digital converters. Decimation is accomplished by only activating a selection of the analog to digital converters within the set of interleaved analog to digital converters. The flip-flops associated with the inactive analog to digital converters are configured to form a shift register. The samples of the activated analog to digital converters are shifted into the shift register. When all the flip-flops of the shift register are full, the samples are written to memory of the system. The shift register configuration allows the samples to be stored so that the allocation of system memory is optimized and the number of system memory writes is reduced. One embodiment of the invention includes presettable dividers for providing control over the rate at which the flip-flops are loaded with sampled data.

A HACT device which propagates charge packets 21 along a charge transport channel 17 by a surface acoustic wave (SAW) 14 is provided with an interdigital electrode grid 30 disposed on the upper surface of the HACT, near the charge transport channel 17, having electrodes 30 spaced a distance of one-half wavelength of the SAW. A hold voltage Vh is applied across alternating electrodes to store (i.e., stop and hold) each charge packet. When a charge packet is to be released, the hold voltage Vh is removed and the electrodes 30 are shorted together or alternatively connected through a maximum allowable impedance, thereby allowing each charge packet 21 to be stored and released by the device without having the electrodes 30 absorb the SAW electric fields. Because the electrodes 30 are spaced one-half a SAW wavelength apart, the HACT memory can store each and every charge packet 21, thereby providing a Nyquist bandwidth device. Furthermore, the electrodes 30 are made thin to reduce mechanical absorption of the SAW by the electrodes.

A signal processing apparatus enjoying a remarkably enhanced operation speed while ensuring accurate control capability due to data holding and learning control includes an A/D converter for converting an analog signal into a digital signal, a packet interface for generating a packet on the basis of the digital signal, a timing port controller for controlling the timing of operation of the A/D converter and generating output data on the basis of the packet, a power supply interruption detecting circuit for detecting a decrease in source voltage to thereby generate a power supply interruption detecting signal, and a data flow processor including a data store and a data flow loop for processing the packet in accordance with tag information contained in the packet. The data flow processor responds to the power supply interruption detecting signal to save electric power from consumption and hold the content of the data store.