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RELATED PATENTS
This invention is related to those disclosed in the commonly-assigned U.S.
Pat. Nos. 4,555,783 (issued Nov. 26, 1985 to Swanson and entitled METHOD
OF COMPUTERIZED IN-CIRCUIT TESTING OF ELECTRICAL COMPONENTS AND THE LIKE
WITH AUTOMATIC SPURIOUS SIGNAL SUPPRESSION) and 4,459,693 (issued Jul. 10,
1984 to Prang, et al. and entitled METHOD OF AND APPARATUS FOR THE
AUTOMATIC DIAGNOSIS OF THE FAILURE OF ELECTRICAL DEVICES CONNECTED TO
COMMON BUS NODES AND THE LIKE), which are both incorporated herein by
reference.
FIELD OF THE INVENTION
The present invention pertains to automatic testing of electronic circuits,
and more particularly to improved test techniques for digital devices.
BACKGROUND OF THE INVENTION
Programmable, computer-controlled instruments and systems for testing
printed circuit boards and electronic components thereon are called
"automatic test equipment" or "ATE's." ATE's include functional testers
and in-circuit testers. A functional tester tests overall functionality of
a board-under-test, "BUT," i.e., how the electronic components and
circuits of the BUT function collectively. Functional testing of a portion
of a circuit board is called "cluster testing." Thus, functional and
cluster testers test so-called functions-under-test ("FUT's"). on the
other hand, in-circuit testers test individual devices-under-test
("DUT's"). As the name implies, in-circuit testing is performed without
the DUT's being physically disconnected from the other electronic
components or circuits of the BUT with which they normally are
electrically connected.
ATE's are used to detect manufacturing defects, such as short circuits
(e.g., a solder bridge between the etched, conductive tracks on the BUT),
faulty assembly of electronic components on the BUT, or defective devices
themselves.
For instance, in-circuit testers can detect defects in digital logic
devices such as integrated circuits ("IC's"). To accomplish such testing,
the IC's are exercised and checked against their truth tables. More
specifically, the tester applies pre-selected drive signals to inputs of
the DUT's, monitors or detects the responses to the drive signals on the
outputs of the DUT's, and compares the detected responses with expected or
predicted responses for those devices.
To perform in-circuit tests on a fully-assembled printed circuit board, the
tester must be able to have access to the circuit nodes on the BUT.
"Nodes" are the electrical connections between the leads of electronic
components of the BUT, e.g., the etched, conductive tracks on the pc board
that extend between various output leads and input leads of electronic
components on the BUT.
Electrical access to the circuit nodes on the BUT typically is provided by
a test fixture, aptly named a "bed-of-nails"fixture. The "nails" in this
fixture typically are a plurality (e.g., hundreds) of probes, each
typically being a spring-loaded pin, that electrically contact the nodes
on the BUT during testing. Some of the nails supply the drive signals to
the BUT, and others receive the response signals from the BUT. The nails
are inserted in sockets so located on the fixture as to maintain the nails
in registration with the selected circuit nodes with which they are to
make electrical connection. Connections between the fixture and the tester
are made by wiring the other end of the sockets to electrical connectors
in the tester. The physical interface between the fixture and the tester
is called the "receiver."
A conventional tester has sets of digital drivers that it uses to drive the
IC inputs to desired voltage states, and a set of digital sensors to check
the logic levels at the IC outputs. These drivers and sensors typically
form driver/sensor testing pairs ("D/S"), in which the output of a driver
is tied to the input of an associated sensor. In this way, BUT nodes
contacted by the D/S pairs each can be either driven by a current supplied
by the driver or tracked, i.e., have its current sensed by the sensor of
the D/S pair. Drivers and sensors preferably are separately controllable
by the tester.
When a D/S pair is used to place an IC input in a desired voltage state,
the driver is enabled (connected) and a suitable voltage is applied to the
IC input. Then, the sensor of another D/S pair is enabled to sense the
response to that drive signal at an IC output .
For example, if the IC were a NAND gate having two inputs N0, N1 and an
output N3, and if it were desired to apply a HIGH level to both inputs
while checking the output for a LOW level, the following test patterns
could be followed: a) the drivers of the D/S pairs, which are associated
with the test nails which, in turn, are connected to inputs N0, N1, are
enabled, b) a voltage selected to place these inputs N0, N1 in the HIGH
state is applied to those drivers, c) the sensor of each of the D/S pair,
which is associated with the tester nail which, in turn, is connected to
output N3, is enabled, and d) the sensor is controlled to check for a LOW
output from the NAND gate.
To fully test all possible combinations of input values and the resulting
output value for the NAND gate, of course, would require four tests, as
indicated by the following truth table for the NAND gate:
______________________________________
N0 N1 N3
______________________________________
LOW LOW HIGH
LOW HIGH HIGH
HIGH LOW HIGH
HIGH HIGH LOW
______________________________________
Thus, for this simple circuit having a single DUT, four tests can be
performed, each of which entails the driving of two nodes (connected to
inputs N0, N1) and the sensing of a third node (connected to output N3).
Of course, actual PC boards typically have a large number of electronic
components, many of which can have multiple inputs and outputs, so the
tests can be quite complex.
Such complex digital tests routinely are conducted with presently
manufactured testers, typically at speeds faster than the testers' central
processing units ("CPU's") can control in real time. Therefore, the CPU's
typically load series of test patterns into memory banks. Then, to start
the tests, the CPU's enable high-speed controllers, which transfer the
test patterns to the drivers and store the responses detected by the
sensors in the memory banks. After the test procedures are completed, the
CPU's transfer the results of the tests from the memory banks to main
memory for later analysis.
An additional complication arising in in-circuit testing is test isolation.
Driven nodes (i.e., circuit interconnections) on the pc board typically
are connected not only to the inputs of the DUT's but also to inputs
and/or outputs of other electronic components. Consequently, many
electronic components on the pc board, in addition to DUT's, typically are
energized simultaneously by the drive signals. The tester must be able to
electrically isolate each DUT from the other electronic components to
which they are electrically connected. Analog devices are isolated, e.g.,
by conventional techniques collectively referred to as "guarding." Digital
devices typically are isolated by a process known as "backdriving."
Backdriving can be understood with continued reference to the example given
above. Suppose the test requires that input N1 be held HIGH, but further
suppose that input N1 is connected to a node which the output of another
IC, called an "upstream" or "predecessor" device, ordinarily would be
driving to a LOW value. The tester can handle this conflict in logic
states by momentarily forcing N1 to the desired HIGH state regardless of
the state to which it is being held by the upstream IC. This technique of
momentarily overriding an IC output is called "backdriving." In other
words, backdriving is the process of forcing the output of an up-stream
digital device to a logic level different from that to which the digital
device is "trying" to drive it.
Typically, backdriving is carried out by applying to a node (called a
"controlled node") a backdriving current that exceeds the drive capacity
of the device to whose output the node is connected, and thus is
sufficient in amplitude to change the voltage state of that node. By
controlling the state of the controlled node, the DUT's input node or
nodes (called "protected nodes") are placed in desired logic states.
Often, the controlled nodes are those which are connected immediately
between the outputs of up-stream electronic components and the inputs of
the DUT's. When that is the case, the controlled nodes are also protected
nodes. Other times, the controlled nodes are other nodes of the BUT, e.g.,
nodes connected to the inputs to the upstream electronic components. When
that is the case, for example, the backdriving currents cause the inputs
of those upstream electronic components to assume values that result in
outputs at the desired voltage levels, and, these voltage levels are
applied to the protected nodes leading to the inputs of the DUT's. In
other words, the backdriving signals applied to upstream electronic
components propagate through the circuit and eventually yield the desired
state on the protected nodes.
The generation of an appropriate backdriving strategy or methodology is
important to the success of the testing of the digital devices. For
example, consider what can happen when a DUT is connected as part of a
feedback loop. For instance, take the situation of a conventional toggle
flipflop circuit configured as follows: the Q output of a J-K flip-flop is
connected in a feedback loop through input N0 of a NAND gate back to the
clock input of the flip-flop, while a HIGH value is applied to input N1 of
the NAND gate, and the J and K inputs of the flip-flop are tied to a LOGIC
ONE, so that the Q output of the flip-flop toggles to an opposite state
whenever a positive going transition is applied to the clock input. It
would be desirable to test this circuit by initially clearing the
flip-flop, contacting a driver to the node leading to the clock input,
placing the clock input in a LOW state, applying a HIGH value to the clock
input, and checking the output of the flip-flop to assure that it properly
changes state.
However, when this test is run, the sudden change in the flip-flop output
(HIGH to LOW) elicited by the drive signals immediately feeds back a LOW
signal to the clock input. However, this LOW signal soon is overcome by
the drive signal which restores that input to a HIGH value. Thus, the
clock input, and the node connected to it, experience a momentary dip in
voltage, known as a "glitch." (A "glitch" is any small, spurious pulse or
spike, regardless of polarity.) The glitch can cause the flip-flop to
toggle back to the state it was in before the test, depending on the size
and duration of the glitch. If this happens, the tester may conclude that
the flip-flop did not toggle and, therefore, failed the test. An
appropriate backdriving strategy therefore is necessary to avoid the
generation of the glitch, and, thereby, the erroneous test results.
Another example of the many test situations requiring a special backdriving
strategy is the testing of bused devices, i.e., several digital devices
all having outputs connected to a common bus. The tester must check each
device individually to see if each one can control the logic state of the
bus. Unfortunately, since the device outputs are all tied together, any
defective device could force the bus to an erroneous state at which, for
example, the bus would remain despite an output from another of the
devices which normally would place the bus in a different state. In other
words, the bus is "stuck" in the erroneous state. The problem is to
identify which, if any, of the electronic components is the defective one.
The strategy by which backdriving currents are applied to isolate DUT's,
such as those in the above examples, is called the "isolation protocol."
The isolation protocol consists of a plurality of isolation methods, one
for each DUT. Each isolation method is a procedure for placing one or more
outputs of an IC that is up-stream from the DUT being isolated into a
specified logic state by driving one or more inputs of that IC (or of a
device up-stream from that IC) into selected logic states or a sequence of
selected logic states.
When a specified protected node is to be placed in a desired logic state,
one or more isolation methods may be available to accomplish this task.
From the perspective of the specified protected node, each such available
method entails the identification of a set of nodes to be controlled in
order to protect the specified protected node, and the specification of
backdriving currents required to effect that control.
As is known in the art, there are numerous different types of methods that
can be employed to isolate any particular DUT. Generally speaking, these
types of isolation methods can be classified in accordance with the way
they achieve the isolation, and typically fall into one of several
classes---- e.g., inhibits, disables, H-forces, and L-forces. An inhibit
method prevents a glitch from propagating into the output so as to keep
the output constant, and, normally, to drive the output into the weaker
state. (For example, in transistor-transistor logic ("TTL"), an inhibit
method attempts to drive the output into the HIGH state which is typically
the weaker state.) A disable method forces an output into an OFF state. An
H-force method forces the output into a HIGH state, while an L-force
method forces the output into a LOW state.
The selection of which of the available types of isolation methods to use
is made by analyzing the BUT's topology and the characteristics of the
electronic components contained thereon. Of course, where a BUT has a
plurality of protected nodes, a plurality of isolation methods may be
selected for implementation during testing, each isolation method causing
one or more of the protected nodes to assume the desired logic state
therefor.
In the examples described above, to protect against unwanted glitches in
the flip-flop circuit, the tester inhibits the NAND gate in the feedback
loop, thereby eliminating the glitch-sensitive feedback signal and
permitting the glitch-free testing of the flip-flop. (Generally speaking,
as discussed in the above-referenced U.S. Pat. No. 4,555,783, to protect
against unwanted glitches during a test, a tester typically disables all
tri-state electronic components (i.e., digital devices having outputs that
can be HIGH, LOW, or a high-impedance state) by placing them in their
high-impedance state, and inhibits all other electronic components (except
for the DUT's) by forcing their inputs to a state that effectively
inhibits their operation.)
The protocol for testing the common bus example, given above, to determine
which device is defective and is keeping the bus stuck in one state,
entails disabling all of the devices (e.g. by placing them in their high
impedance state) and measuring the bus current, then enabling each device
separately, one at a time, applying logic inputs to the enabled devices
that tend to drive the bus to that one state, and measuring the resulting
bus currents. If the bus current changes significantly, the enabled device
is not faulty, but if the current remains substantially the same as when
the device was disabled, then that device is regarded as faulty.
Backdriving strategies for the common bus scenario are discussed in the
above-referenced U.S. Pat. No. 4,459,693.
A further understanding of methods of isolation can be had by reference to
a paper entitled "Effective Utilization of In-Circuit Techniques When
Testing Complex Digital Assembles," written by Aldo Mastrocola, GenRad,
Inc. of Concord, Massachusetts, U.S.A., presented at the Automatic Testing
and Test and Management '81 Conference, Wiesbaden, West Germany in Mar.,
1981, and incorporated herein by reference. Also, testing equipment for
digital devices employing backdriving for isolation are commercially
available from GenRad, Inc., Concord, MA.
Thus, the isolation needed for accurate and reliable in-circuit testing is
achieved by using a combination of methods of applying backdrive currents
to the BUT, which methods collectively constitute the isolation protocol
for the BUT. However, backdriving currents can present their own problems
in testing pc boards.
These backdrive currents generally are of greater amplitude than, and are
directed in the opposite direction with respect to, the currents normally
flowing in the controlled nodes. Consequently, the up-stream devices with
respect to those nodes experience reverse currents that flow into the
up-stream devices through their output power leads. The effects of these
currents on the up-stream devices is called "backdrive stress." While
these currents often do not present a problem, the rise in temperature
attributable to these currents can cause damage to the up-stream devices,
i.e., under certain conditions the up-stream devices can experience
excessive backdrive stress.
In conventional in-circuit testing, fixed cool-down intervals of
pre-determined length commonly are introduced between the pulses or bursts
of the driving signals in order to reduce adverse temperature effects of
excessive backdrive stress, e.g., by permitting the devices to cool to
room temperature.
Another known technique is to use variable (instead of fixed) cool-down
intervals. An example of this technique is disclosed by U.S. Pat. No.
4,588,945 issued to Groves. In accordance with that patent, records
containing topological descriptions of the BUT, and pre-generated generic
test patterns for the DUT's, are provided. A topological analyzer sorts
through these records, selects patterns which are suitable for testing
each DUT, and supplies these patterns to a damage analyzer. The damage
analyzer receives the selected test patterns and calculates the time the
test will require, and, using safeguard parameters stored with the
topological records, calculates the length of the inter-burst times
necessary to avoid damage to up-stream components that would otherwise
occur. Thus, apparently, the safeguard parameters are not used in
selecting the test patterns, but, rather, they are used only after the
test patterns are selected, in the calculation of the cool-down periods.
Subsequently, a test controller applies the test patterns to DUT's through
a driver module, inserting the calculated inter-burst delays when and
where appropriate.
Generally, circuit board testing is recognized as a significant part of
quality assurance programs. Improvements in the reliability, safety,
efficacity, efficiency and economics of circuit board test and diagnostic
techniques represent marked advances in the manufacture of electronic
products of high quality. Recent trends toward higher-powered logic
families and larger IC's with many parallel outputs (e.g., gate arrays)
have made more evident the problems of excessive backdrive stress
resulting from such testing.
SUMMARY OF THE INVENTION
The invention resides in improved automatic testing equipment and systems
for performing in-circuit, functional or cluster tests which take
backdrive stress into account in selecting appropriate isolation
methods---- e.g., inhibits, disables, H-forces, and L-forces---- during
the generation of the test protocols. The generation of each test protocol
includes an analysis of the circuit board and its components, and of the
available methods to isolate the device- or function-under-test from the
rest of the circuit board. The analysis includes a calculation of "total
stress current" flowing in each upstream component to determine if these
currents are below a safety threshold (e.g., 1 ampere), and the selection
of a combination of methods from those available which (among other
considerations) will produce total stress currents below this threshold.
"Stress current" is the incremental increase in current flowing into an
output power lead of a component due to backdriving. The stress currents
resulting from backdriving the power leads HIGH, each symbolized as
"I.sub.osh," all flow through the device to, e.g., the V.sub.cc lead. The
stress currents resulting from backdriving the power leads LOW, each
symbolized as "I.sub.osl," all flow through the device to, e.g., ground.
The "total stress current" is the greater of the resulting currents
flowing through the V.sub.cc and ground leads.
It was recognized that the principal damage mechanism that determines
whether a particular method or combination of methods would result in
excessive backdrive stress is IC bond wire over-heating, and such
overheating depends on the amplitude of the stress currents. Bond wires
are the small conductors within the IC packages that connect the
semiconductor chips to the components' leads. For example, the V.sub.cc
bond wire connects the chip to the V.sub.cc lead, and the ground bond wire
connects the chip to the ground lead.
Backdrive stress generally will not damage the up-stream devices as long as
the total stress currents flowing through the V.sub.cc and/or ground bond
wires have amplitudes and durations below safe limits. However, if the
backdrive stress resulting from the chosen methods of isolation is
excessive, i.e., the total stress current flowing through the V.sub.cc and
ground bond wires are above a safety threshold for one or more devices on
the BUT, damage to those devices can result from the test. Therefore, as
mentioned above, the calculation of total stress currents that would
result from implementing the available methods of isolation of a BUT are
calculated and the resulting value is used in selecting the isolation
methods to be used in running the test. A suitable value for the safety
threshold has been found to be 1 ampere, although an even higher threshold
can be used for some devices.
Having selected methods of isolation which produce total stress currents
under the safety threshold, the system then can proceed to use the
selected methods in running the test. On the other hand, if all
combinations of the methods produce excessive backdrive stress, the test
equipment alerts the operator of this condition.
Preferably, however, and in accordance with another aspect of the
invention, a maximum length of time under which the test can run safely is
calculated before running the test. This is called "GLOBAL MAXTIME." More
specifically, GLOBAL MAXTIME is an approximation of the minimal length of
time before which the calculated total stress currents would overheat the
V.sub.cc and ground bond wires of the up-stream IC's. Thus, the methods of
isolation are chosen to assure that the stress currents are below a
selected maximum amplitude as described in the preceding paragraphs, and,
then, the GLOBAL MAXTIME is calculated to assure that the effects of the
calculated total stress currents over time will not damage the up-stream
devices were those selected methods implemented.
If the test can not be run in a period of time under the GLOBAL MAXTIME, it
would be unsafe to run the test. On the other hand, if the test can be run
in a period of time under the GLOBAL MAXTIME, the test as generated by the
system can safely proceed. For example, if the GLOBAL MAXTIME is
approximately 7 milliseconds, the test typically can be successfully run.
Consequently, it can be seen that an optimal isolation protocol is
generated in which excessive backdrive stress is eliminated, or the user
is afforded the opportunity to take measures to permit the test (or a
modified version of the test) to be run safely. Effectively, the invention
provides an automated backdrive stress management and control system for
in-circuit, functional, and cluster testing of printed circuit boards.
Each test run by the improved ATE in accordance herewith is characterized
by an inter-burst time period equal to the time it takes to load the next
test to be performed. This time period typically is of sufficient length
to allow the temperature to decline to approximately ambient temperature.
It should be emphasized, however, that the invention does not use the
inter-burst cool-down interval, as in the prior art, as the control
variable to eliminate the adverse temperature effects of excessive
backdrive stress. Rather, the invention uses calculations for the stress
currents, themselves, in the design of the test to eliminated the
potential for excessive backdrive stress during the running of the test.
The invention accordingly comprises the features of construction,
combination of steps, and arrangement of parts which are exemplified in
the illustrative embodiment hereinafter set forth, and the scope of the
invention will be indicated in the appended claims.
BRIEF DESCRIPTION ON OF THE DRAWINGS
The above and further advantages of the invention may be better understood
by referring to the following description in conjunction with the
accompanying drawings, in which:
FIGS. 1A and 1B are block diagrams of illustrative circuits to be tested in
accordance with the invention;
FIG. 2 is a simplified block diagram of an automated system for testing
circuits, such as that of FIGS. 1A and 1B, in accordance with the
invention;
FIGS. 3A and 3B together are a flow chart depicting an algorithm for
generating an optimal test isolation protocol for the system of FIG. 2;
and
FIG. 4A-4G, inclusive, are block diagrams respectively showing the format
of the TARGET, GOAL, METHOD, STRESSED PART, STRESSED LEAD and NODAL
CONFLICT data structures used in the algorithm of FIG. 2.
DESCRIPTION OF THE PREFERRED EMBODIMENT
a. Analysis of Exemplary Boards-Under-Test
An appreciation of the invention can be had by considering the BUT examples
which are shown in FIGS. 1A and 1B, and which are to be tested in
accordance with the invention.
In the illustrated circuit BUTl of FIG 1A, an integrated circuit DUT is to
be in-circuit tested. Electronic devices U9 and U17 are up-stream devices
with respect to DUTl, i.e., devices having one or more outputs
electrically connected to one or more inputs of DUTl. In turn, U6 is
up-stream of U9, U44 is up-stream of U17, inverter U67 is upstream of both
DUTl and U7, and U33 is up-stream of U6, U9 and U67.
Initially, the topology and electronic components or parts of BUTl are
analyzed. For example, for reasons explained in the above-referenced U.S.
Pat. No. 4,555,783, since the outputs DA1...DA4 of DUTl are electrically
connected to the outputs OUl...OU4 of U7, U7's outputs are disabled during
testing of DUTl. In addition, since a glitch, i.e., transient spike, on
line DUTl-CK could cause test difficulties, U67 is disabled or inhibited
to prevent glitch propagation to the DUT-CK input of DUTl. However,
glitches on the AIl...AI4 lines will not cause such test difficulties
since it is unlikely that such glitches will occur at critical times
during testing.
To achieve the desired isolation, several alternative isolation methods can
be utilized. For instance, the outputs of U17 and U9 can be disabled or U9
and U17 can be inhibited. To illustrate the invention, the analysis of
different methods of disabling the outputs of U17 and U9 will be
presented. A similar analysis of methods of achieving the inhibiting of U9
and U17 can be derived by those skilled in the art.
The circuit analysis to achieve the desired disabling is as follows----
First, an analysis of circuit topology yields an identification of nodes
available for backdriving. For example, one method of achieving the
disablement is to use nodes SEL.sub.13 AI and SEL2.sub.-- AI (i.e., the
enable inputs of U17 and U9) to disable (e.g., tri-state) the outputs of
U17 and U9. It is possible that U17 cannot be disabled in this way,
however, because SEL2.sub.-- AI is unavailable. This situation would
arise, for instance, either if SEL2.sub.-- AI had to be placed in a
conflicting logic state in order to test DUTl (which would give rise to a
"nodal conflict" or "holding conflict"), or the signal driving SEL2.sub.--
AI were too strong to be backdriven without damaging up-stream devices
(not shown) driving that line.
On the other hand, if the more direct or "brute force" approach were used,
that of backdriving U17's outputs so as to change each of their signals
from LOW to HIGH, the backdriving stress, i.e., the net currents on U17
could be excessive.
A technique for reducing the currents required to backdrive U17 involves
controlling the nodes connecting U44 to U17 in order to generate better
(i.e., more easily backdriven) output signals from U17. For example, U44's
outputs could be backdriven to force U17's outputs to the weaker "HIGH"
state, which would protect U17 by avoiding the need for the application of
the higher backdriving currents to the U17 outputs.
Unfortunately, the stress currents into U44 resulting from this method
could be excessive. An alternative to backdriving the U44 outputs is to
drive its enable input SEL.sub.-- Z to disable U44's outputs.
Similarly, SEL.sub.-- ND, SEL.sub.-- AI and ENCLK.sub.-- DA could be driven
to disable the respective outputs of U6, U9 and U67. While each of the
resulting stress currents in SEL.sub.-- ND, SEL.sub.-- AI and ENCLK.sub.--
DA individually might be at a safe level, the total stress current
experienced by U33 could be excessive. If this were the case, it could be
avoided by driving the TP3 line LOW to protect U33. On the other hand, if
TP3 were not available for this purpose, U33's outputs could be driven
into a weak (HIGH) state to avoid the difficulty; however, if the signals
present on the U33 | | |
