A process for creating self-aligned vertically arrayed planar transistors. The preferred embodiment relates to the simultaneous fabrication of both NPN and PNP planar vertically arrayed transistors in a conventional monolithic, epitaxial, PN junction isolated, integrated circuit. A field oxide is employed to surface isolate the devices and assist in the self-alignment improvement.
A semiconductor device and manufacturing method thereof is disclosed in which a connection pad layer for securing a contact margin is formed on a first conductivity-type area whereas electrodes are connected directly through openings on a second conductivity-type area without the connection pad layer. In the method, an insulating layer is formed on the overall surface of a substrate. Using a mask pattern for exposing the first conductivity-type area, the insulating layer placed on an exposed portion is anisotropically etched so that the remaining insulating layer serves as an impurity-implantation preventing mask in a succeeding first conductivity-type impurity implantation step. A material layer for the connection pad layer is formed prior to the impurity-implantation step and patterned after the impurity implantation. In forming the second conductivity-type area, an additional insulating layer is formed, and using a mask pattern for exposing the second conductivity area, selectively and anisotropically etched so that the remaining insulating layer or the mask pattern for exposing the second conductivity-type area serves as an impurity-implantation preventing mask.
The invention relates to a method of making a monolithic integrated circuit with at least one CMOS field-effect transistor and one npn bipolar transistor wherein a thin oxide layer is covered with a protective polysilicon layer in both the bipolar-transistor area and the field-effect-transistor area.
A lateral bipolar transistor (10) includes a retrograde doping profile (21) that is formed within a substrate (11) to form the transistor's (10) collector region (14). A base region (16) that includes an inactive base area and an active base area (17) is formed in the collector region (14). An emitter (18) is formed within the active base area (17) wherein current (22) flows through the emitter (18) through the active base area (17) and through the collector region (14). The base region, the emitter, and a collector contact region are all formed by driving dopants from an overlying polysilicon layer.
A process for forming an oxide layer on a sidewall of a trench in a substrate. The process comprises the steps of forming the trench in the substrate, forming a nitride interface layer over a portion of the trench sidewall, forming an amorphous layer over the nitride interface layer, and oxidizing the amorphous layer to form the oxide layer. The process may be used, for example, to form a gate oxide for a vertical transistor, or an isolation collar. The invention also comprises a semiconductor memory device comprising a substrate, a trench in the substrate having a sidewall, an isolation collar comprising an isolation collar oxide layer on the trench sidewall in an upper region of the trench, and a vertical gate oxide comprising a gate oxide layer located on the trench sidewall above the isolation collar. The isolation collar oxide layer is disposed over an isolation collar nitride interface layer between the isolation collar oxide layer and the trench sidewall, the gate oxide layer is disposed over a gate nitride interface layer between the gate oxide layer and the trench sidewall, or both.
