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FIELD OF THE INVENTION
The present invention relates to processes for simultaneously fabricating
bipolar and complimentary field-effect transistors in a semiconductor
substrate.
BACKGROUND OF THE INVENTION
In recent years much effort has been directed toward perfecting a method of
integrating bipolar and complimentary metal oxide semiconductor (CMOS)
technologies on a single wafer. The ability to combine CMOS with bipolar
processes in a single ("BiCMOS") process is extremely desirable for high
performance circuits. For example, CMOS transistors are inherently low
power devices with large noise margins that can achieve a high packing
density. Meanwhile, bipolar transistors provide advantages in switching
speed and current drive. Bipolar transistors are also characterized by
high transconductance which is well suited for driving capacitive loads.
One of the difficulties presented in integrating an MOS device with a
bipolar device in the same circuit is that the fabrication steps required
to form each of the separate devices often differ radically. That is, the
steps used to fabricate a bipolar device are vastly different from the
steps required to fabricate a CMOS or an MOS device. As a result,
conventional processes are often lengthy and complicated, using a large
number of masking operations and numerous thermal cycles.
Another basic limitation to prior art processes has to do with the nature
of optical lithography and its affect on the attainable circuit density.
In the widely used technique of projection printing, an image of the
patterns on the mask is projected onto a resist coated wafer. Upon the
exposure of an individual chip site the wafer is moved or stepped on an
interferometrically controlled XY table to the next site and the process
is repeated. Using state-of-the-art optics, projection printing (also
frequently referred to as direct-step-on-wafer or step-and-repeat) systems
are capable of producing sub-micron resolutions.
However, this high level of resolution does not come without a
corresponding trade-off. The trade-off in this case is the limited depth
of focus over which the image quality is maintained. For projection
printing, the depth of the focus is approximated by the equation
d.f.(depth of focus)=.lambda./2(NA).sup.2
where NA is the numerical aperture of the projection optics and .lambda. is
the exposure wavelength. Thus, high resolution (very large numerical
aperture) is achieved at the expense of a very shallow depth of focus.
In other words, the ability to print a highly dense circuit layout, having
minimal device sizes and structures, is especially dependant on the
existence of a highly planar surface on which geometric shapes from a mask
may be transferred. Unfortunately, the requirement of a highly planar
surface is completely at odds with orthodox methods of forming a
semiconductor circuit in a silicon substrate.
Traditionally, in fabricating an integrated circuit the silicon substrate
layer is first subject to oxidation. Openings are etched in the oxide, and
then impurities are introduced or implanted into the substrate. Next, the
silicon surface is either reoxidized or subjected to depositions of
polysilicon, CVD oxide, silicon nitride, etc. The result of these
successive processing steps (e.g., oxidation, etching, implantation,
reoxidation) are large steps or incongruities running across the surface
of the wafer. Obviously, over the course of the entire process these steps
or incongruities lead to a non-uniform, non-planar wafer surface.
Consequently, the ability to maintain high image quality (due to the depth
of focus problems described above) is substantially degraded in prior
methods.
One way in which practitioners have attempted to minimize this problem is
to planarize the surface of the wafer by reflowing a boron-phosphosilicate
glass across the wafer surface prior to contact mask. The surface is then
aggressively planarized using sophisticated etchants when the metalization
steps are reached. Despite these attempts to replanarize the wafer surface
in the back-end processing steps, the lack of planarization in the
front-end processing steps (i.e., those steps leading up to the contact
mask step) has already taken its toll on the devices. The inability to
pattern compact and high-resolution device structures brings about
low-density, low-performance circuits. Hence, past semiconductor
processes, and particularly BiCMOS processes, have not been able to take
full advantage of the high numerical aperture (i.e., resolution) which
modern optical equipment can produce due to the depth of focus problem.
The critical importance of maintaining planarization throughout each and
every processing step is therefore appreciated.
As will be seen, the presently invented BiCMOS process maintains an
extremely high level of planarization throughout all of the processing
steps using a novel technique known as "waffelization". When combined with
a number of additional novel processing features (each of which is
believed to be separately inventive in its own right) the disclosed BiCMOS
process is capable of producing device dimensions and circuit densities
well beyond the limits of the prior art. For example, using the presently
invented process it is possible to produce gate widths of 0.5 microns or
less on MOS-type devices and emitter widths of roughly 0.2 microns for
bipolar transistors. Consequently, it is contemplated that a 6-transistor
memory cell may easily be fabricated within an area of about 3.0.times.4.8
microns--or a total dimension of approximately 14.4 square microns. This
is about the size of a via contact opening in many prior processes.
In addition to achieving high circuit densities and high device performance
through planarization of the wafer surface, the invented BiCMOS process is
also characterized by its simplicity, reliability, its self-aligning
nature, and the overall design flexibility provided--both from a circuit
design perspective as well as an applications specific viewpoint.
Other prior art known to Applicant includes U.S. Pat. No. 4,727,046 of
Tuntasood et al.; U.S. Pat. No. 4,826,783 of Choi et al.; and U.S. Pat.
No. 4,816,423 of Havemann.
SUMMARY OF THE INVENTION
The present invention disclosed and claimed herein describes a process
whereby MOS transistors and bipolar transistors are formed together in the
same silicon substrate. In one embodiment, the invented process comprises
the steps of first defining separate active areas in a substrate or
epitaxial layer for each of the transistors. Active areas are defined by
forming shallow recessed field oxidation regions in the substrate.
Utilizing shallow field regions helps to reduce bird's-beak encroachment
into the active areas and also produces a more planarized surface.
Next, a gate dielectric layer is formed over the surface of the wafer.
Above the gate dielectric, a first layer of polysilicon is deposited. This
first layer of polysilicon is then masked and selectively etched to form a
plurality of first polysilicon members each of which is equally-spaced
apart from one another. In other words, a plurality of spaces of equal
width are etched into the polysilicon down to the underlying gate
dielectric or substrate. The polysilicon members formed in this step
comprise the gates of the MOS transistors and the extrinsic base contacts
of the bipolar transistors.
After the first polysilicon members have been defined, the base regions of
the bipolar transistors are formed by doping of the appropriate active
areas. The first polysilicon members are then fully insulated by forming
an oxide layer over the sidewalls and tops of each of the members. An
additional layer of polysilicon is then deposited over the substrate to a
thickness sufficient to cover the first polysilicon members and planarize
the entire wafer surface. The additional layer of polysilicon uniformly
fills each of the gaps or spaces formed during the previous etching step.
The additional layer of polysilicon is then etched to form a plurality of
second polysilicon members which are electrically isolated from the first
polysilicon members. Impurities, which are either present in the deposited
additional polysilicon layer or are introduced by a supplemental step, are
then diffused into the substrate to form the source/drain regions of the
MOS transistors, and the extrinsic base and emitter regions of the NPN
transistors. Moreover, the second polysilicon members also optionally form
a first interconnect layer for the completed circuit. The final processing
steps include those steps essential to the interconnection of the MOS and
bipolar transistors.
The manifold inventive concepts embodied by the presently invented BiCMOS
process are best described and understood by reference to the detailed
description which follows. Each novel concept contributes certain
technical advantages--the sum of which engenders an especially
high-performance, highly-reliable and highly-dense circuit. The process
itself is characterized by its simplicity, its self-aligning nature and
the extreme level of planarization sustained throughout. A litany of the
technical advantages and features of the invented process includes:
1. Planarization of the wafer surface through the process of waffelization.
Beginning with the earliest processing steps, planarization is maintained
all the way through metalization.
2. Use of a very thin field oxidation to preserve a narrow active pitch.
This overcomes the problem of bird's-beak and interconnect coupling
capacitance.
3. The availability of n-type and p-type MOSFETs in both enhancement,
depletion and zero-threshold modes. A single masking step is employed for
each type of device (n-type or p-type).
4. Use of amorphous polysilicon to facilitate planarization and avoid
impressing a harmful grain structure into the substrate in the emitter
regions of the bipolar transistors.
5. Self-aligned well compensation in a single masking step for the MOS
transistors.
6. Use of polysilicon as an interconnect layer and as a diffusion source
for creating hyper-shallow PN junctions.
7. Use of cobalt silicide as a contact to polysilicon. Cobalt silicide
permits the formation of highly self-aligned contacts which may overlap
gate, oxide and isolation regions.
8. An air-bridge interconnect system which utilizes polyimide as an
intemediate dielectric layer. Optionally, the polyimide may be removed;
thereby forming voids which act to reduce interlayer coupling capacitance
to a minimum. Alternatively, these voids may be "backfilled" with various
arbitrary materials to create exotic types of semiconductor devices aimed
at specific applications.
BRIEF DESCRIPTION OF THE DRAWINGS
The novel features believed characteristic of the invention are set forth
in the appended claims. The invention itself, however, as well as other
features and advantages thereof, will be best understood by reference to
the detailed description which follows, read in conjunction with the
accompanying drawings, wherein:
FIGS. 1A and 1B are cross-sections of a semiconductor structure
illustrating the starting wafer material and the separate regions for
forming NPN bipolar, n-channel field-effect, and p-channel field-effect
transistors.
FIGS. 2A and 2B are cross-sections following formation of an n+ buried
layer.
FIGS. 3A and 3B are cross-sections following formation of an epitaxial
layer.
FIGS. 4A and 4B are cross-sections after formation of separate p and n-well
regions.
FIGS. 5A and 5B are cross-sections after formation of field oxidation
regions.
FIGS. 6A and 6B are cross-sections after opening an area for the NPN
bipolar base region.
FIGS. 7A and 7B are cross-sections following deposition of the first
polysilicon layer.
FIGS. 8A and 8B are cross-sections following gate etch.
FIGS. 9A and 9B are cross-sections following implantations of n and p-type
lightly doped regions, the bipolar base regions, and the well compensation
implants.
FIGS. 10A and 10B are cross-sections following oxide side wall spacer etch.
FIGS. 11A and 11B are cross-sections following planarization poly
deposition.
FIGS. 12A and 12B are cross-sections after planarization poly etch back.
FIGS. 13A and 13B are cross-sections after isolation oxide regions have
been formed.
FIGS. 14A and 14B are cross-sections illustrating source, drain, emitter,
implants into the planarized poly regions.
FIGS. 15A and 15B are cross-sections following source, drain and emitter
doping and drive-in.
FIGS. 16A and 16B are cross-sections following opening of the gate contact
regions.
FIGS. 17A and 17B are cross-sections after formation of cobalt silicide
contact regions.
FIGS. 18A and 18B are cross-sections following formation of poly/poly
contacts.
FIGS. 19A and 19B are cross-sections following deposition and masking of
titanium used for poly 2 silicide.
FIGS. 20A and 20B are cross-sections after deposition of poly 2 and the
nitride top layer.
FIGS. 21A and 21B are cross-sections after poly 2 mask.
FIGS. 22A and 22B are cross-sections following masking for pedestal
contacts.
FIGS. 23A and 23B are cross-sections following formation of pedestal
contacts.
FIGS. 24A and 24B are cross-sections following metal 1 mask.
FIGS. 25A and 25B are cross-sections following formation of via pedestals.
FIGS. 26A and 26B are cross-sections after formation of metal 2
interconnection regions.
DESCRIPTION OF THE PREFERRED EMBODIMENT(S)
A novel BiCMOS process for simultaneously forming bipolar transistors and
MOS transistors in the same semiconductor substrate is disclosed. In the
following description, numerous specific details are set forth, such as
specific conductivity types, dopants, thicknesses, etc., in order to
provide a more thorough understanding of the present invention. It will be
obvious, however, to one skilled in the art that these specific details
are not necessary to practice the present invention. In other instances,
other well-known processing steps and methods have not been shown in
detail in order to avoid unnecessarily obscuring the present invention.
FORMATION OF THE ACTIVE REGIONS FOR THE BJTs AND MOSFETs
Referring to FIGS. 1A and 1B, a cross-sectional view of the starting
semiconductor substrate 10 is shown. Substrate 10 has a crystal
orientation of <100> and has been doped with a p-conductivity type
impurity to a resistivity of approximately 10 ohm-centimeters. Orientation
<100> is used because it provides the lowest possible surface state
density. This is standard practice for MOS processing. Optionally, the
back side of the wafer may be coated with a polysilicon layer as a means
for introducing dislocations into the crystalline structure--the
dislocations acting as impurity trapping sites for heavy metals.
Next, alignment marks are etched into the surface of the wafer using a
reactive ion etch (RIE). These alignment marks are in the form of crosses,
squares, etc., and are used as an alignment reference for subsequent
masking layers. The alignment marks are formed using an alignment mask
aligned to the wafer in accordance with standard photolithographic
techniques. (e.g., depositing photoresist, masking the surface of the
substrate, exposing the masked substrate to ultraviolet light, developing
the photoresist, etc.). Considering the high degree of planarization
achieved by the invented processes, reference alignment marks provide a
simple and easy method of maintaining mask registration throughout later
processing steps.
It should be understood that the alignment mask is an optional masking step
in the presently invented process. Alternatively, visual alignment may be
made to the implanted buried layer regions. However, since the surface of
the wafer will be highly planarized throughout the entire process--making
visual mask registration difficult--the inclusion of the alignment mask
step is preferred. Furthermore, because of the contribution each oxide
step has toward defeating planarization, it is desirable to avoid
generating a buried layer oxide boundary edge simply for alignment
purposes.
With reference to FIGS. 2A and 2B, buried layer regions 12 and 13 are
formed using conventional ion implantation techniques. Antimony ions are
implanted at an energy of approximately 180 KeV and at a dose of
approximately 1.0.times.10.sup.15 atoms per square centimeter
(atoms/cm.sup.2). Buried layer 13 forms the n+ collector region for NPN
bipolar transistor 20 while buried layer region 12 forms an n+ doped
region under p-channel transistor 40.
Following the antimony ion implantation, a p-type epitaxial layer 15 is
deposited over the surface of the wafer as shown in FIGS. 3A and 3B.
Epitaxial layer 15 is approximately 2 microns thick and is doped p-type to
a concentration of about 1.0.times.10.sup.17 atoms/cm.sup.3. Layer 15 is
formed by exposing the wafers to a diclorosilane (SiH.sub.2 Cl.sub.2) gas
at approximately 1050.degree. C. The antimony ions in buried layer regions
12 and 13 are subsequently driven (i.e., diffused) downward into
p-substrate 10 and upward into epitaxial layer 15 at a temperature of
about 1100.degree. C. for approximately five hours in an atmosphere
consisting of N.sub.2 +5% 0.sub.2. The drive-in cycle helps to repair
damage done to the substrate surface during ion implantation.
Next, an n-well mask is employed to mask off those regions of epitaxial
layer 15 which will subsequently become p-well regions. The exposed areas
of epitaxial layer 15 are then subjected to a phosphorous ion implant at
an energy of 180 KeV and a dose of 2.5.times.10.sup.13 atoms/cm.sup.2.
After this implant, epitaxial layer 15 is divided into separate n-well and
p-well regions as shown in FIGS. 4A and 4B.
In FIGS. 4A and 4B, n-well region 23 is utilized in the formation of
p-channel field-effect transistor (FET) 40. P-well region 21 furnishes the
proper conductivity type region for the formation of n-channel FET 30.
N-well region 22 is similarly utilized in the formation of NPN bipolar
junction transistor (BJT) 20.
Referring to FIGS. 5A and 5B, another high-energy implant is employed to
form the collector plug region 25, which functions as a low resistance
vertical contact down to the underlying n+ buried layer region 13. As
mentioned earlier, buried layer region 13 eventually forms the collector
of NPN transistor 20. After appropriate masking, phosphorous ions are
implanted at an energy of 180 KeV and a dose of 1.0.times.10.sup.15
atoms/cm.sup.2. The collector drive and n-well drive are performed
simultaneously at 1100.degree. C. for approximately six hours in an
atmosphere comprising N.sub.2 +5% 0.sub.2. The N.sub.2 +5% 0.sub.2 gas
helps to establish an equilibrium between nitridation and oxidation of the
surface of the wafer. This prevents excessive nitridation of the wafer
surface which is usually undesirable.
Following the collector plug and n-well drive cycles, a thin (approximately
250 .ANG.) pad silicon dioxide layer is grown across the entire surface of
the wafer. This pad oxide is grown in a furnace at 900.degree. Celsius (C)
for fifteen minutes using an oxygen gas flow. A standard silicon nitride
deposition using gas phase, low pressure chemical vapor deposition (LPCVD)
techniques follows growth of the pad oxide. This silicon nitride layer
acts as a mask layer during formation of the field oxide regions. Growing
a pad oxide beneath the nitride layer markedly reduces stress induced
dislocations in the underlying silicon substrate. (Note that the pad oxide
is not shown in the Figures because of the relative thinness of that
layer).
The growth of the field oxide (FOX) regions are performed using the
well-known processing method known as recess oxidation (ROX). In the
recess oxidation method a thick field oxide layer is first grown thermally
in the patterned FOX regions. Due to the fact that thermally grown oxide
takes up more volume than does single crystalline silicon, there is a
substantial volume of silicon dioxide which grows above the planar surface
of the substrate. This elevated portion of the silicon dioxide is
subsequently etched isotropically to produce a recessed surface across the
wafer. After etching the wafer surface is again oxidized, resulting in a
nearly planar surface. Active regions for the devices are defined by the
FOX regions at this point in the process.
Normally, field oxidation produces what is commonly referred to as
birds'-head or birds'-beak features. These formations consist of an oxide
bump (birds'-head) along with a lateral growth of oxide (birds'-beak) at
the silicon nitride boundaries. The length of the birds'-beak is
proportional to the thickness of the field oxide layer. Typically, lateral
oxide penetration is between one-half and one times the field oxide
thickness. The birds'-beak phenomena sets a fundamental limit on the pitch
of the active region; that is, how close active layers can be placed
adjacent to one another.
In the presently invented process, field oxide regions are defined using a
high resolution active layer mask which opens selected areas in the
silicon nitride layer. The nitride is etched anisotropically using a
reactive ion etch (RIE). A first field oxide layer is then grown in these
openings at 900.degree. C. in steam to form a 2000 .ANG. oxide film. This
first field oxide film is then dipped off in a 10:1 solution of hydrogen
fluoride (HF) 48% and water. A second field oxide layer is then grown at
900.degree. C. in steam to form an approximately 1000-2000 .ANG. field
oxide layer 28 as shown in FIGS. 5A and 5B.
Because the field oxide thickness in the invented process is relatively
thin when compared to prior art methods, the penetration of the
birds'-beak into the active layer regions is markedly reduced. By way of
example, active layer spacing is on the order of 1.0 microns. Previously,
attempts to reduce the thickness of the field oxide region were avoided
since a thin field oxide generally corresponds to a high coupling
capacitance between the substrate and the overlying metal interconnects.
The reason why a relatively thin field oxide is tolerated in the presently
invented process is because the interconnection layers are not in contact
with, nor in close proximity to, the substrate surface. This aspect of the
present invention will be described later.
In addition, because field plate isolation is used in the presently
invented BiCMOS process, the surface potential is easy controlled. Also,
use of field plate isolation and thin field oxide contributes greatly to
the radiation hardness of the circuit. This is of critical importance in
certain military applications. FIGS. 5A and 5B show field oxidation
regions 28 after the silicon nitride masking layer has been removed.
Yet another advantage of using a thin field oxide is that by choosing a
silicon nitride mask layer thickness carefully, the field threshold
adjustment implant can penetrate through the field oxide after it is
grown, as well as the silicon nitride layer. In this way, a single implant
may be utilized to provide correct V.sub.T for the transistors while
simultaneously providing the proper field threshold level.
When used in this manner, the silicon nitride acts as a sort of
DECELERATING or breaking layer--setting a shallow depth for the implant
dose in the transistor active regions. Optionally, the silicon nitride
layer can be removed prior to the field implant, resulting in
significantly higher channel mobilities due to the deeper implant. Higher
channel mobility translates into better transistor performance due to the
corresponding reduction in impurity scattering.
The ability to perform transistor threshold and field implants
simultaneously also provides great flexibility in selecting device types.
For example, if boron is implanted in an n-channel device an
enhancement-mode n-channel MOSFET having a threshold of approximately 0.5
volts is produced. On the other hand, if this implant is left out of the
active regions (by appropriate masking) then a natural device (i.e.,
approximately 0 volt V.sub.T) results. Furthermore, if the p-type
enhancement-mode device implant is directed into the n-channel
transistors, a -0.5 volt V.sub.T depletion mode device is created.
Moreover, a single masking/implant process step can be used to change the
characteristics of selected field-effect devices from enhancement-mode, to
depletion-mode, or to zero threshold type devices. Because of the symmetry
between n-channel and p-channel devices each individual transistor is
available in all three types. This results in a substantial savings in
masking steps and allows interesting device type combinations. By way of
example, it might be desired to produce a NAND gate which uses an
enhancement-mode lower device and a zero threshold upper device.
Ion implantation is a most valuable tool for controlling threshold voltage.
Very precise quantities and purities can be introduced making it possible
to maintain extremely close control of V.sub.T. For instance, where boron
is implanted through a gate oxide for a p-channel device, the negatively
charged boron acceptors serve to reduce the effects of the positive
surface state charge. As a result, V.sub.T becomes less negative.
Similarly, a shallow boron implant into the p-type substrate of an
n-channel transistor can make V.sub.T positive--as required for an
enhancement device. The capability, as described above, of allowing
enhancement, depletion, and zero threshold type devices to be incorporated
on the same chip using a single implant therefore provides many advantages
to the integrated circuit designer.
In the currently preferred embodiment, the n-type V.sub.T and field implant
mask aligns to the active layer region. A boron ion implantation follows
at an energy of 100 KeV and a dose of approximately 5.times.10.sup.12
atoms/cm.sup.2. Following this implant, a p-type V.sub.T and field implant
is performed. The masking layer is aligned to the active layer and
phosphorous ions are implanted at 180 KeV with a dose of approximately
1.times.10.sup.13 atoms/cm.sup.2. Following the threshold implants, the
field nitride regions are reactive ion etched until removed, then the
underlying pad oxide is dipped off in a 100:1 solution of water and HF.
FORMATION OF THE GATE DIELECTRIC
At this point in the process we are ready to form the gate oxide for the
n-channel and p-channel FETs. After the pad oxide etch there can exist
residual nitride films around the birds'-beak regions. These residual
films can suppress subsequent oxidation resulting in a thinner gate oxide
in these areas. To insure that this residual nitride is completely removed
a first gate oxide layer of approximately 200 .ANG. is grown in a furnace
at 900.degree. C. in an atmosphere of 87% argon, 10% 0.sub.2 and 3% HCI.
Immediately afterwards this first gate oxide is dipped off in a 100:1
solution of HF. This extra growth and etching step insures complete
removal of residual nitride films. The second gate oxide (i.e., the actual
gate oxide used in the devices) is also grown in a furnace at 900.degree.
C. using the same gas as was used in growth of the first gate oxide. This
second gate oxide layer is carefully grown to a thickness of approximately
100 .ANG..
After the gate oxide has been formed, selected regions must be removed to
create buried contacts down to the substrate. One example is in the case
of bipolar NPN transistor 20 where a buried contact is needed for
electrical connection down to the extrinsic base region. Traditionally,
buried contacts are formed by first spinning a layer of photoresist over
the gate oxide, developing the photoresist, etching the gate oxide in the
contact areas, then depositing polysilicon. This technique has been widely
used in NMOS transistor processes.
Conversely, because the presently invented BiCMOS process employs a gate
oxide which is extremely thin (approximately 100 .ANG.), it is undesirable
to expose this thin oxide to reactive chemicals. Therefore, in the
invented process after the growth of the gate oxide layer is completed, a
first polysilicon deposition is performed in a furnace at 580.degree. C.
This produces a thin (approximately 500 .ANG.) layer of amorphous
polysilicon which covers all of the gate oxide previously grown. This thin
layer of polysilicon acts to cap the very thin gate oxide prior to the
formation of the buried contacts.
It is significant that this first protective polysilicon layer is amorphous
in structure. By its nature, amorphous polysilicon is highly smooth and
contains no embedded grain structure. In contrast, ordinary polysilicon
(grown at a higher temperature) is generally much rougher and more
granular than amorphous polysilicon. When ordinary polysilicon is reactive
ion etched down to the single crystalline silicon substrate the grain
structure of the polysilicon can become imprinted into the substrate
surface. This causes considerable damage to the underlying crystal lattice
and can diminish device performance, particularly in bipolar junction
transistors.
FIGS. 6A and 6B show cross-sections in which the protective polysilicon
layer 26 is opened in base contact region 27 using conventional masking
techniques. The base contact regions of layer 26 are first etched using a
reactive ion etch and then the underlying gate oxide is dipped off in a
100:1 solution of water and HF. (Note that in FIGS. 6A and 6B the
underlying gate oxide layer is not shown due to its relative thinness when
compared with other layers). The opening over region 27 is utilized to
later form buried base contacts for BJT 20.
An important feature of the invented process is that both n-type and p-type
buried contacts are available. This is in contrast with standard MOS
processes where all of the polysilicon is typically doped n-type so that
buried contacts to p-channel FETs or p-type BJT base regions are generally
not available. If an attempt were made to form buried contacts to a p-type
substrate using n-type polysilicon the n-type dopant from the polysilicon
would diffuse down and form a PN junction with the underlying p-type
material. In the presently invented process, p-type polysilicon is used in
p-type channel FETs and an n-type polysilicon is utilized in n-channel
FETs. Hence, as will be described in more detail below, symmetric buried
contacts are available.
FORMATION OF FIRST LEVEL POLYSILICON MEMBERS
After the buried contact regions have been opened, a second, much thicker,
layer of polysilicon is deposited over the wafer. In the preferred
embodiment, the second polysilicon deposition occurs in a furnace at
580.degree. C. This produces an amorphous layer which is approximately
2000 .ANG. thick. Again, it is important that the second polysilicon
deposition be amorphous to maintain an extremely smooth and planar
surface.
In FIGS. 7A and 7B, the amorphous second polysilicon layer is shown as
layer 31. Note that polysilicon layer 31 completely covers field oxidation
regions 28 as well as base contact region 27. It is understood, of course,
that there is no gate oxide present in base region 27 underlying poly
layer 31. As described above, this oxide was removed in a previous
processing step. But gate oxide does underlie poly layer 31 over the
channel regions of n-channel FET 30 and p-channel FET 40.
Following the deposition of poly layer 31 a high temperature TEOS
(tetra-ethyl-ortho-silicon) oxide 32 is deposited over the surface of poly
layer 31. Reoxidation of poly layer 31 is avoided to prevent
recrystalization of poly layer 31. A reoxidation cycle might also destroy
the amorphous nature of layer 31 and form asperities therein.
Note also that in FIGS. 7A and 7B, poly layer 31 is illustrated as a
uniformly planar surface for ease of representation. Actually, there
exists a physical step over each of the buried contact regions. The height
of the step being equal to the thickness of the protective poly layer 26
(see FIGS. 6A and 6B) plus the thickness of the gate oxide. The sum of the
gate oxide and poly layers, and therefore the height of the step, is about
500 .ANG.. (For purposes of discussion, the surface of the wafer is
considered planar whenever any step or feature is 1000 .ANG. or less in
height.)
Referring now to FIGS. 8A and 8B, next in the sequence of steps is the
polysilicon gate etch. To perform the gate etch an extremely high
resolution masking layer is aligned back to the active layer of the
devices. A reactive ion etch of oxide layer 32 is followed by a second
reactive ion etch which anisotropically etches the underlying polysilicon
layer. By using a highly selective etchant the anisotropic etch of the
polysilicon stops on the thin gate oxide.
Recall that where emitters are to be formed there is no existing gate oxide
to stop on. Over etching in these regions is potentially hazardous to the
underlying crystal lattice. However, if amorphous polysilicon is used as
described above, no grain pattern is impressed into the substrate. Thus
the electrical properties of the emitter junction are maintained. Because
of the use of amorphous polysilicon, over etching in the emitter regions
does not have a deleterious effect on device performance.
Following the poly gate etch, a slight oxidation of the exposed sidewall
polysilicon is performed. Approximately 1000 .ANG. of oxide is grown on
the poly in the polysilicon in a furnace at 900.degree. C. in a steam
atmosphere. Oxidizing the poly gate sidewalls helps to marginally reduce
the gate width while fully insulating each of the polysilicon members. It
also creates a minute birds'-beak at the silicon interface which reduces
the electric field density near the polysilicon edges and corners.
Oxidation of the sidewalls also densifies the top oxide layer 32.
At this point in the process, gate 33 of p-channel FET 40 has been defined
along with gate 34 of n-channel FET 30 and the extrinsic base contacts 35
of NPN bipolar transistor 20. Additionally, polysilicon members 36 have
also been defined along the surface of the wafer. The function of
polysilicon members 36 will be explained in more detail later.
Note that in FIGS. 8A and 8B, uniform spaces 38 have been defined between
each polysilicon member. In the currently preferred embodiment, spacings
38 are each about 0.5 microns in width. Maintaining a controlled and
accurate polysilicon spacing 38 across the entirety of the wafer is of
crucial importance to the goal of planarization. When viewed from the top,
these uniform polysilicon spacings 38 create a "waffle-like" pattern
across the surface of the wafer. Hence, the origin of the term
"waffelization" to denote the technique for achieving complete
planarization of the semiconductor surface.
Using a controlled poly space 38 (all polysilicon spaces being equal in
dimension, i.e., "waffelized") makes possible the invented planarization
scheme. This scheme is based on the isotropic (i.e., uniform in all
directions) deposition of a material--in this case polysilicon--followed
by an unmasked anisotropic (i.e., vertical) etch. Once spaces 38 have been
etched out of the polysilicon layer and a sidewall oxide formed, an
isotropic deposition of amorphous polysilicon is used to fill in spaces
(i.e., the gaps between the previously patterned polysilicon lines). Since
the spaces 38 are uniform across the wafer, each is filled at the same
time and at an identical rate.
Deposition continues until a totally planar surface is produced. Generally,
this requires a polysilicon deposition to a thickness which is
approximately twice the thickness of members 36. The anisotropic etch of
this second polysilicon layer reduces the thi | | |
