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Description  |
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This invention is in the field of semiconductor memories, and is
specifically directed to the entry into special test modes for such
memories.
This application is related to application Ser. No. 552,567, incorporated
herein by this reference. This application is also related to applications
Ser. Nos. 569,009, now U.S. Pat. No. 5,072,137, 568,968, 569,000, 570,148,
569,002, 570,124, and 570,203, now U.S. Pat. No. 5,072,138, all
contemporaneously filed with this application. All of these applications
are assigned to SGS-Thomson Microelectronics, Inc.
BACKGROUND OF THE INVENTION
In modern high density memories, such as random access memories having
2.sup.20 bits (1 Megabit) or more, the time and equipment required to test
functionality and timing of all bits in the memory constitutes a
significant portion of the manufacturing cost. Accordingly, as the time
required for such testing increases, the manufacturing costs also
increase. Similarly, if the time required for the testing of the memory
can be reduced, the manufacturing cost of the memories is similarly
reduced. Since the manufacturing of memory devices is generally done in
high volume, the savings of even a few seconds per device can result in
significant cost reduction and capital avoidance, considering the high
volume of memory devices produced.
Random access memories (RAMs) are especially subject to having significant
test costs, not only because of the necessity of both writing data to and
reading data from each of the bits in the memory, but also because RAMs
are often subject to failures due to pattern sensitivity. Pattern
sensitivity failures arise because the ability of a bit to retain its
stored data state may depend upon the data states stored in, and the
operations upon, bits which are physically adjacent to a particular bit
being tested. This causes the test time for RAMs to be not only linearly
dependent upon its density (i.e, the number of bits available for storage)
but, for some pattern sensitivity tests, dependent upon the square (or 3/2
power) of the number of bits. Obviously, as the density of RAM devices
increases (generally by a factor of four, from generation to generation),
the time required to test each bit of each device in production increases
at a rapid rate.
It should be noted that many other integrated circuit devices besides
memory chips themselves utilize memories on-chip. Examples of such
integrated circuits include many modern microprocessors and
microcomputers, as well as custom devices such as gate arrays which have
memory embedded therewithin. Similar cost pressures are faced in the
production of these products as well, including the time and equipment
required for testing of the memory portions.
A solution which has been used in the past to reduce the time and equipment
required for the testing of semiconductor memories such as RAMs is the use
of special "test" modes, where the memory enters a special operation
different from its normal operation. In such test modes, the operation of
the memory can be quite different from that of normal operation, as the
operation of internal testing can be done without being subject to the
constraints of normal operation.
An example of a special test mode is an internal "parallel", or multi-bit,
test mode. Conventional parallel test modes allow access to more than one
memory location in a single cycle, with common data written to and read
from the multiple locations simultaneously. For memories which have
multiple input/output terminals, multiple bits would be accessed in such a
mode for each of the input/output terminals, in order to achieve the
parallel test operation. This parallel test mode of course is not
available in normal operation, since the user must be able to
independently access each bit in order to utilize the full capacity of the
memory. Such parallel testing is preferably done in such a way so that the
multiple bits accessed in each cycle are physically separated from one
another, so that there is little likelihood of pattern sensitivity
interaction among the simultaneously accessed bits. A description of such
parallel testing may be found in McAdams et al., "A 1-Mbit CMOS Dynamic
RAM With Design-For-Test Functions", IEEE Journal of Solid-State Circuits,
Vol SC-21, No. 5 (October 1986), pp. 635-642.
Other special test modes may be available for particular memories. Examples
of tests which may be performed in such modes include the testing of
memory cell data retention times, tests of particular circuits within the
memory such as decoders or sense amplifiers, and the interrogation of
certain portions of the circuit to determine attributes of the device such
as whether or not the memory has had redundant rows or columns enabled.
The above-referenced article by McAdams et al. describes these and other
examples of special test functions.
Of course, when the memory device is in such a special test mode, it is not
operating as a fully randomly accessible memory. As such, if the memory is
in one of the test modes by mistake, for example when installed in a
system, data cannot be stored and retrieved as would be expected for such
a memory. For example, when in parallel test mode, the memory writes the
same data state to a plurality of memory locations. Accordingly, when
presented with an address in parallel test mode, the memory will output a
data state which does not depend solely on the stored data state, but may
also depend upon the results of the parallel comparison. Furthermore, the
parallel test mode necessarily reduces the number of independent memory
locations to which data can be written and retrieved, since four, or more,
memory locations are simultaneously accessed. It is therefore important
that the enabling of the special test modes be accomplished in such a
manner that the chance is low that a special test mode will be
inadvertently entered.
Prior techniques for entry into special test mode include the use of a
special terminal for indicating the desired operation. A simple prior
technique for the entry into test mode is the presentation of a logic
level, high or low, at a dedicated terminal to either select the normal
operation mode or a special test mode such as parallel test, as described
in U.S. Pat. No. 4,654,849. Another approach for the entry into test mode
using such a dedicated terminal is disclosed in Shimada et al., "A 46-ns
1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits, Vol. 23, No. 1,
(February 1988) pp. 53-58, where a test mode is enabled by the application
of a high voltage to a dedicated control pad while performing a write
operation. These techniques are relatively simple but they of course
require an additional terminal besides those necessary for normal memory
operation. While such an additional terminal may be available when the
memory is tested in wafer form, significant test time also occurs after
packaging, during which special test modes are also useful. In order to
use this technique of a dedicated test enable terminal for package test,
it is therefore necessary that the package have a pin or other external
terminal for this function. Due to the desires of the system designer that
the circuit package be as small as possible, with as few connections as
possible, the use of a dedicated pin for test mode entry is therefore
undesirable. Furthermore, if a dedicated terminal for entering the test
mode is provided in packaged form, the user of the memory must take care
to ensure that the proper voltage is presented to this dedicated terminal
so that the test mode is not unintentionally entered during system usage.
Another technique for enabling special test modes is the use of an
overvoltage signal at one or more terminals which have other purposes
during normal operation, such overvoltage indicating that the test mode is
to be enabled, such as is also described in U.S. Pat. No. 4,654,849, and
in U.S. Pat. No. 4,860,259 (using an overvoltage on an address terminal).
Said U.S. Pat. No. 4,860,259 also describes a method which enables a
special test mode in a dynamic RAM responsive to an overvoltage condition
at the column address strobe terminal, followed by the voltage on this
terminal falling to a low logic level. The McAdams et al. article cited
hereinabove, describes a method of entering test mode which includes the
multiplexing of a test number onto address inputs while an overvoltage
condition exists on a clock pin, where the number at the address inputs
selects one of several special test modes. Such overvoltage enabling of
special test modes, due to its additional complexity, adds additional
security that special test modes will not be entered inadvertently,
relative to the use of a dedicated control terminal for enabling the test
modes.
However, the use of an overvoltage signal at a terminal, where that
terminal also has a function during normal operation, still is subject to
inadvertent enabling of the special mode. This can happen during "hot
socket" insertion of the memory, where the memory device is installed into
a location which is already powered up. Depending upon the way in which
the device is physically placed in contact with the voltages, it is quite
possible that the terminal at which an overvoltage enables test mode is
biased to a particular voltage before the power supply terminals are so
biased. The overvoltage detection circuit conventionally used for such
terminals compares the voltage at the terminal versus a power supply or
other reference voltage. In a hot socket insertion, though, the voltage at
the terminal may be no higher than the actual power supply voltage, but
may still enable the special mode if the terminal sees this voltage prior
to seeing the power supply voltage that the terminal is compared against.
Accordingly, even where special test modes are enabled by an overvoltage
signal at a terminal, a hot socket condition may still inadvertently
enable the special mode.
It should also be noted that similar types of inadvertent enabling of
special test modes can occur during power up of the device, if the
transients in the system are such that a voltage is presented to the
terminal at which an overvoltage selects the test mode, prior to the time
that the power supply voltage reaches the device.
The inadvertent test mode entry is especially dangerous where a similar
type of operation is required to disable the test mode. For example, the
memory described in the McAdams et al. article requires an overvoltage
condition, together with a particular code, to return to normal operation
from the test mode. In the system context, however, there may be no way in
which an overvoltage can be applied to the device (other than the hot
socket or power up condition that inadvertently placed the device in test
mode). Accordingly, in such a system, if the memory device is in test
mode, there may be no way short of powering down the memory in which
normal operation of the memory may be regained.
It is therefore an object of this invention to provide an improved circuit
and method for exiting a special mode in an integrated circuit device.
It is a further object of this invention to provide such a circuit and
method for exiting a special mode which does not require the presentation
of signals outside of nominal operating ranges.
It is a further object of this invention to provide such a circuit and
method for exiting a special mode which does not require the user to be
aware of whether the device is in or out of a special mode.
It is a further object of this invention to provide such a circuit and
method in which the special mode is a special test mode.
It is a further object of this invention to provide such a circuit and
method in which the signal for exiting the special mode is an operation
inherent in the normal use and operation of the device.
Other objects and advantages of the invention will become apparent to those
of ordinary skill in the art having reference to this specification.
SUMMARY OF THE INVENTION
The invention may be incorporated into a memory device having a normal
operating mode and a special operating mode, such as a special test mode.
The device includes chip enable circuitry, and also test mode enable
circuitry which enables the entry into test mode only during such times as
the chip enable circuitry is not enabling the device. Upon enabling the
device from the chip enable terminals and circuitry, the special test mode
is exited. The circuit may also prevent entry into test mode in the event
of overvoltage excursions or other entry signals applied while the device
is enabled.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is an electrical diagram, in block form, of a memory device
incorporating the preferred embodiment of the invention.
FIG. 2 is an electrical diagram, in block form, of the test mode enable
circuitry of the memory of FIG. 1.
FIGS. 2a and 2b are electrical diagrams, in block form, of alternative
embodiments of the test mode enable circuitry of FIG. 1.
FIG. 3 is an electrical diagram, in schematic form, of the overvoltage
detector circuit in the test mode enable circuitry of FIG. 2.
FIG. 4 is an electrical diagram, in schematic form, of a first embodiment
of a power-on reset circuit, including a reset circuit therewithin, as
used in the test mode enable circuitry of FIG. 2.
FIGS. 4a and 4b are electrical diagrams, in schematic form, of alternate
embodiments of reset circuits for the power-on reset circuit of FIG. 4.
FIG. 5 is an electrical diagram, in schematic form, of the evaluation logic
in the test mode enable circuitry of FIG. 2.
FIGS. 5a, 5b and 5c are electrical diagrams, in schematic form, of
alternative embodiments of the evaluation logic in the test mode enable
circuitry of FIG. 2.
FIG. 6 is an electrical diagram, in schematic form, of the D flip-flops
used in the test mode enable circuitry of FIG. 2.
FIGS. 7, 8 and 9 are timing diagrams illustrating the operation of the test
mode enable circuitry of FIG. 2 in the memory of FIG. 1.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now to FIG. 1, a block diagram of an integrated circuit memory 1
incorporating the preferred embodiment of the invention described herein
will be discussed. Memory 1 is an integrated circuit memory, for example a
static random access memory (SRAM), having 2.sup.20, or 1,048,576, storage
locations or bits. Memory 1 in this example is a wide-word memory,
organized as 2.sup.17, or 128k, addressable locations of eight bits each.
Accordingly, for example in a read operation, upon the access of one of
the memory locations, eight data bits will appear at the eight
input/output terminals DQ0 through DQ7. Memory 1, in this example,
includes an array 10 which has 1024 rows of 1024 columns, with eight
columns accessed in each normal memory operation.
In this example of memory 1, memory array 10 is divided into eight
sub-arrays 12.sub.0 through 12.sub.7, each of which have 1024 rows and 128
columns. For purposes of reducing the power consumed during active
operation, in this embodiment only one of the sub-arrays 12 is energized
during each active cycle, with the selection of the sub-array 12 to be
energized determined by the desired memory address (i.e., three bits of
the column address). Accordingly, as will be further described
hereinbelow, during a normal memory operation such as a read, all eight
bits of the accessed memory location will be located in the same sub-array
12.
Memory 1 includes seventeen address terminals A0 through A16, for receiving
the seventeen address bits required to specify a unique memory address. In
the conventional manner, the signals from these seventeen address
terminals are buffered by address buffers 11. After such buffering,
signals corresponding to ten of the address terminals (A7 through A16) are
received by row decoder 14, for selecting the one of the 1024 rows in
array 10 to be energized by row decoder 14 via bus 15. Signals
corresponding to the remaining seven address terminals (A0 through A6) are
received by input/output circuitry and column decoder 16 to select one of
sub-arrays 12 by way of control lines 17, and to select the desired
columns therein according to the column address value. While single lines
are indicated for the communication of the address value from address
buffers 11 to row decoder 14 and input/output circuitry and column decoder
16, it should be noted that many conventional memories communicate both
true and complement values of each address bit to the respective decoders,
for ease of decoding.
As noted above, for purposes of reducing power consumption, memory 1
according to this embodiment energizes only one of sub-arrays 12, selected
according to the three most significant column address bits. In this
embodiment, repeaters (not shown) are present between sub-arrays 12 for
controlling the application of the energized word line within the
sub-array 12. In this way, the column address (particularly the three most
significant bits) controls the application of the word line so that only
that portion of the word line in the selected sub-array 12 is energized
through the memory operation cycle. Column decoder 16 also selects eight
of the 256 columns in the selected sub-array 12, according to the value of
the remaining bits of the column address. In this embodiment, also for
purposes of reducing active power consumption, only those sense amplifiers
(not shown) in the selected sub-array 12 which are associated with the
desired memory bits are energized. The sense amplifiers so selected by
column decoder 16 are then in communication with input/output circuitry
and column decoder 16 via local data lines 18, through which the reading
of data from or writing of data to the eight selected memory cells in
array 10 may be done in the conventional manner.
Of course, many alternative organizations of memory 1 may be used in
conjunction with the invention described herein. Examples of such
organizations would include by-one memories, where a single bit is input
to or output from in normal operation. In addition, wide-word memories
where each sub-array is associated with one of the input/output terminals,
and memories where the entire array is energized during normal operation,
may alternatively be used. As mentioned hereinabove, of course, other
memory types such as dynamic RAMs, EPROMs, and embedded memories, each
with organization of their own, may also benefit from this invention.
It should also be noted that the block diagrams of this embodiment of the
invention, illustrating the electrical placement of the circuits, may not
necessarily correspond to the physical layout and placement of the
circuitry on an actual memory 1. It is contemplated that the physical
layout and placement of sub-arrays 12 on the memory chip may not
correspond to that shown in FIG. 1; for example, the eight sub-arrays 12
may be placed in such a manner that input/output circuitry and column
decoder 16 is physically located between groups of sub-arrays 12, and
similarly row decoder 14 may be physically located between groups of
sub-arrays 12. It is contemplated that such layout optimization can be
determined by one of ordinary skill in the art according to the particular
parameters of interest for the specific memory design and manufacturing
processes.
Circuitry for controlling the communication of data between input/output
circuitry and column decoder 16 of memory 1 is also schematically
illustrated in FIG. 1. It is of course contemplated that other control
circuitry for controlling the operation of memory 1 as is conventional
will also be incorporated into memory 1; such circuitry is not shown in
FIG. 1 for purposes of clarity. Output data bus 20, which is eight bits
wide in this example, is driven by input/output circuitry and column
decoder 16, in a read operation, with the data states of the memory
location accessed according to the memory address. Each line of output
data bus 20 is received by non-inverting output buffer 22, which drives
the output terminal DQ with the correct data state, at levels and currents
corresponding to the specifications of memory 1. Each of output buffers 22
are enabled by a signal on line 24 from AND gate 26. The signal on line 24
thus controls whether the logic level on output data bus 20 is presented
at terminals DQ, or if output buffers 22 present a high-impedance state to
terminals DQ.
AND gate 26, in this embodiment, has four inputs. A first input of AND gate
26 receives a chip enable signal via AND gate 25 and OR gate 33. AND gate
25 receives signals from terminal E1 at an inverting input and from
terminal E2 at a non-inverting input, such that the output of AND gate 25,
on line CE, is at a high logic level responsive to terminal E1 being low
and terminal E2 being high. The output of AND gate 25, on line CE, is
connected to a first input of OR gate 33, which receives a signal on line
T from test mode enable circuitry 29, as will be described hereinbelow.
During normal operation, line T will be at a low logic level, so that OR
gate 33 will respond directly to the state of line CE from AND gate 25.
Accordingly, in this embodiment, the output of OR gate 33 corresponds to a
chip enable signal, and enables the operation of memory 1 and the
operation of output buffers 22. Of course, as is well known in the art,
the chip enable signal may be generated from alternative logical
combinations of multiple enable signals, or from a single chip enable
terminal, as is conventional for some circuits in the art.
As shown in FIG. 1, in the example of memory 1 according to this embodiment
of the invention, line CE is connected to one input of OR gate 19, the
output of which is connected to input/output circuit and column decoder 16
for controlling the enabling and disabling thereof. Other functional
blocks are also generally controlled by chip enable terminals E1 and E2
via OR gate 19, in a similar manner; the connections for performing such
control are not shown in FIG. 1 for clarity. The other input of OR gate 19
receives the output of AND gate 21, which receives line T from test mode
enable circuitry 29 at one input, and receives terminal OE at its other
input. As will be described in further detail hereinbelow, this
construction allows the output enable terminal OE to provide a chip enable
function when memory 1 is in test mode.
A second input received by AND gate 26 is the write enable signal received
at terminal W.sub.--. Accordingly, when AND gate 25 indicates selection of
memory 1 in combination with write enable terminal W.sub.-- at a high
logic level, indicating a read operation, AND gate 26 can enable output
buffers 22. Conversely, during a write operation indicated by write enable
terminal W.sub.-- at a low logic level, AND gate 26 will necessarily have
a low logic level and will therefore necessarily place output buffers 22
in the high impedance state at their output. A third input received by AND
gate 26 is an output enable signal from terminal OE, as is conventional in
the art for enabling and disabling the output terminals; the use of an
output enable signal is useful especially when multiple memories 1 have
their output terminals connected together in wired-OR fashion.
The fourth input received by AND gate 26 in this embodiment is generated by
parallel test circuitry 28, which performs a comparison of multiple data
words when memory 1 is placed into a special test mode. Parallel test
circuitry 28 receives, on lines 30, multiple eight bit data words from
input/output circuitry and column decoder 16; each of these data words
corresponds to the data read from one of sub-arrays 12 according to a
portion of the column address. Parallel test circuitry 28 performs the
comparison of these multiple data words, and generates a signal on line 32
corresponding to whether or not the comparison was successful.
When the special test mode for parallel test is enabled by a high logic
level on line T connected thereto, parallel test circuitry 28 performs the
comparison of the multiple data words presented thereto on lines 30, and
generates a signal on line 32 corresponding to whether or not the
comparison was successful. In this embodiment, line 32 is driven to a high
logic level by parallel test circuitry 28 in test mode when the multiple
data words all present the same data, and to a low logic level in test
mode when there is an error, i.e., when the multiple data words compared
do not present the same data. In order that output buffers 22 are operable
during normal operation, parallel test circuitry 28 will present a high
logic level during normal operation, i.e., when parallel test circuitry 28
is not enabled.
Also as will be described in further detail hereinbelow, during a special
test mode, line T will be driven to a high logic level by test mode enable
circuitry 29. This will cause the output of OR gate 33 to go to a high
level, allowing enabling of output buffers 22 in the absence of the chip
enable condition of terminal E1 low and terminal E2 high; as will be noted
hereinbelow, in this embodiment of memory 1, the chip enable condition
will cause disabling of the special test mode. Accordingly, with a special
test mode enabled, output enable terminal OE will, in effect, provide the
chip enable function for memory 1.
It should be apparent from FIG. 1 that memory 1 is a common input/output
memory, and as such terminals DQ both present output data and receive
input data. Terminals DQ are thus connected to input buffers 34, which
during write operations present the input data to input data control
circuitry 36, which will communicate the input data, via input data bus
38, to the selected memory cells via input/output control circuitry and
column decoder 16. Input buffers 34 are controlled in a similar manner as
output buffers 22 discussed hereinabove, with the enabling signal on line
40 generated by AND gate 42, which performs the logical AND of the chip
enable signal from terminal CE and the write enable signal from terminal
W.sub.-- (inverted by inverter 44). In parallel test mode, input data may
be written to multiple memory locations in memory 10 by input/output
circuitry and column decoder 16 in the conventional manner, by enabling
multiple memory locations and simultaneously writing the same data
thereto.
Test mode enable circuit 29 is provided in memory 1 for enabling one of
several special test modes. By way of explanation, the special test mode
corresponding to parallel read and write operations is shown by way of
parallel test circuitry 28 in FIG. 1. Other special test modes, such as
described in the McAdams et al. article cited hereinabove, may also be
enabled by test mode enable circuit 29, responsive to the inputs connected
thereto.
Test mode enable circuit 29 receives signals from address terminals A1 and
A3, and receives a signal from AND gate 25, via inverter 27, on line TRST.
As will be described in further detail hereinbelow, responsive to a
sequence of overvoltage conditions at terminal A3 with terminal A1 in a
particular logic state, and so long as AND gate 25 indicates that memory 1
is not enabled, test mode enable circuitry 29 will generate a high logic
level on line T, indicating to parallel test circuitry 28 in this
embodiment, and to such other circuits in memory 1 as may be enabled by
particular test modes, that the special test mode of operation is to be
entered.
Test Mode Enable Circuitry
Referring now to FIG. 2, the construction of test mode enable circuitry 29
will now be described in detail. According to this embodiment of the
invention, two distinct and mutually exclusive special test modes can be
enabled, depending upon the logic state at terminal A1 at the time of the
overvoltage condition at terminal A3. It should be noted that, while test
mode enable circuitry 29 receives the logic state at terminal A3 prior to
address buffers 11, alternatively the buffered value from terminal A3
could be communicated to test mode enable circuitry 29.
Test mode enable circuitry 29, as noted above, receives signals on lines
A1, A3, and TRST as inputs. Test mode enable circuitry 29 presents signals
on line T to parallel test circuitry 28, as noted above, to indicate
whether or not the parallel test mode is enabled. Additionally, test mode
enable circuitry 29 has another output on line T2, for enabling a second
special test in memory 1, if desired. Line T2 is connected to such other
circuitry in memory 1 as is necessary for performing such an additional
test; such other special test, in this embodiment, is mutually exclusive
with the parallel test function indicated by the signal on line T. While
only two mutually exclusive special test modes are shown on FIG. 2, it is
of course contemplated that many more special test functions may be
enabled by simple extension of the logic included in test mode enable
circuitry 29, including the use of additional ones of inputs such as
address inputs for the selection of such additional special test modes. It
is contemplated that such extension will be apparent to one of ordinary
skill in the art having reference to this specification,. Furthermore, it
should be noted that the special test modes enabled by test mode enable
circuitry 29 need not be mutually exclusive of one another, as certain
functions may work cooperatively with one another (e.g., a particular
special read function may be enabled together with the parallel test mode,
with the parallel test without the special read function separately
selectable).
Test mode enable circuitry 29 includes evaluation logic 30, which receives
a signal from address terminal A1 on the line marked A1 in FIG. 2.
Evaluation logic 30 also receives, as an input, line TRST from the chip
enable circuitry (i.e., AND gate 25 via inverter 27) so that, as will be
described in further detail hereinbelow, the special test modes will be
disabled, and normal operating modes entered, upon the selection of memory
1 by the chip enable inputs E1 and E2. Also according to this embodiment
of the invention, evaluation logic 30 receives an input on line CKBHV,
which is generated by overvoltage detector 32. Overvoltage detector 32
receives line A3 from the corresponding address terminal, for determining
whether the voltage applied thereat is in an overvoltage condition.
Further included in test mode enable circuitry 29 is power-on reset circuit
40, which provides an enable signal on line POR to evaluation logic 30 (as
well as to other circuitry in memory 1) at a point in time after power
supply V.sub.cc is powered up. As will be described in further detail
hereinbelow, power-on reset circuit 40, via evaluation logic 30, will lock
out entry into test mode during power-up of memory 1.
Test mode enable circuitry 29 also includes D-type flip-flops 90 and 92
connected in series with one another, and having their clock and reset
inputs controlled by evaluation logic. As mentioned above, two special
test modes are selectable in this embodiment of the invention; test mode
enable circuitry 29 thus includes two pair of flip-flops 90 and 92, each
pair for enabling the selection of a particular special test mode via
drivers 110. As will be described in more detail below, the provision of a
series of multiple flip-flops 90, 92 for each of the special test modes in
test mode enable circuitry 29 is so that a sequence of signals (e.g., a
series of overvoltage excursions on address terminal A3) must be presented
in order for a special test mode to be enabled, rather than only requiring
a single such signal or overvoltage excursion. The requirement of a
sequence of two or more such signals for enabling a special test mode
provides a high degree of security that such a mode will not be
inadvertently entered, due to noise, power loss and restoration, hot
socket insertion, or other such events.
Overvoltage Detection
Referring now to FIG. 3, the construction and operation of overvoltage
detector 32 will now be described in detail. As will be apparent from this
description, the overvoltage condition detected by overvoltage detector
32, responsive to which line CKBHV will go to a high logic level to
indicate the overvoltage condition, is the condition where the voltage
applied to terminal A3 is a certain value below ground, or V.sub.ss. It
should be noted that a positive overvoltage condition (i.e., the voltage
at terminal A3 exceeding a certain value greater than the positive power
supply to memory 1, or V.sub.cc) can alternatively be detected by
overvoltage detector 32, with the appropriate design modifications made
thereto.
Line A3 from the corresponding address terminal is connected to the drain
of p-channel transistor 34.sub.0. According to this embodiment, p-channel
transistors 34.sub.0 through 34.sub.4 are p-channel transistors connected
in diode configuration (i.e., with their gates connected to their drains),
and connected in series with one another to establish a diode chain. While
five transistors 34 are used in this embodiment of overvoltage detector
32, it should be noted that the number of transistors 34 so used depends
upon the trip voltage at which overvoltage detector 32 is to issue the
overvoltage signal. The number of transistors 34 used, and their threshold
voltages, will of course determine this value.
At node N1, the source of transistor 34.sub.4, the top one of transistors
34 in the diode chain, is connected to the drain of a p-channel pull-up
transistor 36. Transistor 36 has its source connected to V.sub.cc, and its
gate connected to V.sub.ss. Transistor 36 is a relatively small transistor
relative to transistors 34, in terms of its width-to-length ratio (W/L).
For example, the W/L of transistor 36 in this embodiment is on the order
of 1/250, while the W/L of transistors 34 is on the order of 2.
Accordingly, when transistors 36 are in a conductive state, they will be
capable of pulling down node N1 even though transistor 36 remains
conductive.
In this embodiment, also connected to node N1 is the drain of p-channel
transistor 38, which has its source connected to V.sub.cc and its gate
controlled by a signal on line RST.sub.-- from evaluation logic 30 (see
FIG. 2). Transistor 38 is a relatively large transistor, relative to
transistors 34 and 36, having a W/L on the order of 8, so that when it is
conductive, node N1 can be pulled to V.sub.cc through it, even with
transistors 34 in a conductive state. Transistor 38 is thus capable of
resetting the state of overvoltage detector 32 responsive to a low logic
level on line RST.sub.--, even with the voltage on line A3 in the
overvoltage condition).
Node N1 is connected to the input of a conventional inverting Schmitt
trigger circuit 40. As is conventional for such circuits, Schmitt trigger
40 performs the logical inversion with hysteresis in its transfer
characteristic. Such hysteresis, provided by n-channel transistor 42.sub.n
and p-channel transistor 42.sub.p, provides stability to overvoltage
detector 32, so that small variations in the voltage of line A3 around the
trip voltage will not cause the output of overvoltage detector 32 to
oscillate between high and low logic levels.
The output of Schmitt trigger 40 is connected, via inverting buffer 44, to
the input of a latch consisting of cross-coupled inverters 46 and 48. The
input of inverter 46 receives the output of inverter 44, and the output of
inverter 46 drives line CKBHV, which is the output of overvoltage detector
32. Inverter 48 has its input connected to the output of inverter 46, and
has its output connected to the input of inverter 46. In this embodiment,
inverters 46 and 48 are both conventional CMOS inverters, with the W/L of
the transistors in inverter 48 preferably much smaller (e.g., W/L on the
order of 0.5) than those of inverter 46 (W/L on the order of 2.0). Such
construction allows the state of line CKBHV to remain latched, but also
allows inverter 44 (its transistors having W/Ls on the order of 1.0) to
overwrite the state of the latch with relative ease. The presence of the
latch of inverters 46 and 48 also lends additional stability to
overvoltage detector 32, so that oscillations at the output on line CKBHV
are less likely to be generated from small variations of the voltage of
line A3 about the trip voltage.
In operation, the normal condition of overvoltage detector 32 (i.e., the
voltage at terminal A3 in its nominal range) has node N1 pulled up, by
transistor 36, to V.sub.cc. This causes Schmitt trigger 40 to have a low
logic level at its output which, by operation of inverters 44 and 46,
presents a low logic level on line CKBHV. Inverter 48, together with
inverter 46, latches this low logic level on line CKBHV. This condition
indicates to the remainder of memory 1, via test mode enable circuitry 29
as will be described later, that the normal operational mode is selected.
Enabling of a special test mode is performed by presenting a voltage at
terminal A3 which is sufficiently below the voltage of V.sub.cc to cause
node N1 to be pulled low. The trip voltage level to which terminal A3 must
be pulled is calculated by determining the voltage at which the diodes of
transistors 34 will all be forward biased. With node N1 pulled to V.sub.cc
by transistor 36, transistors 34 (in this case numbering five) will all be
conductive when the voltage at terminal A3 is at or below voltage
V.sub.trip :
V.sub.trip =V.sub.cc -5(V.sub.tp)
where V.sub.tp is the threshold voltage of p-channel transistors 34. For
example, with a V.sub.tp on the order of 2.4 volts, V.sub.trip will have a
value on the order of -7.0 volts, for a nominal V.sub.cc value of 5.0
volts.
With the voltage at terminal A3 at or below V.sub.trip, node N1 is pulled
low, toward the voltage of terminal A3. This causes Schmitt trigger 40 to
present a high logic level at its output, which is in turn inverted by
inverter 44. As noted above, inverter 44 is sufficiently large, relative
to inverter 48, to cause inverter 46 to change state, presenting a high
logic level on line CKBHV, indicating to the remainder of test mode enable
circuitry 29 that terminal A3 is in the overvoltage condition.
Overvoltage detector 32 is reset to the normal operating condition in one
of two ways. First, upon the return of terminal A3 to a voltage above
V.sub.trip, transistors 34 will become non-conductive, allowing transistor
36 to pull node N1 up toward V.sub.cc. Upon node N1 reaching a voltage at
which Schmitt trigger 40 switches, a low logic level will again be
presented on line CKBHV. As will be noted hereinbelow, the operation of
memory 1 according to the preferred embodiments of the invention requires
that the overvoltage condition be presented at least twice in succession
in order for the special test modes to be entered; accordingly, this is
the usual way in which overvoltage detector 32 will be reset.
A second way in which overvoltage detector 32 is reset is by operation of
transistor 38, responsive to a low logic level on line RST.sub.--. As will
be discussed hereinbelow, line RST.sub.-- will be driven to a low logic
level responsive to the unconditional exit from test mode into normal
operating mode, triggered by various events. As noted above, transistor 38
is preferably large enought that it can pull node N1 high even with
transistors 34 conducting, and accordingly cause Schmitt trigger 40 and
inverters 44, 46, and 48 to make the transition required to present a low
logic level on line CKBHV again. As noted in FIG. 2, line CKBHV is
received by evaluation logic 30.
Power-on Reset
According to this embodiment of the invention, evaluation logic 30 also
receives, at an input thereof, a signal on line POR from power-on reset
circuit 40. The function of power-on reset circuit 40 is to prevent
inadvertent entry into a special test mode upon power-up of memory 1.
Accordingly, during such time as memory 1 is powering up, power-up reset
circuit 40 will indicate the same to evaluation logic 30 via line POR and
disable any entry into a special test mode. Once memory 1 is sufficiently
powered up, power-up reset circuit 40 will indicate the same to evaluation
logic 30 via line POR, and allow the overvoltage condition at terminal A3,
and such additional or alternative indications of a desired entry into a
special test mode, to enable a tes | | |
