Dynamic RAM with on-chip ECC and optimized bit and word redundancy

Claims

What is claimed is:

1. A memory, comprising: a first array of memory cells having a first plurality of word lines, a first plurality of bit lines, and a first plurality of redundant bit lines; a first plurality of data lines; switching means for coupling selected ones of said plurality of redundant bit lines of said first array and selected ones of said plurality of bit lines of said first array to said first plurality of data lines; a separate array of redundant memory cells comprising a second plurality of word lines and a second plurality of bit lines; address means coupled to said first plurality of word lines of said first array of memory cells and to said second plurality of word lines of said separate array of redundant memory cells for accessing an X-bit error correction word comprising data bits and check bits from one of said first array of memory cells and said separate array of redundant memory cells; error correction circuitry coupled to said first plurality of data lines and to said plurality of bit lines of said separate array of redundant memory cells, for reading said accessed X-bit error correction word from one of said first plurality of data lines and said separate array of redundant memory cells and correcting any faulty data bits therein; and output means coupled to said error correction circuitry for providing said data bits as said accessed X-bit error correction word as corrected by said error correction circuitry for external read-out.

2. The memory as recited in claim 1, further comprising a second plurality of data lines having X+N data lines, wherein a first group X of said second plurality of data lines are selectively coupled to said plurality of bit lines of said first array, and wherein a second group N of said second plurality of data lines are selectively coupled to said plurality of redundant bit lines of said first array.

3. The memory as recited in claim 2, wherein said first group X of said second plurality of data lines are coupled to said first plurality of data lines by said switching means, and wherein said switching means couples one of said second group N of said second plurality of data lines to one of said first plurality of data lines if one of said first group X of said second plurality of data lines is coupled to a faulty one of said plurality of bit lines of said first array of memory cells.

4. The memory as recited in claim 3, further comprising a second switching means for coupling bit lines of said separate array of redundant memory cells to said error correction means when a word line of said first array addressed by said addressing means is faulty.

5. The memory as recited in claim 2, wherein said second plurality of data lines are disposed above said plurality of bit lines of said first array of memory cells in a zig-zag pattern relative to said plurality of bit lines of said first array of memory cells to minimize capacitive coupling thereto.

6. The memory as recited in claim 1, wherein said error correction circuitry comprises a plurality of syndrome generators, and a syndrome bus coupled to said plurality of syndrome generators for receiving respective syndrome bits therefrom.

7. The memory as recited in claim 6, wherein said error correction circuitry is comprised of differential cascode voltage switch XOR logic gates.

8. The memory as recited in claim 6, wherein during a writeback cycle respective parity bits are generated by said plurality of syndrome generators and stored as check bits of said error correction word.

9. The memory as recited in claim 8, wherein said plurality of syndrome generators compare said stored check bits of said error correction word with respective check bits generated by said plurality of syndrome generators for said data bits of said error correction word during a fetch cycle, to generate respective syndrome bits.

10. The memory as recited in claim 9, further comprising means coupled to said plurality of syndrome generators for determining which of said data bits of said error correction word are in error, and means for inverting one of said data bits.

11. The memory as recited in claim 10, wherein said determining means is comprised of a plurality of differential cascode voltage switch XOR gates.

12. The memory as recited in claim 1, wherein said memory is formed on a rectangular portion of a semiconductor chip, said rectangular portion having two long sides, and wherein said error correction circuitry is disposed on an area of said semiconductor chip that extends between said two long sides of said rectangular portion of said semiconductor chip, said area of said semiconductor chip having no other circuitry associated therewith.

13. The memory as recited in claim 1, wherein said output means comprises a buffer that stores both of said data bits and said check bits of said error correction word.

14. The memory as recited in claim 13, wherein said output means further comprises means for addressing at least one of said data bits stored in said buffer, and at least one I/O means for receiving said at least one of said data bits for data transmission.

15. An architecture for at least part of an integrated circuit chip, comprising:

an array of memory cells disposed on a first portion of the integrated circuit chip, comprising a plurality of word lines, a plurality of bit lines, a first plurality of memory cells, each of said first plurality of memory cells being coupled to one of said plurality of word lines and to one of said plurality of bit lines, a plurality of redundant bit lines, and a second plurality of memory cells, each of said second plurality of memory cells being coupled to one of said plurality of word lines and one of said plurality of redundant bit lines;

a first plurality of data lines;

switching means for coupling selected ones of said plurality of redundant bit lines and said plurality of bit lines to said first plurality of data lines;

an independent word line redundancy array disposed on a second portion of the integrated circuit chip spaced from said first portion, said independent word line redundancy array having a plurality of word lines and a plurality of bit lines;

an error detection and correction means coupled to said first plurality of data lines and to said plurality of bit lines of said independent word line redundancy array for reading and correcting an error correction word comprising a plurality of data bits and a plurality of check bits; and

a buffer coupled to said error detection and correction means for temporarily storing said error correction word.

16. The integrated circuit chip architecture of claim 15, wherein said independent redundant word line array is comprised of twin cell redundant word lines.

17. The integrated circuit chip architecture of claim 15, wherein said plurality of arrays of memory cells, said switching means, said independent word line redundancy array, said error detection and correction means, and said buffer are disposed in a pipelined fashion on said integrated circuit chip.

18. The integrated circuit chip architecture as recited in claim 15, wherein said error detection and correction means generates said check bits in accordance with a double error detect, single error correct error correction code.

19. The integrated circuit chip architecture as recited in claim 18, wherein said error detection and correction comprises a plurality of DCVS XOR logic gates.

20. The integrated circuit chip architecture as recited in claim 15, wherein said buffer further comprises output means for selecting at least some of said plurality of data bits stored by said buffer.

21. The integrated circuit chip architecture as recited in claim 20, further comprising decoding means for decoding mode address signals to set an operating mode of the integrated circuit chip.

22. The integrated circuit chip architecture as recited in claim 21, wherein said output means selects said data bits in a manner established by said decoding means.

23. The integrated circuit chip architecture as recited in claim 22, wherein said buffer sends one of said data bits to an I/O pad during a given access cycle.

24. The integrated circuit chip architecture as recited in claim 22, wherein said buffer sends two of said data bits to two I/O pads, respectively, during a given access cycle.

25. The integrated circuit chip architecture as recited in claim 22, wherein said buffer sends two of said data bits in a sequential fashion to an I/O pad during a given access cycle.

26. In a manufacturing process for forming wafers having a plurality of memory chips thereon, each of the memory chips comprising both a number X of memory cells and a number Y of redundant cells, wherein wafers successively formed by the manufacturing process have an average number N of faulty memory cells, and support circuitry for writing data into and reading data out of the memory chip, the improvement comprising the steps of:

forming an error correction code circuit block in the support circuitry of each memory chip when said average number N of faulty memory cells in wafers successively formed by said manufacturing process is greater than said number Y of redundant cells, and

when said average number N of faulty memory cells in wafers successively formed by said manufacturing process is equal to or less than the number Y of redundant cells, forming the wafers without forming said error correction code circuit block in the support circuitry of each memory chip.

27. A memory chip, comprising:

an array of memory cells interconnected by a plurality of word lines, a first plurality of bit lines, and a plurality of redundant bit lines,

means coupled to said plurality of word lines, said plurality of bit lines, and said plurality of redundant bit lines for simultaneously addressing a first predetermined number X of said first plurality of bit lines so as to access an X-bit error correction word, while also simultaneously addressing a second predetermined number N of said plurality of redundant bit lines,

a first set of X+N data lines coupled to at least said first predetermined number X of said first plurality of bit lines and to said second predetermined number N of said plurality of redundant bit lines,

a second set of X data lines, and

first switching means for selectively coupling said first set of X+N data lines to said second set of X data lines, so that signals originating from one or more of said second predetermined number N of said plurality of redundant bit lines are sent to said second set of X data lines in place of signals originating from any one or more of said first predetermined number X of said first plurality of bit lines that are faulty.

28. The memory chip as recited in claim 27, further comprising:

a plurality of redundant word lines having a second plurality of bit lines associated therewith,

second switching means having a set of inputs coupled to both of said second set of X+N data lines and to said second plurality of bit lines and a set of outputs for transmitting an accessed X-bit error correction word from one of said second set of X+N data lines and said second plurality of bit lines to said set of outputs, and

a third plurality of data lines coupled to said set of outputs of said second switching means.

29. The memory chip as recited in claim 28, wherein said plurality of redundant word lines are disposed in a portion of the memory chip spaced from said plurality of word lines.

30. The memory chip as recited in claim 28, further comprising:

means coupled to said third plurality of data lines for providing a Hamming code error checking and correcting function, and a buffer coupled to said means for providing a Hamming code error checking and correcting function for storing both data bits and check bits generated therefrom.

31. The memory chip as recited in claim 28, wherein said first set of X+N data lines, said first switching means, said second set of X data lines, said second switching means, and said third plurality of data lines are arranged in a pipelined fashion on the memory chip.

32. The memory chip as recited in claim 31, wherein said means for providing a Hamming code error checking and correcting function and said buffer are arranged in a pipelined fashion on the memory chip.

33. The memory chip as recited in claim 31, wherein said first set of X+N data lines are disposed in a zig-zag pattern over said first plurality of bit lines so as to minimize capacitive coupling between said first set of X+N data lines and said first plurality of bit lines.

34. A memory chip, comprising:

a first array of memory cells disposed on a first portion of said memory chip, said memory cells being interconnected by a plurality of bit lines and a plurality of word lines, said array including a plurality of sense amplifiers coupled to said plurality of bit lines to sense a differential signal of a first magnitude therefrom to read said memory cells,

a second array of redundant cells disposed on a second portion of said memory chip spaced from said first portion thereof, said redundant cells being interconnected by a plurality of bit lines and a plurality of word lines, said second array including a plurality of sense amplifiers coupled to said plurality of bit lines to sense a differential signal of a second magnitude greater than said first magnitude therefrom to read said redundant cells, and

first means formed on said memory chip coupled to said first array for reading a multi-bit error correction word from at least one of said plurality of word lines of said first array, said first means being coupled to said second array for reading a multi-bit error correction word from at least one of said plurality of word lines of said second array when said at least one of said word lines of said first array is faulty, said first means detecting and correcting at least one erroneous bit in said multi-bit word.

35. The memory chip as recited in claim 34, wherein said word lines of said second array of redundant cells are coupled to each of said bit lines.

36. The memory chip as recited in claim 35, wherein said second array of redundant cells comprise a twin cell array.

BACKGROUND OF THE INVENTION

1. Technical Field

The invention relates generally to the field of dynamic random access memory (DRAM) design, and more particularly to a DRAM architecture that optimizes the combination of on-chip error correction code (ECC) circuitry, bit line redundancy, and word line redundancy, so as to optimize the ability of the DRAM to correct different types of errors.

2. Background Art

From the very early stages of DRAM development in the 1970's, designers have recognized the need for some sort of on-chip error recovery circuitry. That is, given the large number of processing steps needed to make a memory chip, and given the large number of discrete transistor-capacitor memory cells to be fabricated, from a practical standpoint it is inevitable that at least some memory cells will not function properly.

One of the first on-chip error recovery techniques utilized in the industry was the general idea of redundancy. In redundancy, one or more spare lines of cells are added to the chip. These can be either spare word lines (i.e. lines of cells having their FET gate electrodes interconnected) or spare bit lines (i.e. lines of cells having their FET drain electrodes interconnected on a common line coupled to a sense amplifier that senses the state of the selected memory cell). Typically, a standard NOR address decoder is provided for each redundant line. After the memory chip is manufactured, it is tested to determine the addresses of faulty memory cells. These addresses are programmed into the address decoder for the redundant lines, by controllably blowing fuses, setting the state of a RAM or EEPROM, etc. When the address sent to the memory chip is for the line on which the faulty cell resides, the address decoder for the redundant line activates the redundant line instead In this manner, if discrete cells in the memory chip are inoperative, redundant cells can be substituted for them. Among the earliest patents directed to redundancy are U.S. Pat. No. 3,753,244, entitled "Yield Enhancement Redundancy Technique," issued Aug. 28, 1973 to Sumilas et al and assigned to IBM (word line redundancy), and U.S. Pat. No. 3,755,791, entitled "Memory System With Temporary or Permanent Substitution of Cells For Defective Cells," issued Aug. 28, 1973 to Arzubi and assigned to IBM (bit line redundancy).

One of the drawbacks associated with redundancy is that it can only rectify a relatively small amount of faulty random cells. That is, as the number of faulty cells increases, the number of redundant lines needed to correct these cells increases, to the point where you have a large amount of spare memory capacity that ordinarily is not used (and may itself incorporate faulty cells, such that you need even more redundant lines to correct errors in the remaining redundant lines). Therefore, typically a relatively small amount of redundant lines are provided on-chip, such that if an entire subarray or array of cells is faulty, redundancy can no longer be used for correction.

This problem is addressed by the use of partially-good chips. Two or more chips having large amounts of faulty cells are mounted and stacked together in a multi-chip package. In one technique, the chips are selected such that they complement one another in terms of which arrays are good and which arrays are faulty. For example, if a given array on a first memory chip is bad, a second chip is selected wherein that same array is good. Thus, the two partially-good chips operate as one all-good chip. See U.S. Pat. No. 3,714,637, entitled "Monolithic Memory Utilizing Defective Storage Cells"; U.S. Pat. No. 3,735,368, entitled "Full Capacity Monolithic Memory Utilizing Defective Storage Cells"; and U.S. Pat. No. 3,781,826, "Monolithic memory utilizing Defective Storage Cells", all issued to W. Beausoleil and assigned to IBM.

Over time, some workers in the art have come to understand that the error recovery techniques discussed may not efficiently rectify all of the possible errors that may occur during DRAM operation. Specifically, a memory cell that initially operates properly may operate improperly once it is in use in the field. This may be either a so-called "soft error" (e.g. a loss of stored charge due to an alpha particle radiated by the materials within which the memory chip is packaged) or a "hard error" (a cycle-induced failure in the metallization or other material in the chip that occurs after prolonged use in the field). Because both of these types of errors occur after initial testing, they cannot be corrected by redundancy or by the use of partially-good chips. In general, this problem has been addressed by the use of error correction codes (ECC) such as Hamming codes or horizontal-vertical (HV) parity. These techniques are typically used in larger computer systems wherein data is read out in the form of multi-bit words.

The Hamming ECC double error detect, single error correct (DED/SEC) system of the prior art will now be briefly described. The data is stored as an ECC word having both data bits and check bits. The check bits indicate the correct logic states of the associated data bits. The ECC logic tests the data bits using the check bits, to generate syndrome bits indicating which bits in the ECC word are faulty. Using the syndrome bits, the ECC logic then corrects the faulty bit, and the ECC word as corrected is sent on to the processor for further handling.

As previously stated, in the prior art ECC circuitry was typically used in large systems and embodied in separate functional cards, etc. While this type of system-level ECC is now being used in smaller systems, it still adds a degree of both logic complexity and expense (due to added circuit cost and decreased data access speed) that makes it infeasible for less complicated systems. In these applications, memory performance/reliability suffers because there is no system-level ECC to correct for errors that occur after initial test.

The solution to this problem is to incorporate ECC circuitry on the memory chip itself. This reduces the expense associated with ECC, while at the same time increasing the effective memory performance. U.S. Pat. No. 4,335,459, entitled "Single Chip Random Access Memory With Increased Yield and Reliability," issued 6/15/82 to Miller, relates to the general idea of incorporating Hamming code ECC on a memory chip. The stored data is read out in ECC words consisting of 12 bits (8 data bits, 4 check bits) that are processed by the ECC circuitry. The corrected 8 data bits are sent to an 8-bit register. The register receives address signals that select one of the 8 bits for output through a single bit I/O. U.S. Pat. No. 4,817,052, entitled "Semiconductor memory With An Improved Dummy Cell Arrangement And With A Built-In Error Correcting Code Circuit," issued 3/28/89 to Shinoda et al and assigned to Hitachi, discloses a particular dummy cell configuration as well as the general idea of interdigitating the word lines so that adjacent failing cells on a word line will appear as singlebit fails (and thus be correctable) by the ECC system, because