In a multiprocessor computer system, a number of processors are coupled to main memory by a shared memory bus, and one or more of the processors have a two level direct mapped cache memory. When any one processor updates data in a shared portion of the address space, a cache check request signal is transmitted on the shared data bus, which enables all the cache memories to update their contents if necessary. Since both caches are direct mapped, each line of data stored in the first cache is also stored in one of the blocks in the second cache. Each cache has control logic for determining when a specified address location is stored in one of its lines or blocks. To avoid spurious accesses to the first level cache when a cache check is performed, the second cache has a special table which stores a pointer for each line in said first cache array. This pointer denotes the block in the second cache which stores the same data as is stored in the corresponding line of the first cache. When the control logic of the second cache indicates that the specified address for a cache check is located in the second cache, a lookup circuit compares the pointer in the special table which corresponds to the specified address with a subset of the bits of the specified address. If the two match, then the specified address is located in the first cache, and the first cache is updated.
A cache memory system reduces the rate of cache misses. The cache memory system includes a first auxiliary storage device which stores first information blocks and a second auxiliary storage device which stores second information blocks fetched from a lower level memory device. Each second block includes a plurality of the first information blocks. A process for fetching information selectively fetches a first or second information block from the lower level memory device and selectively stores the fetched block in the first auxiliary storage device and/or the second auxiliary storage device. Selection of the size of block to fetch and where to store the fetched block is according to whether the data to be referenced by the central controller is in the first auxiliary storage device or the second auxiliary storage device and whether first information blocks that do not include the referenced data are both in the second information block including the referenced data and in the first auxiliary storage device. A control unit that controls the selective fetching and storing maintains state data that includes entries corresponding to second information blocks. Each entry identifies a corresponding second information block and indicates the number of first information blocks that are in the first auxiliary storage device and from the corresponding second information block.
A memory system for reducing cache snooping overhead for a multilevel cache system has a highest cache level connected to a main memory and a lowest cache level connected to a processor or other memory accessing device. Each intermediate level cache is connected to a cache level one level above and below that cache. The highest cache level detects a memory access on a shared memory bus, and determines if that memory access resides in that cache. If there is a hit in that cache, the highest cache level checks a hit flag for every storage location within that highest level cache to determine if the memory access also hits a storage location within the next lower cache level. If there is a hit in the next lower cache level, that cache also checks a hit flag for every storage location within that cache to determine if the memory access also hits a storage location within the next lower cache level. This process continues until the memory access does not hit a particular cache level or until the lowest cache level is reached.
Storage is managed in a shared electronic store (SES) by assigning storage classes (STCs) to each directory entry having a data item stored in SES. The assignments of directory entries and data elements to the respective STCs can be changed at any time by any CPC. Eventually, no free space remains in the SES cache, and then space for new directory entries and data items must be obtained by reclaiming space occupied by directory entries and associated unchanged data items. The reclaiming of SES space is controlled on a STC basis. Any specified STC may reclaim from itself or from another STC using reclaiming software/microcode in SES, which includes a reclaim vector, a reclaim counter, a queue, and reclaiming controls. The vector and counter have respective elements for all possible STCs to controls how a specified STC may reclaim space from any or all target STC. Any enabled target STC reclaims its space according to an LRU algorithm maintained by a queue for the STC. A CPC can issue a command to load different values in target STC elements in the SES vector for a specified STC to control how reclaiming is apportioned for the specified STC. In SES, associated target counter elements are loaded from its vector. Reclaiming is done automatically in SES upon each directory miss in the current target STC having a non-zero counter value, when no free space exists. The counter is decremented for each reclaimed directory entry until its count reaches zero, and then the counter element for the next non-zero target STC is used for reclaiming until it reaches zero. When all STC elements in the counter are zero for the specified STC, the counter elements are reloaded from the vector elements to repeat the reclaiming operation, as long as a repeat factor for the specified STC has not reached zero. The repeat factor is decremented each time the counters are loaded from the vector. When the counters and repeat factor have all reached zero, reclaiming is disabled for the specified STC.
A computer system which utilizes processor boards including a first level cache system integrated with the microprocessor, a second level external cache system and a third level external cache system. The second level cache system is a conventional, high speed, SRAM-based, writeback cache system. The third level cache system is a large, writethrough cache system developed using conventional DRAMs as used in the main memory subsystem of the computer system. The three cache systems are arranged between the CPU and the host bus in a serial fashion. Because of the large size of the third level cache, a high hit rate is developed so that operations are not executed on the host bus but are completed locally on the processor board, reducing the use of the host bus by an individual processor board. This allows additional processor boards to be installed in the computer system without saturating the host bus. The third level cache system is organized as a writethrough cache. However, the shared or exclusive status of any cached data is also stored. If the second level cache performs a write allocate cycle and the data is exclusive in the third level cache, the data is provided directly from the third level cache, without requiring an access to main memory, reducing the use of the host bus.
A method for preventing deadlock due to the need for data exclusivity when performing forced atomic instructions in a multi-level cache in a multi-processor system. The system determines whether an aligned multi-byte word in which the data of a forced atomic instruction, such as an integer store operation, is exclusive in a first level cache. If so, the forced atomic instruction is allowed to enter a second level cache pipeline. If not, the forced atomic instruction is prevented from entering the second level cache pipeline and a cache miss and fill operation is initiated to cause the aligned word to be exclusive in the first level cache.
