In a data processing system having a plurality of queues for prioritizing I/O requests to a storage device, the priority of the queues for servicing is dynamically adjustable as opposed to each queue having a fixed priority. Dynamically adjusting the priority of a queue allows the priority of a queue with "stuck" requests to be raised so the "stuck" requests can be serviced very quickly.

In order to make use of row address lock mode of operation of a plurality of memory banks comprising synchronous DRAMs or the like and divided into a plurality of real bank groups, for example, for example, more than the memory banks are grouped into a plurality of logical groups each spanning the real bank groups. Addresses are allocated in unit of each logical group in a block-interleaving manner. When a series of requests issued by a given requester include a plurality of requests for accessing the same row address in the same memory bank, that requester requests that the row address be locked for access by the plurality of requests. The lock request is retained by a row address management unit. When a succeeding request from another requester requests access to a row address other than the locked address in the same memory bank, a priority circuit selects a predetermined number of requests from the initial requester having locked the memory in preference to a request made by the other requester.

When an IOP is transferring data at the maximal throughput because of the fact that the input-output processor (IOP) has issued a next request under a state when the request buffers are full of requests from the IOP at least a part of the requests from the instruction processor (IP) is inhibited. Inhibition of the requests from the IP is released when the pitch of the requests from the IOP reaches a predetermined period or more. When the IOP is transferring data at the maximal throughput in a system having a cache memory, access to the main memory by the IP is inhibited in case requested data does not exist in the cache memory.

A cache memory control unit includes plural banks composing a cache memory, an address array for feeding a hit signal or a mishit signal indicating whether or not the corresponding data is stored in the cache memory in response to the access requests received from plural instruction processors couples to the cache memory, and a data transfer requester for sending out a data transfer request to the main storage in response to a mishit signal. Each of the banks includes a first stack for holding an access request according to the access request and the hit signal, and a transfer data monitor for monitoring the data sent out of the main storage according to the data transfer request for the main storage, accessing each of the banks based on the access request from the first stack if the data is not being sent, and sending out the data from the bank to any one of plural instruction processors.

An imaging system in which, if image data of variable resolutions is to be handled in keeping with the increasing resolution of the image data, the processing is executed efficiently without lowering the processing capability of the respective circuits. A memory controller time-divisionally transmits an acknowledge signal to the respective circuits within a range of the bandwidth limitation of an image data bus in which image data can be furnished to the respective circuits, and manages control so that the respective circuits will execute the pre-set processing. The memory controller has access to data in the respective circuits in real-time to cause image data to be written from the respective circuits to the image memory or to be read out from the image memory and sent to the respective circuits.