A heterojunction field effect transistor structure having a plurality of vertically stacked field effect devices. Two or more devices having electrically independent source and drain regions are formed such that a single gate electrode controls current flow in each of the devices. Each of the vertically stacked FETs have electrically isolated channel regions which may be controlled by a single gate electrode. Vertically stacked devices provide greater device packing density.
A semiconductor device comprises a heterostructure which includes first and second mutually separated conductive layers, e.g., active layers in which a respective two-dimensional electron gas can be induced. A source region and drain region each contact both conductive layers. A gate electrode is disposed between the source and drain regions. First and second output contact regions each contact both conductive layers. The first and second output contact regions are positioned between the source and drain and are overlapped by the gate electrode.
A complementary field effect structure having a first field effect device (26) including a quantum well having a first channel (12). A first doping region (14) is positioned adjacent to a first quantum well and a first gate electrode (29) is positioned so that the first doping region (14) is between the first gate electrode (29) and the first channel (12) . A second field effect device (37) includes a second channel (22) and a second doping region (19) positioned adjacent to the second channel. A second gate electrode (31) is positioned over the second channel (22) so that the second channel (22) is between the second gate electrode (31) and the second doping region (19). An interconnect electrically couples the first gate electrode (29) to the second gate electrode (31).
A complementary heterojunction semiconductor device (10) has a first resonant interband tunneling transistor (12) coupled to a second resonant interband tunneling transistor (14) through a common output (16). The first transistor (12) has a first gate (18) of a first semiconductor type and a drain (28) coupled to the first gate (18). The first gate (18) is also coupled to the common output (16). The second transistor (14) has a second gate (32) of a second semiconductor type and a source (42) coupled to the second gate (32). The second gate (32) is also coupled to the common output (16). The valence band (60,80,82) of the first semiconductor type has an energy level greater than the conduction band (62,64,84) of the second semiconductor type.
A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.
Logic circuits using a heterojunction field effect transistor structure having vertically stacked complementary devices is provided. A P-channel quantum well and an N-channel quantum well are formed near each other under a single gate electrode and separated from each other by a thin layer of barrier material. P-source and P-drain regions couple to the P-channel. N-source and N-drain regions couple to the N-channel. The P-source/drain regions are electrically isolated from the N-source/drain regions so the P-channel and N-channel devices may be interconnected to provide many logic functions.
