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Description  |
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BACKGROUND OF THE INVENT ION
1. Field of the Invention
This invention relates to video signal processing circuits. More
particularly, it relates to such circuits in which video signals, for
example, from a video tape recorder, are subjected to error correction,
error concealment and weighted mean processing.
2. Description of the Prior Art
In recording and/or reproducing digital sample data of video signals by
means of a digital video tape recorder (VTR), so-called "code errors"
result from noise or defects in the recording medium. The erroneous sample
data produced by the code errors are subjected to error correction using
error correction codes and those which cannot be thus corrected are
subjected to error concealment by interpolation or replacement using other
error-free sample data. In generating a sequence of odd and even numbered
fields which have been disrupted as a consequence of reproduction at a
speed different from that employed during recording, weighted mean
processing is frequently performed in which signals of a given field are
used to form signals of another field.
In the so-called "D-1" format (a 4:2:2 format set forth in CCIR
recommendations No. 601), which is one of the formats used in component
digital VTR, two-dimensional error correction using a product code is
performed, which involves the use so-called "outer"and "inner" codes.
During recording, 360-byte-per-line sample data are subjected to in-line
shuffling, and then are fed to a two-dimensional error correction coding
circuit where product codes are added thereto. First, a 2-bit outer code,
i.e. outer correction code or outer purity, is annexed at intervals of 30
bytes or samples. The resulting code block is subjected to sector array
shuffling and then a 4-byte inner code, i.e., inner correction code or
inner party, is annexed at intervals of 60-bytes-per-row of sample data in
the perpendicular direction of the shuffled code block to form an inner
code block. A sync block structure generated from two such inner code
blocks is recorded as a unit on the magnetic tape. During playback, an
operation which is the reverse of the above mentioned operation is
performed. Thus, two of the inner code blocks are removed from the sync
block and subjected to error correction with the use of the inner code,
followed by deshuffling which is the reverse of the above described sector
array shuffling. Finally, a so-called erasure correction is performed,
using 2-byte outer codes at intervals of each outer code block having 32
bytes per row.
Any erroneous sample data, which could not be error corrected through the
use of the product code, are subjected to error concealment by
interpolation or replacement. Among the methods for error concealment are
(1) a method of interpolation in the horizontal or H direction, using
sample data on both sides of and on the same line as the erroneous sample
data, (2) a method of interpolation in the vertical or "V" direction,
using sample data at the same horizontal position as and on lines above
and below the line of the erroneous sample data, (3) a method of
interpolation in the D.sub.+ direction, using near-by sample data on a
positive diagonal line of the reproduced video image, that is, a diagonal
line with a rightward positive gradient, (4) a method of interpolation in
the D.sub.- direction, using near-by sample data on a negative diagonal,
that is, on a diagonal with a negative gradient from left to right, (5) a
method of replacement with error-free samples of the preceding frame or
field exhibiting high temporal correlation, and (6) a method of replacing
the erroneous sample data with near-by sample data.
Meanwhile, it is desirable for actual error concealment to function over a
wide range of error rates, for example, over a range from substantially 0%
during normal reproduction to substantially 100% during high speed tape
shuttling.
However, an error concealment method with a high concealment accuracy may
operate properly for a low error rate but fail to operate properly for a
high error rate, while an error concealment method which is usable even at
a high error rate may suffer from low concealment accuracy, such that no
single concealment method is fully effective o conceal errors with
suitable or acceptable concealment accuracy over the above mentioned wide
range of error rates. Even if it were possible to use a plurality of error
concealment methods in combination and to provide the ability to switch
manually from one to the other manual switching is cumbersome and
undesirable from the standpoint of operational reliability.
On the other hand, in case of a high error rate in the sample data
reproduced by the VTR, most of the sample data are erroneous and thus
cannot be error concealed by interpolation or replacement. It is however
desirable that some sort of error concealment be carried out even on these
occasions.
Additionally, it occurs frequently that correct sample data are contained
in sample data which as a whole have been determined to be in error in the
course of the error correction process. For example, in the course of the
above-mentioned outer error correction, when the number of erasure
pointers generated by the inner error correction product code exceeds the
number of parities of the outer code, it is possible to compute the
syndrome of the outer code block without performing error correction
thereon, when all of these syndromes are determined to be "0", under the
assumption that all of the sample data in the outer code block are free of
errors. However, in employing the inner code or inner parity, it is
possible that erroneous data will be deemed to be correct since it is not
certain that the inner code or parity has sufficient error detection
capability to generate correct erasure pointers, or if error detection by
the outer code or parity exhibits a sufficient reliability. It is
undesirable from the viewpoint of reliability to treat such sample data as
being error free, while it is wasteful to discard it as erroneous.
When weighted mean processing is to be performed in order to synthesize
signals of one field from signals of a given or existing field after error
concealment, several horizontal delay devices are required for error
concealment, and especially for two-dimensional error concealment, while
several other horizontal delay elements are required for weighted mean
processing. However, the use of dedicated horizontal delay devices for
error concealment and weighted mean processing would be uneconomical.
Finally, when weighted mean processing operations are performed at the
upper and lower ends of the picture surface the image quality may
deteriorate and the picture may suffer from flicker or vertical movement.
OBJECTS AND SUMMARY OF THE INVENTION
It is an object of the present invention to provide a video signal
processing circuit which is free of the above drawbacks.
It is another object of the present invention to provide a video signal
processing circuit in which effective error concealment may be performed
over a wide range of error rates.
It is a further object of the present invention to provide a video signal
processing circuit whereby optimum error concealment may be performed
within a wide range even at error rates up to 100%.
It is a further object of the present invention to provide a video image
processing circuit wherein a mode-independent concealment strategy is
adopted in which the concealment method used is independent of the current
playback mode and the best possible concealment method for the current
error situation can be selected.
It is a further object of the present invention to provide a video image
processing circuit wherein variable-length horizontal interpolation is
employed in which the number of samples used in the horizontal concealment
calculation can be varied automatically from two to six samples.
It is a further object of the present invention to provide a video signal
processing circuit having an ideal direction ranking capability in which
the concealment directions may be ranked from best to worst.
It is a further object of the present invention to provide a video signal
processing circuit wherein luminance data are used to determine the ideal
direction ranking, which direction ranking may be used for both luminance
and chrominance concealment.
It is a further object of the present invention to provide a video signal
processing circuit wherein an error threshold serves to limit the use of a
concealment method based on an estimated concealment error value.
It is a further object of the present invention to provide a video signal
processing circuit wherein adaptive temporal replacement is employed such
that video data and error flags surrounding a point being concealed are
examined to determine whether the data in a current frame is substantially
the same as the video data in a preceding frame and, based on such
determination, using such video data from the preceding frame to conceal
errors in the current frame.
It is a further object of the present invention to provide a video signal
processing circuit including concealment circuitry having its own frame
memory.
It is a further object of the present invention to provide a video signal
processing circuit wherein the maximum number of recursion levels allowed
for recursive concealment is made variable in order to selectably
determine the maximum concealment area that may be derived from an
error-free point.
It is a further object of the present invention to provide a video signal
processing circuit wherein, for sample data that may not actually be
erroneous the concealment value produced by a concealment method is
compared with the original value of the sample data and, if the difference
therebetween is less than a pass-through threshold value, the original
value is output in place of the concealment value.
It is a further object of the present invention to provide a video signal
processing circuit wherein, when performing weighted mean processing for
synthesizing signals of one field from signals of a given or known field,
for correcting an odd and even sequence of the fields which has been
disrupted horizontal delay devices are used in common for the respective
processing operations to reduce the required number of such delay devices.
It is yet another object of the present invention to provide a video signal
processing circuit in which weighted mean processing is carried out using
selectably different signal combination methods for sample data at the
upper and the lower edges of the picture surface, on the one hand and for
sample data at the inner portions, on the other.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing the general organization of a video
signal processing circuit according to an embodiment of the present
invention and its peripheral circuity.
FIG. 2 is a block diagram showing a typical construction of a
one-dimensional error concealment circuit.
FIG. 3 depicts error states of sample data for illustrating the operating
principle of the one-dimensional error concealment circuit of FIG. 2.
FIG. 4 is a guide for arranging FIGS. 4A and 4B.
FIGS. 4A and 4B together constitute a block circuit diagram showing an
embodiment of a variable-length interpolation circuit.
FIG. 5 shows an array of sample data to be processed by two-dimensional
error concealment.
FIG. 6 shows an array of error flags for the sample data of FIG. 5.
FIG. 7 is a block circuit diagram of a ranking control circuit for
two-dimensional error concealment.
FIG. 8 is a guide for arranging FIGS. 8A, 8B and 8C.
FIGS. 8A, 8B and 8C together constitute a block circuit diagram showing a
more detailed construction of the ranking control circuit of FIG. 7.
FIG. 9 is a block circuit diagram showing a main part of an embodiment of a
two-dimensional error concealment circuit.
FIG. 10 is a block circuit diagram for illustrating one embodiment of a
high accuracy temporal replacement decision circuit.
FIG. 11 is a block circuit diagram for illustrating embodiments of high and
low accuracy temporal replacement circuits.
FIG. 12 is a block circuit diagram for illustrating an embodiment of a low
accuracy temporal replacement decision logic circuit.
FIGS. 13 and 14 illustrate a number of generations of sample data produced
by repetitive replacement.
FIGS. 15 and 16 represent video images produced by a combination of
recursive replacement and default temporal replacement.
FIG. 17 is a block circuit diagram of a repetitive replacement decision
circuit.
FIG. 18 is a block circuit diagram of a gray flag processing circuit.
FIG. 19 is a block circuit diagram showing a weighted mean processing
circuit and its peripheral circuitry.
FIG. 20 illustrates weighted mean processing near the upper and lower edges
of a picture.
FIG. 21 is a block diagram for illustrating the principle of implementing a
variable coefficient multiplication circuit utilizing bit shifting and
summation.
FIG. 22 is a chart for illustrating gain and delay characteristics of line
signals formed by weighted mean processing and located at field positions
apart from the upper and lower ends of the picture.
FIG. 23 is a chart for illustrating gain and delay characteristics of the
line signal of a field in the vicinity of the upper end of the picture,
formed with a fixed value weighting coefficient.
FIG. 24 shows gain and delay characteristics of line signals of an image
formed with a weighting coefficient different from that used to form the
line signals of FIG. 22.
FIG. 25 is a block diagram showing an embodiment of a variable coefficient
multiplication circuit employing a read only memory.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
OVERALL CONSTRUCTION OF VIDEO SIGNAL PROCESSING SYSTEM
FIG. 1 shows, in a block diagram, a video signal processing circuit
according to an embodiment of the present invention, and its peripheral
circuitry. In the present illustrative embodiment, signal processing is
assumed to be performed on signals reproduced by a D-1 format digital VTR.
A D-1 format digital VTR is so constructed that digital video (and audio)
signals are allocated to e.g. four channels and the digital signals of
these four channels are recorded and/or reproduced in parallel by four
rotary magnetic heads.
Thus, the four-channel reproduction signals (a to d channel signals) from
the four magnetic heads of the digital VTR are subjected to clock
regeneration, demodulation and error correction through the use of a
so-called "inner code", i.e. inner correction code or inner parity
previously added to the signals. The four channel data thus subjected to
inner code error correction are transmitted to field memories 101a, 101b,
101c and 101d shown in FIG. 1. Each of these field memories 101a to 101d
has a memory capacity of, e.g., three fields. The video data of the
respective channels sequentially read out from these field memories 101a
to 101d are transmitted to deshuffle circuits 102a, 102b, 102c, 102d for
deshuffling and then transmitted to outer code error correction circuits
103a, 103b, 103c, 103d for error correction through the use of a so-called
"outer code", i.e outer correction code or outer parity likewise added to
the signals previously. At this time, the gray flags (described
hereinbelow) are annexed to the data, in addition to the usual error
flags. These four channels of video data, including error flags and gray
flags, are transmitted to a deinterleaving circuit for deinterleaving and
are grouped together, while being separated into a luminance component and
a chrominance component, which are transmitted to a luminance component
error concealment section 105Y and a chrominance component error
concealment section 105C. The luminance component data and the chrominance
component data, with errors concealed by the error concealment sections
105Y, 105C, respectively, are output by way of output circuits 106Y, 106C,
respectively.
The gray flag is briefly explained hereinafter. In the D-1 format digital
VTR, a two-dimensional error correction is performed by a product code
using so-called outer and inner codes. Thus, during recording,
360-byte-per-line sample data in one channel are subjected to product code
error correction coding. First, at intervals of 30 bytes or 30 samples a
to byte outer code, that is outer correction code or outer parity, is
generated and annexed and the data are subjected to a second array
shuffling to form a 32 sample.times.60 row product block array. Then, at
an interval of 60 samples per row a 4-byte inner code, that is, inner
correction code or inner parity, is generated and annexed to form 32 rows
of inner code blocks, with each row consisting of 64 samples. Two of the
64-sample inner code blocks are connected together and a sync pattern (2
bytes) and an identification pattern (4 bytes) are annexed to a leading
position to form a sync block. The data is recorded on magnetic tape
wherein each sync block is regarded as one recording unit.
In reproduction, an operation which is the reverse of the above described
sequence is performed. Thus, two inner code blocks are taken out from the
sync block and subjected to error correction with the use of the inner
code to produce data of the above mentioned product block array
organization which are then input to the field memories 101a to 101d of
FIG. 1 as the input data. In deshuffling circuits 102a to 102d, a
deshuffling operation, which is the reverse of the above mentioned sector
array shuffling operation, is performed. In the outer code correction
circuits 103a to 103d, a so-called erasure correction is performed, at
intervals of 32 sample-per-column outer code blocks using the two-byte
outer code. The erasure pointer used at this time is obtained at the time
of the above mentioned inner code error correction.
Meanwhile, when there is a large number of error samples in the inner code
block such that error correction becomes impossible because the error
correction ability of the inner code is overloaded, the inner code block
in its entirety is deemed to be in error and erasure pointers are set. The
inner code block is passed to erasure correction by the outer code. The
outer code acts perpendicularly to the inner code. It is capable of
detecting if any errors exist, and can correct one or two errors
(erasures). Normally, when the number of erasure pointers is three or
more, (i.e. the inner code is overloaded for three or more inner code
blocks), the error correction capability of the outer code block is also
overloaded and the entire block is marked as being in error for purposes
of error concealment. However, when random error is encountered it occurs
frequently that, even when a small number of sample data in the inner code
block are in an error state, the remaining sample data are correct data,
i.e. error-free data. Thus, considering that most data of the inner code
block deemed to be in error in their entirety are, in fact, correct data,
all data in the outer code block may be assumed to be correct if, as a
result of error detection by the outer code, such is determined to be free
of errors. However, in view of the possibility of mistaken error
detection, it is not desirable that the block be handled as completely
correct data only on the basis of the results of error detection by the
outer code. Thus, to indicate seemingly correct data, gray flags are
introduced. Thus, where sample data is deemed to be in error as a whole by
inner code error detection but deemed to be free of error by the results
of error detection by the outer code, the error flag is reset, while the
gray flag is set. When the difference upon comparison of the original
sample data with the result of error concealment is within a predetermined
threshold, the probability is extremely high that the data are correct so
that the original sample data are handled as the correct data.
The sample data which have been corrected for errors, inclusive of sample
data which are in error and which have not been corrected for errors, are
transmitted, along with the error flags and the gray flags, so as to be
supplied to the error concealment units 105Y, 105C for error concealment.
GENERAL CONSTRUCTION OF ERROR CONCEALMENT UNIT
The arrangement of the luminance component error concealment unit 105Y and
the chrominance component error concealment unit 105C, shown in FIG. 1, is
hereinafter explained. Since the concealment units 105Y, 105C are of
substantially the same construction, only one of the units, herein the
luminance component error concealment unit 105Y, is explained.
To the luminance component error concealment unit 105Y, there are supplied,
in association with the luminance component of the component digital video
signals, sample data which have been corrected for errors as described
above, together with error flags and gray flags. Of these, the sample data
and the error flags are first transmitted to a one-dimensional concealment
circuit 111 for error concealment in the horizontal direction, that is, in
the direction of the horizontal scanning lines, and then transmitted to a
two-dimensional concealment circuit 112 and a line delay circuit 113
having a delay time of 1H, i.e. one horizontal scanning period. The
outputs (the sample data and the delayed error flags) from the
two-dimensional concealment circuit 112 are transmitted to a line delay
circuit 114 and a frame delay circuit 115 having a delay time of one frame
(1F=2V=2 vertical scanning periods). The outputs from these line delay
circuits 113, 114 and from the frame delay circuit 115 (sample data and
error flags) are transmitted to the two-dimensional concealment circuit
112. The output signal from the line delay circuit 113 is the reference
signal for a current line 0H, whereas the output from the one-dimensional
concealment circuit 111 corresponds to the sample data and error flags for
-1H, that is, one line below the current line, the output from the line
delay circuit 114 corresponds to the sample data and error flags for +1H,
that is, one line above the current line and the output from the frame
delay circuit 115 corresponds to the sample data and error flags for +1F,
that is, the current line of the previous frame. In other words, sample
data for the current line, the lines directly above and below the current
line and the current line of the previous frame, are supplied to the
two-dimensional error concealment circuit 112.
If a delay TD caused by processing in the two-dimensional error concealment
112 is to be taken into account, it is sufficient if the delay time in the
line delay circuit 114 and the frame delay circuit 115 are set so as to be
H-T.sub.D and F-T.sub.D, respectively.
In the two-dimensional error concealment circuit 112, an optimum error
concealment is performed, using the sample data on the above mentioned
four lines. This two-dimensional error concealment circuit 112 has a
plurality of error concealing functions, including interpolation in a
plurality of directions, replacement of the erroneous sample data by
sample data at the same position of the previous frame or replacement of
the erroneous sample data by vicinal or neighboring sample data and
execution of error concealment in an ideal direction which will minimize
changes in the sample data. For finding this optimum direction, a ranking
control circuit 117 is provided within the two-dimensional error
concealment circuit 112. It is in this ranking control circuit 117 that
the optimum direction of two-dimensional error concealment is found on the
basis of the sample data and the error flags and, based on the results, an
optimum two-dimensional error concealment is executed.
In the above described manner, error concealment is performed on the
erroneous sample data which have not been corrected for errors in the
course of the error correction of the preceding stage.
A weighted mean processing circuit is hereinafter described. The sample
data from the two-dimensional concealment circuit 112 are transmitted to a
weighted mean processing circuit 120 by way of a gray flag processing
circuit 118. Sample data are simultaneously supplied to this weighted mans
processing circuit 120, from (a) one line above the current line (i.e.
+1H), provided from the line delay circuit 114, (b) sample data at the
relative position of +2H, that is, two lines above the current line, after
a delay introduced in a line delay circuit 121, and (c) sample data at the
relative position of -1H, that is, one line below the current line, from
the one-dimensional concealment circuit 111. In the weighted mean
processing circuit 120, video sample data from a plurality of lines are
summed together in a predetermined mixing ratio to provide signals for at
least another field from the signals of a given field. This processing is
performed to compensate for disorders in the sequence of even- and
odd-numbered fields brought about by different speed reproduction of VTR
video signals.
Meanwhile, if the processing time T.sub.D in the two dimensional
concealment circuit 112 and the processing time T.sub.G in the gray flag
processing circuit 118 is to be taken into consideration, it is sufficient
to set the delay time in the line delay circuit 121 to 1H+T.sub.D
+T.sub.G, while introducing a delay circuit having a delay time equal to
T.sub.D +T.sub.G between the line delay circuit 114 and the weighted mean
processing circuit 120 and between the one-dimensional concealment circuit
111 and the weighted mean processing circuit 120.
In the circuitry of FIG. 1, a signal delayed by 1H in the line delay
circuit 113 is transmitted by way of the two dimensional concealment
circuit 112 and a gray flag processing circuit 118 to the weighted mean
processing circuit 120 to provide a 0H or reference position signal. On
the other hand, a line delayed by 1H in the line delay circuit 114 and the
1H delayed signal further delayed through a line delay circuit 121 are
transmitted to the weighted mean processing circuit 120 to provide,
respectively a +1H signal, that is, the signal one line above the
reference position signal and a +2H signal, that is, a signal two lines
above the reference signal. The signal from the one-dimensional
concealment circuit 111 is the -1H signal, that is, the signal one line
below the reference signal. In this manner, the line delays induced by the
line delay circuit 113, 114, simultaneously produce the necessary plural
line signals at the weighted mean processing circuit. In other words, the
line delay circuits 113, 114 are used simultaneously in two-dimensional
error concealment and in weighted mean processing. In this manner, one
delay circuit may be used in lieu of three line delay circuits dedicated
to weighted mean processing in the conventional system, so that a
significant saving may be realized in memory capacity.
In the circuitry of FIG. 1, of the four video signals transmitted to the
weighted mean processing circuit 120, the -1H, signal is directly supplied
from the one-dimensional concealment circuit 111 and thus remains in the
state prevailing before the two-dimensional concealment is executed.
However, in view of the low weighing factor for the -1H sample data at the
time of the weighted mean processing operation, it is not crucial to
perform high precision concealment and hence no practical problem is
raised. It is however, possible to add a line delay circuit in the
weighted mean processing circuit to delay the signal from the line delay
circuit 121 further by 1H and to supply the thus delayed signal to the
circuit 120 without using the video signal from the one-dimensional
concealment circuit 111. In this case, the delay of the output signal from
the delay circuit 114 is the reference 0H and that of the output signal
from the two-dimensional concealment circuit 112 is -1H such the totality
of the four input video signal is replaced by signals which have undergone
two-dimensional concealment. In this case, although two line delay
circuits each in the two-dimensional error concealment processing section
and in the weighted mean processing circuit, thus totalling four line
delay circuits, are required, one line delay circuit may be saved as
compared with one conventional system.
ERROR CONCEALMENT METHODOLOGY
The error flags associated with luminance video sample data and multiplexed
chrominance video sample data are inspected. It is assumed that both o | | |
