Apparatus and method for positioning an integrated circuit chip within a multichip module

What is claimed is:

1. A method for attaching an integrated circuit chip to an upper surface of a substrate having a fiducial mark thereon, said attaching method utilizing a high accuracy XY table, said table having a first rotational adjustment stage and a second rotational adjustment stage, said first rotational adjustment stage comprising a chip alignment stage for holding and aligning a chip relative to XY table motion, said second rotational adjustment stage comprising a substrate alignment stage, said attaching method further utilizing a chip pickup for removing said chip from said chip alignment stage and for placing said chip on said substrate and a memory means containing desired positional offset information for said chip relative to said substrate fiducial mark, said method comprising the steps of:

(a) placing a substrate on said substrate alignment stage, said substrate having an adhesively coated upper surface;

(b) aligning said substrate relative to XY table motion;

(c) locating and saving in said memory means the position of the fiducial mark on said substrate;

(d) placing a chip on said chip alignment stage;

(e) aligning said chip relative to XY table motion, said chip aligning being accomplished with reference to a characteristic feature of said chip;

(f) energizing said chip pickup to lift said chip from said die alignment stage;

(g) positioning said substrate under said chip by moving said XY table;

(h) recalling from said memory means the stored offset for said chip relative to said fiducial mark on said substrate;

(i) lowering said chip to a desired location on the upper surface of said substrate based on said recalled, chip offset location, and allowing a portion of the weight of said chip pickup to be applied to said chip;

(j) holding said chip pickup against said chip for a period of time to allow said chip to adhesively attach to said substrate; and

(k) releasing said chip from said chip pickup.

2. The chip attach method of claim 1, wherein multiple chips are to be attached to the upper surface of said substrate, and said method further comprises repeating said steps (d)-(k) for each of said multiple chips to be attached to said substrate.

3. The chip attach method of claim 1, further comprising the step of locating the center of each chip, and wherein said chip pickup energized in said step (f) lifts said chip relative to said located chip center.

4. A method for attaching a first and second integrated circuit chips to an upper surface of a substrate having a reference feature thereon, said attaching method utilizing a high accuracy XY table, said table having a first rotational adjustment stage and a second rotational adjustment stage, said first rotational adjustment stage comprising a chip alignment stage and said second rotational adjustment stage comprising a substrate alignment stage, said attaching method further utilizing a chip pickup and memory storage means having at least a prestored desired location information for said second chip relative to a reference feature of said first chip, said method comprising the steps of:

(a) placing the substrate on said substrate alignment stage, said substrate having an adhesively coated upper surface;

(b) aligning said substrate relative to XY table motion;

(c) locating and saving in said memory means the position of the substrate reference feature;

(d) placing the first chip on said chip alignment stage;

(e) aligning said first chip relative to XY table motion, said first chip aligning being accomplished with reference to at least one reference feature of said first chip;

(f) energizing said chip pickup to lift said first chip from said chip alignment stage;

(g) positioning said substrate under said first chip by moving said XY table;

(h) recalling from said memory means the stored offset for said first chip relative to said substrate reference feature;

(i) lowering said first chip to the desired location on the upper surface of said substrate based on said recalled, first chip offset location, and allowing a portion of the weight of said chip pickup to be applied to said first chip;

(j) releasing said first chip from said chip pickup;

(k) placing the second chip on said chip alignment stage;

(l) aligning said second chip relative to XY table motion, said second chip aligning being accomplished with reference to at least one characteristic feature of said second chip;

(m) energizing said chip pickup to lift said second chip from said chip alignment stage;

(n) positioning said substrate under said second chip by moving said XY table;

(o) recalling from said memory means the prestored desired location information for said second chip relative to a reference feature of said first chip;

(p) lowering said second chip to the desired location on the upper surface of said substrate based on said recalled, second chip offset location, and allowing a portion of the weight of said chip pickup to be applied to said second chip; and

(q) releasing said second chip from said pickup.

5. The chip attach method of claim 4, wherein said steps (k)-(q) are repeated for each of a plurality of chips to be attached to said substrate.

6. The chip attach method of claim 5, wherein for each of said plurality of chips said lowering step (p) further includes holding said chip pickup against said chip for a period of time sufficient to allow said chip to adhesively attach to said substrate.

7. A method for accurately positioning a plurality of die on a substrate without reference to a substrate fudicial mark, said substrate having a first physical reference feature and a first one of said plurality of die having a second physical reference feature, said method comprising the steps of:

(a) positioning said first one of said die relative to said first physical feature of said substrate; and

(b) subsequent said step (a), positioning the remaining die of said plurality of die on said substrate relative to said second physical reference feature of said first die positioned on said substrate, wherein only said first die is positioned on said substrate relative to said substrate first physical reference feature while the reaming chips are placed on said substrate relative to said first die's second physical reference feature.

8. The die positioning method of claim 7, wherein said first physical reference feature of said substrate used in said positioning step (a) comprises a corner of said substrate.

9. The die positioning method of claim 7, wherein said first die's second physical reference feature employed in said step (b) comprises an interconnection pad located on an upper surface of said first die.

10. Apparatus for accurately positioning a plurality of die on a substrate without reference to a substrate fiducial mark, said apparatus comprising:

first means for positioning a first one of said die relative to a physical feature of said substrate, said first die having a first physical feature to facilitate the subsequent positioning of said plurality of die on said substrate; and

second means operatively associated with and responsive to said first means for accurately positioning the remaining die of said plurality of die on said substrate relative to the physical feature on an upper surface of the first die positioned on said substrate by said first means, wherein said chips are each accurately positioned relative to one another within the tolerances of said second positioning means' capability to recognize said first die's first physical feature.

11. The die positioning apparatus of claim 10, wherein said substrate physical feature used by said first positioning means comprises a corner of said substrate.

12. The die positioning apparatus of claim 10, wherein said first die's physical feature used by said second positioning means comprises an interconnection pad located on the upper surface of said first die.

13. The die positioning apparatus of claim 10, wherein said first positioning means positions said first die relative to said substrate physical feature with reference to said first physical feature of said first die, and wherein said second positioning means uses said first physical feature of said first die to position the remaining die of said plurality of die.

14. The die positioning apparatus of claim 13, wherein said first physical feature of said first die comprises an interconnection pad on the upper surface of said first die.

15. Apparatus for accurately positioning a die relative to a substrate having a fiducial mark thereon, said apparatus comprising:

a high accuracy XY table, said table having a first rotational adjustment stage and a second rotational adjustment stage, said first rotational adjustment stage comprising a die alignment stage for holding and aligning a die relative to XY table motion based on a physical feature of the die, said second rotational adjustment stage comprising a substrate alignment stage, said substrate alignment stage including means for holding said substrate having said fiducial mark thereon;

locating means operatively associated with said high accuracy XY table for locating the fiducial mark on said substrate;

a die pickup operatively associated with said high accuracy XY table for removing said die from said die alignment stage and for placing said die on said substrate; and

control processing means coupled to said first and second rotational adjustment stages of said XY table, said locating means and said die pickup, for controlling the respective alignment of said substrate and said die, and transfer of said die to the desired location on said substrate relative to said located fiducial mark using said die pickup.

16. The die positioning apparatus of claim 15, further comprising a bridging structure disposed over said XY table, said bridging structure supporting said locating means and said die pickup.

17. The die positioning apparatus of claim 16, wherein said die pickup includes two motion stages, a first motion stage being reciprocally mounted to said bridging structure for Z-axis movement relative to said XY table, said first motion stage having a lower stop affixed thereto, and a second motion stage mounted to said first stage for reciprocal Z-axis movement relative to said first stage, said lower first stage stop being affixed so as to contact and raise said second stage with the rising of said first motion stage, said second stage having a die attach mechanism secured thereto, said attach mechanism comprising a vacuum pickup tool.

18. The die positioning apparatus of claim 15, wherein said control processing means includes memory means for storing the desired location on said substrate of said die relative to said fiducial mark.

19. The die positioning apparatus of claim 18, wherein multiple die are to be accurately positioned on said substrate using said apparatus, and wherein said memory means stores for each of said multiple die the desired location for the die on the substrate relative to said fiducial mark.

20. The die positioning apparatus of claim 19, wherein said XY table includes vacuum hold means for releasably holding said die during said die alignment stage.

21. Apparatus for accurately positioning a die having a first physical feature relative to a substrate having a second physical feature, said apparatus comprising:

a high accuracy XY table, said table having a first rotational adjustment stage and a second rotational adjustment stage, said first rotational adjustment stage comprising a die alignment stage for holding and aligning the die relative to XY table motion based on said first physical feature of the die, said second rotational adjustment stage comprising a substrate alignment stage, said substrate alignment stage including means for holding said substrate;

locating means operatively associated with said high accuracy XY table for locating said second physical feature on said substrate;

a die pickup operatively associated with said high accuracy XY table for removing said die from said die alignment stage and for placing said die on said substrate; and

control processing means coupled to said first and second rotational adjustment stages of said XY table, said locating means and said die pickup, for controlling the respective alignment of said substrate and said die, and transfer of said die to the desired location on said substrate relative to said located substrate second physical feature.

22. The die positioning apparatus of claim 21, wherein said control processing includes memory means for storing the desired location on said substrate of said die relative to said located second physical feature.

23. The die positioning apparatus of claim 22, wherein said die comprises a first die and multiple additional die are positioned on said substrate using said apparatus, and wherein said control means positions each one of said multiple additional die on said substrate relative to the first die positioned thereon.

24. The die positioning apparatus of claim 23, wherein each of said multiple additional die is positioned on said substrate relative to the first physical feature of said first die positioned on said substrate.

25. The die positioning apparatus of claim 24, wherein said first physical feature of the first die comprises an interconnection pad positioned on an upper surface of said first die.

26. The die positioning apparatus of claim 24, wherein said control means includes memory means for storing the desired position on said substrate of each of the multiple additional die relative to said first physical feature of the first positioned die.

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BACKGROUND OF THE INVENTION

1. Technical Field

The present invention is generally directed to an improved multichip integrated circuit module. More particularly, the present invention relates to a packaging method for electronic integrated circuit chips, particularly very large scale integrated circuit (VLSI) devices, on a substrate also having a polymer encapsulant overlying the chips on the substrate and providing a means for supporting inter chip and intra chip connection conductors. Even more particularly, the present invention relates to a repairable multichip module structure and corresponding repair method; a multichip module structure having high I/O capacity with optimal heat removal through one side and high performance I/O through an opposite side; multichip module structures optimized for speed; multichip module structures having the ability to incorporate an assortment of components of varying thickness and function therein; and multichip modules having an integrated hermetic structure with high I/O count.

2. Description of the Prior Art

Multichip modules are divided into two basic structures. In the most common structure, a miniature circuit board is provided upon which integrated circuits are mounted and electrically connected. The second multichip module structure involves mounting chips on a substrate, and subsequently providing interconnect to the chips by essentially building an interconnecting circuit board over the top of the chips. These two approaches are referred to herein as "chip on board" for the first approach, and "circuit board above chips" for the second approach.

In the "chip on board" approach, the circuit board is typically fabricated using alumina or silicon substrate, with copper or aluminum interconnection metallization. The most frequently used dielectric is polyimide. Silicon dioxide can be used as a dielectric on silicon substrates with certain thermal advantages. There are three primary methods for making connection from the pads of the chips to the miniature circuit board. These are wire bonding, tape automated bonding or tab bonding, and flip chip or solder bump bonding. Each of these approaches, including their advantages and disadvantages, are discussed below.

There are two know prior art approaches for the "circuit board above chips" technique. These approaches are the Semiconductor Thermoplastic Dielectric (STD) process and the High Density Interconnect (HDI) overlay process. In the STD process chips are mounted on a substrate and a thermoplastic dielectric is pressed over the chips at high temperature and pressure such that it fills the gaps between the chips and leaves a dielectric over the tops of the chips. Interconnection in this approach is achieved by: forming via holes in the dielectric to the pads of the chips; subsequently metallizing the entire surface; and patterning the metal to form the interconnect. The HDI overlay approach distinguishes over the STD approach in that chips are placed on a substrate and subsequently a polymer overlay is adhered over the tops of the chips. This overlay bridges the gaps between the chips. Again interconnection is provided by forming via holes in the polymer dielectric, metallizing the entire surface of the overlay and pattering the metal to form the interconnect. A discussion of the HDI overlay approach is provided by Eichelberger et al. U.S. Pat. No. 4,783,695, entitled "Multichip Integrated Circuit Packaging Configuration and Method," and U.S. Pat. No. 4,918,811, entitled "Multichip Integrated Circuit Packaging Method." The subject invention falls into the category of "circuit board above chips" and most closely resembles the STD approach.

Depending on the application and on the choice of multichip module technique, there are a series of problems associated with interconnect of electronic components which are solved with varying degrees of success. The rest of this section discusses these problems in terms of the solution provided by each of the basic prior art multichip module technologies. The problems discussed include heat removal, interconnect density, high frequency performance, alignment of chips or interconnect to the circuit board, reliability, ease of manufacture, interconnection to the next level, capability of repair, substrate choice and hermeticity.

Heat Removal

"Chip on board" technology is at a disadvantage for heat removal because the interlayer dielectric used to separate the conductor layers is also a good thermal insulator. This is true of polyimide and to a somewhat lesser extent of silicon dioxide. Since the chips are mounted on the board, heat must be removed through the dielectric layer which as noted, presents a considerable thermal resistance. "Circuit board above chips" technology is inherently better for heat removal since the chips are mounted directly on the substrate. In this case, the only thermal resistance encountered is due to the material that the chip is made of, the die attach material and the thickness of the substrate. (As noted below, pursuant to the subject invention chips are thinned to approximately one-third their original thickness. This is to reduce the thermal resistance due to the chip material, and is especially important when using GaAs as a chip material since GaAs is a reasonably poor thermal conductor. Note also that the die attach material can be applied in the subject invention by either spin or spray techniques, which allows a very thin glue line to be formed. The reduced material thickness contributes directly to reduced thermal resistance in the adhesive.)

Interconnect Density

In many applications it is desireable to achieve the greatest amount of interconnected electronics in the smallest amount of space. In the multichip modules several factors limit the ability to interconnect ICs which are separated by vary small spacings. The factors which limit the spacings between chips are different depending on the approach. In the "chip on board" approach, space must be provided between chips to allow interconnection from the pads of chips to the pads of the circuit board. Typical required spacings are 50 mils for wire bonding from a chip pad to a pad of the circuit board. This means that each chip requires a picture frame of 50 mils around the chip before additional chips can be placed. Tape automated bonding also requires substantial space on the same order of 50 to 100 mils, for bonding from the pads of the chip to the pads of the circuit board. Flip chips or solder bump involves connecting chips with small balls of solder between the pads of the chip and the pads of the circuit board. This technique can allow very close spacing between adjacent chips since, in principle, there is no area required around the periphery of the chip in order to make the interconnect. It should be noted that the flip chip bonding approach is not without substantial disadvantages. First, the chips are rigidly connected to the circuit board by the solder bumps such that differential thermal expansion produces extreme stresses on the chip and the solder bump interconnect. In addition, thermal performance of this structure is poor because the solder bumps do not provide thermal conductivity to the circuit board and the back of the chip is not thermally connected to anything. In certain systems thermal pistons have been provided for heat removal in this structure.

The "circuit board above chips" approach is inherently capable of higher density interconnect in that chips are interconnected within their own periphery. The overlay approach, which utilizes adaptive lithography, suffers somewhat because adaption moats must be provided around each chip in order to accommodate any slight mispositioning of the chips during the die attach process.

A second factor limiting achievable interconnect density is the resolution of the interconnect patterning. The major effect limiting the patterning resolution is the planarity of the interconnect surface. "Chip on board" circuits are fabricated on flat substrates and interconnect planarity is no factor. With the "circuit board above chip" approach, interconnect planarity is an issue. For example, in the overlay approach there are substantial dips between adjacent chips depending on the separation between the chips. This problem is further exacerbated by certain combinations of large and small chips. The result is typically a surface for interconnect patterning which has two to four mil nonplanarity. Contact masking techniques as well as low F number imaging techniques suffer degraded performance in resolution with this level of nonplanarity. (It should be noted that the subject invention is specifically distinguished by a highly planar interconnect surface.)

High Frequency High Speed Performance

All of the multichip module structures described thus far are capable of delivering good high speed performance up to 100 to 200 megahertz clock frequency. When frequencies exceed 200 megahertz, however, special processing techniques must be incorporated to insure optimum operation at the highest frequency. In all cases, impedance controls are necessary and terminating resistors are required. The "circuit board above chip" approach has an advantage at high speeds because the controlled impedance interconnect can be provided all the way to the chip pad. In the "chip on board" approach, a discontinuity is inserted when making the connection from the circuit board to the pad of the chip. This discontinuity results from using wire bond or TAB bonding techniques. The use of flip chip bonding substantially reduces the discontinuity, but suffers from the thermal problems previously mentioned. At high speeds thermal dissipation is essentially a given. In addition, the highest speed circuits are fabricated using GaAs. Matching a substrate to the GaAs expansion coefficient is very difficult especially in systems which mix silicon and GaAs. As a result, severe thermal stresses are encountered in solder bump approaches for high speed circuits.

(It should be noted that the subject invention offers specific advantages at high speed because of the highly planar surface. The interconnect resolution results in very close control of line width and therefore close control of characteristic impedance. In addition, prefabricated terminating resistors can be placed between adjacent chips with very little impact on chip to chip spacing. In the subject invention, optimized for high speed, a power delivery system is provided which features direct connection from the power ground plane to the pads of the chip. The space between power and ground is minimized for low inductance and high dielectric constant dielectric material is used to give high capacitance between power and ground.)

Alignment of Chips for Interconnect To Circuit Board

It is necessary to place the chips with sufficient accuracy that, whatever method of interconnect from the chips to the circuit board, the interconnect will land properly both on the pads of the chip and on the interconnect circuitry. In the "chip on board" approach, chips can be die attached with poor alignment. For wire bonding, manual or automatic wire bonding techniques are used which identify the position of the chips and adjust the wire bonding operation to accommodate mispositioning of the chip. In TAB bonding, the mispositioning of the chips is accommodated by the fan out of the tab interconnect. A typical fan out to 10 mils center can accommodate several mils of mispositioning. It should be noted, however, that fan out results in a larger footprint surrounding each chip and therefore reduced interconnect density.

In the overlay approach using adaptive lithography, chip misplacement is accommodated by identifying the position of each chip and adjusting the artwork for each module to accommodate the actual positioning of the chips in that module. This approach requires a computer driven laser scanning system for painting the artwork patterns. In the STD approach, chip alignment is achieved by providing indentations in the substrate which serve as alignment guides to which two edges of a chip can be registered and thereby maintain alignment. This technique is unsatisfactory for todays commercially available chips because the saw cut cannot be guaranteed to be within plus or minus 2 mils and therefore, since chip pads in some circuits are 3 mils, severe misregistration between chip pads and artwork can result. In addition, it is extremely difficult to provide highly accurate registration indentation in the most desirable substrates, namely, alumina and aluminum nitride. A further problem associated with alignment of chips is that notwithstanding the accurate placement of chips, they often move or swim during subsequent curing of the die attach material. Further, commercially available die attach equipment can result in an overall misplacement of die on the order of 4 to 10 mils. This degree of mispositioning is acceptable in most "chip on board" approaches and in approaches using adaptive lithography. However, it is not acceptable in "circuit board above chip" approaches which do not use adaptive lithography. (As explained below, the subject invention provides a means for both highly accurate positioning of the chips and a means to prevent the chips from swimming on subsequent cure such that die positioning accuracies of 6 to 8 microns are routinely achieved.)

Flip chip or solder bump bonding systems achieve alignment due to the surface tension associated with the melted solder ball. It is only necessary to place the chip and solder ball within several mils of the final position and surface tension will draw the chip into accurate alignment with the chip pads below.

In addition to XY and rotation alignment, chips must also have their height or Z-axis alignment controlled when used in the "circuit board above chip" configuration. In the overlay approach, this Z-axis height control is achieved by milling the substrate to depths which allow the top surface of the chips to be substantially planar. Because chips from the same lot are not all the same thickness, this requires either custom producing each milled substrate or allowing a reasonably high degree of tolerance on the order of plus or minus several mils for chip height variation. In the STD process, a unique technique is used for controlling the variation in chip height. In this technique, chips are placed on a substrate of aluminum and subsequently swaged under high pressure until the corresponding deformation of the aluminum sets all chips at the same height. Today, chips with sub- micron geometries could not undergo the severe stresses involved. In addition, thicknesses of today's chips vary from 10 mils to 30 mils depending on the size of the wafer on which they are fabricated. Finally, the expansion coefficient of aluminum is not well matched to silicon. Chips of substantial size, such as 200 mils on a side or more, can be broken by the differential expansion. Obviously, the technique would not work using alumina or aluminum nitride or even silicon since these materials cannot be deformed. (In the subject invention, a method is disclosed for thinning chips to an extremely well controlled thickness such that all chips can be mounted on a perfectly flat substrate with the result that the top surfaces of all the chips are extremely planar. This technique allows the use of commercially available chips with substantial differences in thickness.)

Reliability

It is possible to provide highly reliable interconnect in any of the prior art technologies by properly selecting materials and processes used. The main sources of unreliability relate to the method of interconnecting the chips to the circuit board. "Chip on board" technologies must make a connection from the chip to the circuit board which is different than the technologies used for interconnecting on the board itself. Specifically wire, flip chip and tab bonding all have interconnect reliabilities which are at least an order of magnitude lower than the interconnect technique used in the integrated circuits themselves. The "circuit board above chip" technique uses the same t