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BACKGROUND AND SUMMARY
The invention relates to monolithic integrated circuits fabricated on low
loss, high resistivity ceramic substrates.
The invention arose during continuing development efforts directed toward
manufacturing advanced and cost effective microwave, millimeter and
electro-optic monolithic integrated circuits (MMICs) capable of high
temperature operation. A new approach adapts a low loss, high resistivity
ceramic substrate onto which is grown high resistivity semi-insulating
buffer layer to transitionally achieve lattice match to a compound
semiconductor's lattice, and enable growth of single crystalline epitaxial
layers to fabricate the MMICs.
The ability to grow active layer single crystal compound semiconductors,
such as GaAs, GaAlAs, InGaAs, Si and InP, and to develop a transitional
buffer layer to achieve lattice match enables a totally new approach to
the development and methods of fabricating MMlCs capable of highest
performance and reliability, and for operation in the microwave to optical
wavelength region.
In a further embodiment, selected buffer layers enable growth of high
temperature superconductors (HTS) on the same ceramic substrate, in
addition to the above noted active layer. Active components such as FETs,
MESFETs, diodes, HEMTs (high electron mobility transistors) and the like
are fabricated in the active layer. Passive components such as low loss
passive networks, filters, delay lines, capacitors, resistors, etc. are
fabricated in the HTS layer.
In a further embodiment, electro-optical devices are fabricated on the same
substrate. The ability to use a ceramic substrate having a low loss
tangent and which is optically transmissive, facilitates the fabrication
of electro-optical transmitters and receivers.
In a further embodiment, the epitaxial growth on the ceramic substrate
eliminates a semi-insulating layer otherwise discretely bonded on the
substrate and subject to fracture problems due to mechanical stresses
caused by mismatch of thermal expansion coefficients. The invention
improves reliability and minimizes the noted fracture problems by
eliminating the discrete bonding of the semi-insulating layer to the
ceramic substrate and by eliminating the semi-insulating layer, which also
improves thermal conductivity of an MMIC by eliminating the poor thermal
conductivity semi-insulating layer. The invention also enables hermetic
sealing of the MMIC by direct eutectic bonding of a metal cover to the
ceramic substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a semiconductor device in accordance with the invention.
FIG. 2 shows a further embodiment of FIG. 1.
FIG. 3 shows an alternate embodiment of FIG. 2.
FIG. 4 shows a further embodiment.
FIG. 5 shows an alternate embodiment of FIG. 4.
FIG. 6 shows a further embodiment.
FIG. 7 shows an alternate embodiment of FIG. 6.
FIG. 8 shows a further embodiment.
FIGS. 9-11 show a processing technique in accordance with the invention.
FIG. 12 shows a further embodiment.
FIGS. 13-22 are graphs showing Raman scattering (RS) and photoreflectance
(PR) data.
FIG. 13 is RS spectrum of sample #1 using 4880 A. The peak at 269 cm.sup.-1
is TO. There is no evidence for LO.
FIG. 14 is RS spectra of GaAs-on-sapphire (bazel plane) sample #1 using the
5145 A line. The sharp peak at 267 cm.sup.-1 is a plasma line and not TO.
FIG. 15 is experimental PR spectrum (solid line) of GaAs-on-sapphire sample
#1 (bazel-plane).
FIG. 16 is RS spectra of GaAs-on-sapphire sample #2 (bazel-plane) using
5145 A.
FIG. 17 is experimental PR spectrum (solid line) of GaAs-on-sapphire sample
#2 (bazel-plane).
FIG. 18 is RS spectra of GaAs-on-sapphire sample #3 (bazel-plane) using
5145 A.
FIG. 19 is experimental PR spectrum (solid line) of GaAs-on-sapphire (bazel
plane) sample #3. The solid line is a lineshape fit.
FIG. 20 is RS spectrum of sample #4 using 4880 A.
FIG. 21 is RS spectra of GaAs-on-sapphire sample #4 (r-plane) using 5145 A.
FIG. 22 is experimental PR spectrum (solid line) of GaAs-on-sapphire
(r-plane) sample #4.
FIG. 23 is lattice constants of semiconductors and IIa fluorides relative
to Si vs. bandgaps of the semiconductors.
DETAILED DESCRIPTION
FIG. 1 shows a semiconductor device 10 including a ceramic substrate 12, a
buffer layer 14 epitaxially grown on substrate 12 and transitionally
matching the lattice of a compound element semiconductor layer, and a
compound element semiconductor layer 16 epitaxially grown on buffer layer
14. Buffer layer 14 is a semiinsulating layer of high resistivity, eg.
greater than about 10.sup.7 ohm-cm. Buffer layer 14 and compound
semiconductor layer 16 are preferably grown by molecular beam epitaxy, to
be described. Buffer layer 14 is single crystalline with ceramic substrate
12 Compound semiconductor layer 16 is single crystalline with buffer layer
14. Buffer layer 14 has an elastically transitional lattice constant
matching at its lower surface the lattice constant of ceramic substrate 12
within a first given range, and matching at its upper surface the lattice
constant of semiconductor layer 16 within a second given range. The first
range is 2% to 40%. The second range is 0.5% to 5%. Buffer layer 14 has a
lattice constant of 3 to 6, and a thickness of 3 microns to 5 microns.
Buffer layer 14 is preferably selected from the group consisting of
Al.sub.2 O.sub.3, ZnS, TiO.sub.2, ThO.sub.2, ZrO.sub.2, BeO, MgAl.sub.2
O.sub.4, AlN, LaAlO.sub.3, LaGaO.sub.3, SrTiO.sub.3, GaInAs, AlInAs,
CaF.sub.2, SrF.sub.2, BaF.sub.2 and InSb, or other oxides or nitrides.
Ceramic substrate 12 is preferably selected from the group consisting of
sapphire, aluminum nitride, silicon carbide, synthetic diamond, and metal
oxides. Compound semiconductor layer 16 is preferably selected from the
group consisting of GaAs, GaAlAs, InGaAs, InP, AlInAs. In a further
embodiment, an interface layer, selected from the group consisting of an
intrinsic layer of silicon and an intrinsic layer of germanium, is between
layers 16 and 14.
Single crystal buffer layer 14 on substrate 12 has a mismatch in lattice
constant relative to substrate 12 resulting in compressive stress, to be
described, such that buffer layer 14 initially has a lattice constant
larger than substrate 12 such that lattice mismatch dislocations are
turned in a direction parallel to the interface between buffer layer 14
and substrate 12 and such that the dislocations remain confined at the
location of the interface. The lattice constant of substrate 12 is about 4
to 5, depending upon the ceramic material chosen. The lattice constant of
semiconductor layer 16 is 5.65 for GaAs. Buffer layer 14 provides
transitional lattice constant matching between substrate 12 and
semiconductor layer 16, for example for Al.sub.2 O.sub.3, alpha is 5.13
and beta is 5.56. Buffer layer 14 is provided by progressively growing a
series of buffer layers of increasing lattice constant, each turning
mismatch dislocations toward substrate 12. This technique involves
sequentially growing multiple thin buffer layers and transitionally
changing the lattice constant of the buffer layers to establish a
different lattice constant at the top sequentially grown buffer layer than
at the bottom buffer layer. The buffer layers are grown by molecular beam
epitaxy at a temperature of about 300.degree. C. to 700.degree. C. During
about the first 100 angstroms of growth, the temperature is periodically
increased to 900.degree. C. to 1,000.degree. C. to anneal monolayers as
they are formed, to minimize discontinuities. The temperature is increased
to the 900.degree.-1,000.degree. C. range every 10 to 20 angstroms of
growth of the buffer layer. The temperature is ramped up from the
300.degree.-700.degree. C. range to the 900.degree.-1,000.degree. C.
range, and then ramped back down to the 300.degree.-700.degree. C. range.
The length of the up ramp is 10 to 30 seconds, and the temperature is held
in the upper range of 900.degree.-1,000.degree. C. for 1 to 5 seconds, and
the length of the down ramp is 10-30 seconds.
FIG. 2 illustrates another embodiment and semiconductor processing
technique for depositing a single crystal compound semiconductor layer on
a ceramic substrate. Device 20 in FIG. 2 includes a ceramic substrate 22,
a super-lattice-strained structure 24 of GaInAs and AlInAs layers grown on
the substrate, and a compound element semiconductor layer 26 epitaxially
grown on super-lattice-strained structure 24. First GaInAs layer 28 is
epitaxially grown on substrate 22, and then AlInAs layer 30 is epitaxially
grown on layer 28, and then GaInAs layer 32 is epitaxially grown on layer
30, and then AlInAs layer 34 is epitaxially grown on layer 32, and so on
to a desired number of pairs of GaInAs and AlInAs layers to the uppermost
pair of layers 36 and 38. Compound element semiconductor layer 26 is then
grown epitaxially on uppermost AlInAs layer 38. In one embodiment, each of
the GaInAs and AlInAs layers is grown to a thickness of 10 angstroms to 50
angstroms, and such layers are grown to a total thickness of
super-lattice-strained structure 24 of 3 microns to 5 microns. The lattice
constants of GaInAs and AlInAs are 5.5 and 5.8, respectively, and provide
transitional lattice constant matching between ceramic substrate 22 and
compound semiconductor layer 26.
In another embodiment, FIG. 3, super-lattice-strained structure 24 has a
GaInAs layer 40 grown on ceramic substrate 22. During the growth, the Ga
dopant concentration is gradually decreased and the Al dopant
concentration is gradually increased to gradually transition GaInAs layer
40 through central zone 42 to an upper zone AlInAs layer 44 for epitaxial
growth thereon of compound element semiconductor layer 26.
FIG. 4 shows an alternate embodiment of FIG. 2, including a ceramic
substrate 46, a super-lattice-strained structure 48 of alternating layers
of CaF.sub.2 and SrF.sub.2 epitaxially grown on substrate 46, and a
compound element semiconductor layer 50 epitaxially grown on
super-lattice-strained structure 48. CaF.sub.2 layer 52 is epitaxially
grown on substrate 46, and then SrF.sub.2 layer 54 is epitaxially grown on
layer 52, and then CaF.sub.2 layer 56 is epitaxially grown on layer 54,
and then SrF.sub.2 layer 58 is epitaxially grown on layer 56, and so on to
an upper pair of layers 60 and 62. Compound semiconductor layer 50 is
epitaxially grown on uppermost SrF.sub.2 layer 62. The lattice constants
of CaF.sub.2 and SrF.sub.2 are 5.4 and 5.8, respectively, and provide
transitional lattice constant matching between ceramic substrate 46 and
compound semiconductor layer 50.
In a further embodiment, FIG. 5, super-lattice-strained structure 48
includes CaF.sub.2 layer 64 epitaxially grown on substrate 46. During the
growth, the Ca dopant concentration is gradually decreased and the Sr
dopant concentration is gradually increased to provide a central
transition region at 66, and during continued growth, the Ca dopant
concentration is further decreased and the Sr dopant concentration is
further increased to provide a high Sr dopant concentration layer 68 at an
upper zone and gradually transitioning the CaF.sub.2 layer 64 to the
SrF.sub.2 layer 66.
FIG. 6 shows a further embodiment including a ceramic substrate 70, a
super-lattice-strained structure 72 of sequential layers of CaF.sub.2,
SrF.sub.2 and BaF.sub.2 on substrate 70, and a compound element
semiconductor layer 74 epitaxially grown on super-lattice-strained
structure 72. CaF.sub.2 layer 76 is epitaxially grown on ceramic substrate
70, and SrF.sub.2 layer 78 is epitaxially grown on layer 76, and BaF.sub.2
layer 80 is epitaxially grown on layer 78, and CaF.sub.2 layer 82 is grown
on layer 80, and SrF.sub.2 layer 84 is grown on layer 82, and BaF.sub.2
layer 86 is grown on layer 84, and so on to a desired number of sets of
CaF.sub.2, SrF.sub.2, and BaF.sub.2 layers to the uppermost set of layers
88, 90, 92. Compound semiconductor layer 74 is epitaxially grown on the
uppermost BaF.sub.2 layer 92. The lattice constants of CaF.sub.2,
SrF.sub.2 and BaF.sub.2 are 5.4, 5.8 and 6.2, respectively, and provide
transitional lattice constant matching between ceramic substrate 70 and
compound semiconductor layer 74.
In a further embodiment, FIG. 7, super-lattice-strained structure 72
includes a CaF.sub.2 layer 94 epitaxially grown on ceramic substrate 70.
During such growth, the Ca dopant concentration is gradually decreased and
the Sr dopant concentration is gradually increased to gradually transition
at region 96 the CaF.sub.2 layer to an SrF.sub.2 layer 98, and during
continued growth gradually decreasing Sr dopant concentration and
gradually increasing Ba dopant concentration to gradually transition at
zone 100 the SrF.sub.2 layer 98 to BaF.sub.2 layer 102.
In a prior art group III-V compound element semiconductor monolithic
microwave integrated circuit, MMIC, having integrated circuitry formed in
a group III-V compound element semiconductor layer grown on a group III-V
compound element semi-insulating layer which is discretely bonded on a
ceramic substrate and subject to fracture problems due to mechanical
stresses caused by mismatch of thermal expansion coefficients, the present
invention provides a method and structure for improving reliability and
minimizing fracture problems by eliminating the discrete bonding of the
semi-insulating layer to the ceramic substrate and by eliminating the
semi-insulating layer. Thermal conductivity of the MMIC is also improved
by eliminating the poor thermal conductivity semi-insulating layer. A
buffer layer is grown on the ceramic substrate and transitionally matches
the lattice of the group III-V compound element semiconductor layer. The
compound element semiconductor layer is grown on the buffer layer such
that heat is transferred from the semiconductor layer and the buffer layer
directly to the ceramic substrate, without otherwise having to pass
through a poor thermal conductivity semi-insulating layer. This also
eliminates the additional thickness of a semi-insulating layer to in turn
shorten the thermal conduction path length. This also eliminates the
discrete bonding of the semi-insulating layer to the ceramic substrate The
compound element semiconductor layer is preferably GaAs, GaAlAs, InGaAs,
InP or AlInAs.
In one embodiment, FIG. 8, ceramic substrate 104 has a high resistivity
semi-insulating buffer layer 106 with an active semiconductor layer 108, a
high temperature superconductor (HTS) layer 110, and an optoelectronic
layer 112. Active layer 108 is provided for integration of active
components such as FETs, MESFETs, diodes, HEMTs (high electron mobility
transistors), etc. HTS layer 110 is provided for integration of passive
components such as low loss passive networks, filters, delay lines,
capacitors, resistors, etc. Opto-electronic layer 112 is provided for
integration of opto-electronic integrated circuitry, such as lasers,
photodetectors, etc. In this embodiment, an optically transparent ceramic
substrate 104 and buffer layer 106 is provided such that the
opto-electronic integrated circuitry in layer 112 receives light from
above and/or from below through substrate 104 and buffer layer 106.
FIGS. 9-11 show a processing technique for depositing a single crystal
compound semiconductor active layer on a ceramic substrate for integration
of active components, and a single crystal HTS layer on the same substrate
for integration of passive components. Ceramic substrate 114 has an
LaGaO.sub.3 buffer layer 116 epitaxially grown thereon. An LaAlO.sub.3
buffer layer 118 is epitaxially grown on layer 116. An HTS layer 120,
preferably YBaCuO or TlBaCaCuO, is epitaxially grown on layer 118. A
portion of layer 120 and layer 118 therebelow is etched away to expose a
portion 122 of layer 116, FIG. 10. Active semiconductor layer 124, FIG.
11, preferably GaAs, is epitaxially grown on exposed portion 122 of layer
116. Alternatively, the buffer layer structure 24 of FIGS. 2 or 3 is
epitaxially grown on exposed portion 122 of layer 116, followed by
epitaxial growth of layer 124. Layer 124 provides an active semiconductor
layer for integration of active components as noted above. HTS layer 120
provides a passive layer for integration of passive components as noted
above. YBaCuO and TlBaCaCuO each have a lattice constant of 3.8 for HTS
layer 120. The lattice constants of LaGaO.sub.3 and LaAlO.sub.3 are 5.5
and 3.7, respectively, and provide transitional lattice constant matching
between ceramic substrate 114 and HTS layer 120.
FIG. 12 shows a further embodiment of FIGS. 1 and 8 including a metal cover
126 having a first portion 128 over layers 108, 110, 112, and a second
outer portion 130 engaging ceramic substrate 104. Cover 126 and ceramic
substrate 104 are pre-oxidized and then heated, or are heated in an
oxidizing atmosphere, to form a eutectic which wets substrate 104. Cover
126 and substrate 104 are then cooled, with cover portion 130 directly
bonded to substrate 104. This provides desirable hermetic sealing. Direct
eutectic bonding is known in the art, and further reference may be had to
U.S. Pat. Nos. 3,744,120, 3,766,634, 3,854,892, 3,911,553, 3,993,411,
3,994,430, and 4,129,243, incorporated herein by reference.
As known in the art, in the development of MMICs to date, the semiconductor
material of choice has been group III-V compounds, preferably GaAs and
InP. The present invention provides new methods and structures for bonding
group III-V compound element semiconductor layers to the surfaces of
ceramics, including metal oxide substrates. A low temperature,
impurity-free technique is provided for depositing GaAs onto ceramic. The
low temperature method prevents diffusion problems otherwise associated
with high temperature material deposition techniques. A significant
advantage of the present invention is an increase in thermal conductivity
due to a reduction in thickness of the GaAs, particularly elimination of
the semi-insulating layer portion thereof, which has poor thermal
conductivity. Another advantage is the elimination of the need for epoxy
or solder bonding to a chip carrier which can result in chip fracture of
high powered devices due to mechanical stresses caused by mismatched
thermal expansion coefficients. Another advantage is the hermetic sealing
enabled by the invention in accordance with known direct eutectic bonding
techniques.
As known in the art, compound element semiconductors and their
heterojunctions are desirable because they yield high speed, high
frequency transistors. Early research concentrated on the growth of
heterojunctions using lattice matched semiconductor crystals. The need for
lattice matching had been assumed critical to avoid dislocations and other
electrically active imperfections. However, it has been found that
mismatched materials can be grown that are device quality without
performance degradation due to dislocations. Hence, the range of materials
and their heterojunctions that can be potentially useful is much wider
with the use of lattice mismatched semiconductors, FIG. 23. Many
electronic devices will exhibit comparable or superior performance through
the use of materials which are not matched to the host substrate. For
example, the use of Ga.sub..47 In.sub..53 As/Al.sub..48 In.sub..52 As
grown 4% mismatched to GaAs for the modulation doped field effect
transistor has been demonstrated to have comparable performance to the
growth of this structure lattice matched to InP, "A High Performance 0.12
.mu.m T-Shape Gate Ga.sub.0.5 In.sub.0.5 As/Al.sub.0.5 In.sub.0.5 As
MODFET Grown by MBE Lattices Mismatched on A GaAs Substrate", Y.K. Chen et
al, IEDM 431-434 (Dec. 1986), and "0.1-.mu.m Gate Al.sub.0.5 In.sub.0.5
As/Ga.sub.0.5 In.sub.0.5 As MODFET Fabricated on GaAs Substrates", G.W.
Wang et al, IEEE Trans. Electron Devices 35 (7) 818-823 (1988).
GaAs has many disadvantages as a substrate. It is expensive, brittle
compared to silicon, and a poor thermal conductor. Since most of the
active region of the devices fabricated are found in less than the top 1%
of the final wafer, it would be very desirable to find a replacement for
this substrate. The use of substrates which are not lattice matched to the
epitaxial device structures opens another degree of freedom in choosing
technologies for integration. This opens the door towards the possibility
of choosing materials based on their intrinsic properties and those of
their heterojunctions, rather than on the availability of a suitable
substrate. The strongest candidate for mismatched growth on an optimum
substrate is the growth of GaAs on an insulating substrate with good
thermal conductivity.
In spite of the 13% lattice mismatch between GaAs and sapphire, their
thermal expansion coefficients are very close in value. This property is
important for device applications. Notwithstanding the lattice mismatch,
single crystal GaAs was grown on sapphire substrates. Samples were
evaluated using Raman scattering (RS) and photoreflectance (PR). The RS
and PR data is shown in FIGS. 13-22. The polarization selection rules of
the RS indicated that sample #1, FIGS. 13-15, (rapidly quenched from heat
treatment) has a (110) orientation, while samples #2, 3 and 4, FIGS. 16-7,
18-19, and 20-22, respectively, (slowly down-ramped from heat treatment)
have the (111) configuration. Epitaxial layers grown at 400.degree. C.
were specular and defect free. However, if substrate temperatures were
raised to the standard GaAs growth temperature of 600.degree. C., surfaces
were quite hazy. A high temperature outgas, several arsenic surface
priming steps and superlattice of InAs/GaAs were used preceding the GaAs
growth sequence. Growth was initiated at low temperature (400.degree. C.)
at a slow growth rate (0.2 .mu.m/hour) and gradually accelerated to 0.8
.mu.m/hour over 0.6 .mu.m of epitaxy.
Czochralski-grown (0001) (c-plane or bazel-plane) and (01-12) (r-plane)
sapphire substrates were used. The substrates were first degreased in
organic solvents and then lightly etched in H.sub.2 SO.sub.4 and HF. They
were then soaked and rinsed in DI water and blown dry with nitrogen gas.
The substrates were then mounted on indium-free mounting blocks and loaded
into the preparation chamber of the MBE. To reduce surface disorder, the
wafers were heat treated at 800.degree. C. for 5 minutes. Of the four
samples studied, sample #1 was rapidly quenched from the high temperature
heat treatment. Samples #2-#4 had the substrate temperature slowly ramped
to 350.degree. C. This difference in procedure was to have a direct impact
of the crystal orientation of the epitaxial growth that was to follow.
Before the growth initiation, an arsenic prelayer was supplied to the
sapphire surface of all samples.
The growth of GaAs was initiated at low temperature (400.degree. C.) at a
rate of 0.2 .mu.m/hour. A 10 period InAs/GaAs superlattice was used to
initiate the growth at the GaAs/sapphire interface. After 0.2 .mu.m of
growth of GaAs the growth rate was increased to 0.4 .mu.m/hour and an
additional 0.4.mu.m was grown. On the completion of growth of the first
0.6 .mu.m, the growth rate was increased to the standard 0.8 .mu.m/hour
for the remainder of the growth sequence. On samples #1 and #2
(bazel-plane), and #4 (r-plane) the growth temperature was increased to
600.degree. C. after the first 2 .mu.m of growth. Sample #3 (bazel-plane)
was grown at 400.degree. C. for the entire epilayer thickness. The GaAs
epitaxial layer thickness of all samples measured approximately 0.6 .mu.m.
Surface morphology was found to degrade rapidly with the increase in
substrate temperature. Accordingly, the surface of samples #1, #2, and #4
were quite hazy. The morphology of sample # 3 was specular and defect
free.
Raman scattering (RS) was studied from four samples of GaAs/Sapphire grown
by MBE. Samples #1-#3 were grown on bazel-plane substrates. Sample #4 was
grown on r-plane. The measurements were made at 300 K in the
back-scattering geometry using the 5145 A line of an Ar-ion laser. For
sample #1 and #4 measurements were also taken using the 4880A line. The
power was about 700 mW.
Shown in FIGS. 13, 14, 16, 18, 20, 21 are the RS spectra of the samples
(#1-4) in the region of the transverse (TO) and longitudinal (LO) q=O
optical phonons of GaAs. The instrumental resolution was 2 cm.sup.-1. The
positions of these phonons should be 269 cm.sup.-1 and 292 cm.sup.-1.
Since RS is a second order process, there are polarization selection
rules. For example, in backscattering RS for the (100) surface only LO is
allowed, from (110) only TO is allowed while from (111) both TO and LO
should be seen. These selection rules apply for material doped less than
about 1.times.10E17 cm.sup.-3.
In FIG. 14, RS spectra of sample #1 (bazel-plane), using 5145 A, there is a
very narrow peak at 267 cm.sup.-1. While at first glance one might assign
this to the TO peak (269 cm.sup.-1) it is actually a plasma line. In FIG.
13, using 4880 A on the same sample, there is indeed a peak at 269.sup.-1.
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