A compact and fast coder-decoder of the Reed-Solomon type and a reader, which comprises such a coder-decoder. The present invention provides a coder-decoder that includes specific registers that are divided into elementary cells set in series and comprising means of multiplexing and of calculation such that during a cycle of a clock signal the data of two of the registers are shifted from one cell and a calculation operation is carried out for one of the data and it is subsequently possible to exchange simultaneously the data between the two registers.

Operation apparatus for deriving an error position polynomial .GAMMA.(x) and a Forney syndrome polynomial T(x) of a Galois field capable of reducing the required number of Galois field multipliers to one, irrespective of the maximum error correction capacity in a Galois field operation, thereby reducing the chip area and achieving a correct operation. The operation apparatus comprises a storing register for storing result values sequentially inputted therein, a multiplexor for receiving outputs from the storing register and selecting a necessary coefficient therefrom, a first register and a second register for storing a coefficient currently selected by the multiplexor and a coefficient previously selected by the multiplexor, respectively, a multiplier for multiplying a value corresponding to an input erasure position and the coefficient stored in the second register, and an adder for adding a value outputted from the multiplier to the coefficient stored in the first register and inputting the resultant value to the storing register.

A Reed-Solomon decoder receives code sequences of M coefficients having a maximum value N, t of which can be corrected. The Reed-Solomon decoder includes 2t polynomial counters successively receiving the M coefficients of each code sequence, the polynomial counter of rank i (i=0,1 . . . 2t-1), providing the coefficient of the term of degree i of a syndrome polynomial. A circuit provides the coefficients of an error locator polynomial from the coefficients of the syndrome polynomial. Another circuit finds the roots of the error locator polynomial by successively trying values .alpha..sup.1 to .alpha..sup.M. The polynomial counter of rank i is preceded by a multiplier by .alpha..sup.(B+i)(N-M), .alpha..sup.B+i being the i-th root of the code generator polynomial.

Circuitry for detecting and correcting errors in data words occurring in Reed-Solomon coded blocks contains a plurality of stages. One stage constructs syndromes in the data flowing through the blocks. Another stage detects erasures in the syndromes. Another stage applies a Euclid's algorithm with and wherein T.sub.s (x), R.sub.s (x), and Q.sub.s-1 (x) are polynomials representing the position of the error, its value, and a provisional value respectively, and R.sub.s (x) and T.sub.s (x) can be normalized with a minimal coefficient T.sub.s (0)=.delta. such that R(x)=R.sub.s (xi/.delta. and T(x)=T.sub.s (x)/.delta.. Another stage detects error positions X.sub.k and values Y.sub.k by conducting a Chien zero-root search in conjunction with ##EQU1## wherein T'(X.sub.k) is the first derivative of T at a place x.sub.k. Another stage uses the accordingly calculated error positions X.sub.k and values Y.sub.k to correct signal-duration matched data words in a currently occurring Reed-Solomon coded block. when the two counts are equal. An exclusive-OR stage has one input terminal which receives the error value at the top of the fourth stack in accordance with the control signal, another input terminal which receives the signal-duration matched data words, and an output terminal that emits corrected data words.]

A lost data correction circuit has a multiplication unit MLT having one dividing unit DIV performing division based on the Euclidean mutual division method, 4t (t is the number of symbols for which the error can be corrected and 2t is the number of the parity symbols) number of computation units PE and (8t+2) number of registers A and B provided in parallel. In this circuit, as the first stage, the lost data positions U are calculated from the error flags and the syndromes S are calculated from the received code; and then, as the second stage, the lost data position polynomial u and correction syndrome T are simultaneously calculated in .epsilon. steps (.epsilon. is the number of the lost data symbols); as the third stage, the error evaluation polynomial .omega. and error position polynomial .sigma. and the corrected error position polynomial .sigma. thereof are calculated in (2t-.epsilon.) steps; as the fourth stage, the product polynomial U.multidot.X of them is calculated; and as the fifth stage, the error positions are calculated. That is, in this lost data correction circuit, the total error position polynomial and error evaluation polynomial are calculated in two steps.