A tri-property code has been adopted and accordingly combinational and sequential circuits for implementing some arithmetic and logical operations are designed individually then combined into a unit for such operations. Most of the circuits are drawn for the decimal system with general procedures applicable to the other radices.
This application is a continuation of application Ser. No. 07/476,301, filed Feb. 7, 1970 now abandoned, which in turn is a continuation-in-part of application Ser. No. 07/181,034 filed Apr. 13, 1988 now abandoned.
A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive bits comprising a sparse-redundant representation of the integer. A converter converts 1-redundant representations of the integer to the space (1/K)-redundant representations. A process is described to design rows of a multiplier by identifying a distribution of multiplication product groups, and transforming the distribution of multiplication product groups to adders to occupy a highest unoccupied row of the multiplier.
A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive bits comprising a sparse-redundant representation of the integer. A converter converts 1-redundant representations of the integer to the space (1/K)-redundant representations. A process is described to design rows of a multiplier by identifying a distribution of multiplication product groups, and transforming the distribution of multiplication product groups to adders to occupy a highest unoccupied row of the multiplier.
A processor system apparatus and method for determining a square root of a particular value of a square of a parameter for use with an electronic circuit breaker system. The system comprises a signal processor or logic circuit for receiving and using at least one input signal to process and output at least one output signal, wherein the logic circuit is configured to determine a whole root of the square root of a particular value of the square of a parameter, wherein the logic circuit is configured to determine a slope of the square of a parameter bounded by at least a first point and a second point, where the first point corresponds to a first value of the square of a parameter and the second point corresponds to a second value of the square of a parameter, wherein the logic circuit is configured to determine a difference between the particular value of the square of a parameter and a value of a square of the whole root, wherein the logic circuit is configured to determine a fractional part of the square root of a particular value of the square of a parameter using the slope and the difference, wherein the logic circuit is configured to determine the square root by combining the whole root of the square root and the fractional part of the square root, and wherein the logic circuit outputs at least one output signal using the square root.
An apparatus and method for anticipating leading zeros/ones used in normalizing the results of a full adder. The propagate (P), generate (G) and zero (Z) states of the two inputs to the adder are combined in two stages of logic to derive a pair of state outputs L.phi.S and L1S which fully specify by respective bit strings the leading zero and leading one conditions of the output from the adder. The two state bit strings, one representing the leading zero evaluation and the second representing the leading one evaluation, are then compared to determine which one of the two is applicable, correspondingly indicating whether the adder result is a positive or a negative value, and the number of leading bit positions requiring shifted removal during the normalization process. The leading 0/1 anticipator according to the present invention lends itself to high speed and low device count circuit implementations.
