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I claim:
1. A data storage device comprising:
dynamic data storage means, integrated on a single semiconductor chip, for
storing a plurality of multiple bit data words in addressable
predetermined multiple bit word storage locations, said multiple bit word
storage locations requiring refreshing in order to retain data;
addressing circuit means integrated on said single chip for periodically
addressing each of said data bit storage locations;
refresh circuit means, integrated on said single chip and randomly
connectable by said addressing circuit means to each of said multiple bit
word storage locations, for periodically refreshing each of said multiple
bit words in said adjacent storage locations; and
logic means, including data comparator means integrated on said single chip
and connected to said refresh circuit means, for comparing each bit of a
predetermined comparand with each corresponding bit of each said data word
stored in said predetermined word storage locations, whereby each data
word bit addressed by said addressing circuit means can be searched, and
for providing an indication of a match between said bits of said comparand
and the corresponding bits of at least one of said data words.
2. A data storage device comprising:
a plurality of dynamic multiple bit data storage locations integrated on a
single chip of semiconductor material, for storing a respective plurality
of multiple bit data words, each bit of said storage locations requiring
refreshing to retain said bits of said data words;
addressing circuit means integrated on said single chip for periodically
addressing each of said data word bit storage locations;
a data refreshing circuit integrated on said single chip, including a read
amplifier and a write amplifier randomly connectable by said addressing
circuit means to each of said bit storage locations, for periodically
reading and writing each of said plurality of data words to retain said
data words in respective predetermined storage locations; and
data comparator means, integrated on said single chip and connected
intermediate said read amplifier and said write amplifier, for comparing
said plurality of data words with a comparand, whereby each data word bit
addressed by said addressing circuit means can be searched, and for
providing an indication of comparison when said bits of said comparand
match the corresponding bits of at least one of said data words.
3. A dynamic associative data storage device comprising:
dynamic data storage means, integrated on a single semiconductor chip, for
storing multiple bit data words in predetermined multiple bit data word
storage locations, said dynamic data storage means requiring periodic
refreshing in order to retain data;
addressing circuit means integrated on said single chip for periodically
addressing each of said data word bit storage locations;
refresh circuit means, integrated on said single semiconductor chip and
randomly connectable by said addressing circuit means to each of said data
bit storage locations, for periodically refreshing each of said data words
bits in said data word bit storage locations; and
associative data searching means, including data comparator means
integrated on said single chip and connected to said refresh circuit
means, for performing associative searching of said data words addressed
by said addressing circuit means.
4. The data storage device of any one of claims 1, 2 or 3 wherein said
comparator means further comprise means integrated on said single chip for
storing a comparand data word prior to said refresh circuit means
refreshing said data word storage locations.
5. The data storage device of claim 4 including means integrated on said
single chip for storing mask data, and wherein mask data and comparand
data are respectively stored during alternating time periods within a
refresh cycle.
6. The data storage device of any one of claims 1, 2 or 3, wherein said
data comparator means comprise:
a plurality of data comparators;
a corresponding plurality of mask data flip-flops; and
a corresponding plurality of match data flip-flops.
7. The data storage device according to any one of claims 1, 2 or 3,
further comprising parity checking means including means for computing and
comparing the exclusive-or of all bits in each of said addressed data
words before and after a refresh operation, and for providing an
indication of error in parity if no match of parity is found.
8. A dynamic associative memory system comprising:
a plurality of dynamic associative memory circuits, each circuit
comprising:
dynamic data storage means, integrated on a single semiconductor chip, for
storing multiple bit data words in predetermined multiple bit data storage
locations, said dynamic data storage means requiring refreshing in order
to retain data;
addressing circuit means integrated on said single chip for periodically
addressing each of said data bit storage locations;
refresh circuit means, integrated on said single semiconductor material
chip and randomly connectable by said addressing circuit means to each of
said bit storage locations, for periodically refreshing each of said
multiple bit data words in said predetermined storage locations;
associative data searching means, including data comparator means
integrated on said single semiconductor chip and connected to said refresh
circuit means, for performing associative searching of said data words
addressed by said addressing circuit means; and
priority interconnect means for interconnecting said plurality of dynamic
associative memory circuits and for prioritizing the operation of said
memory circuits within said associative memory system.
9. The dynamic associative memory system of claim 8 wherein said priority
interconnect means comprise a priority chain circuit.
10. The dynamic associative memory system of claim 8, wherein said priority
interconnect means comprise a priority tree circuit.
11. The dynamic associative memory system as recited in claim 10, further
comprising:
means for detecting failures in said plurality of dynamic associative
memory circuits; and
means for pruning said priority tree to disconnect from said system all
dynamic associative memory circuits in which failures have been detected.
12. A dynamic associative memory system as defined in claim 11 wherein said
means for detecting failures comprise means for computing and comparing
the EXCLUSIVE-OR of all bits in said word storage locations.
13. A data storage device comprising:
dynamic data storage means, integrated on a single semiconductor chip, for
storing a plurality of data words in predetermined word storage positions,
said dynamic data storage means requiring refreshing in order to retain
data;
addressing circuit means integrated on said single chip for periodically
addressing each word storage position;
refresh circuit means, integrated on said single chip and randomly
connectable by said addressing circuit means to each of said data word
storage locations, for periodically refreshing said dynamic data storage
means, including means for periodically refreshing said data words in said
predetermined storage positions;
logic means, including data comparator means integrated on said single chip
and connected to said refresh circuit means, for comparing a predetermined
comparand with each said data word stored in said predetermined word
storage locations, whereby each data word bit addressed by said addressing
circuit means can be searched, and for providing an indication of a match
between said comparand and at least one of said data words; and
parity checking means including means for logically comparing parity in a
word storage location before and after a refresh operation, and for
providing an indication of error in parity if no match of parity is found.
14. A data storage device as defined in claim 13 wherein said parity
checking means include means for computing and comparing the EXCLUSIVE-OR
of all bits in said word storage location. |
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Claims |
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Description |
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FIELD OF INVENTION
The invention relates to refreshable dynamic associative memory storage
devices.
BACKGROUND OF THE INVENTION
Referring to FIG. 1, a schematic of a typical construction of a dynamic
random access memory (DRAM) is shown. During the write mode, data to be
written into the DRAM is applied to the input and amplified by write
amplifier WR. Switches S2 and S3 are open, switches S1 and S4 are closed,
and capacitor C is either charged or discharged according to the status of
the input data, and amplified by write amplifier WR. During the read mode,
switches S1, S3 and S4 are open, and switch S2 is closed so that the
voltage on capacitor C is compared to a reference voltage Vref by read
amplifier RE. According to the difference determined by read amplifier RE,
either a binary "one" or "zero" is transmitted to the output of the DRAM.
When in the data-hold mode, all the switches S1, S2, S3 and S4 remain open
so that the stored charged remains in capacitor C. However, due to the
unavoidable presence of leakage resistance R, the capacitor charge will
gradually dissipate. To compensate for this, a process called refreshing
must be periodically used in the DRAM. To achieve refreshing, all three
switches S1, S2 and S3 are closed, switch S4 is open, and the binary state
detected by read amplifier RE is amplified by write amplifier WR and
reapplied to storage capacitor C. Switches S3 and S4 thus form a
multiplexer which selects either input data or refresh data for
application to write amplifier WR. The dashed line in FIG. 1 represents
the boundary of an integrated circuit chip. Elements within the dashed
line are typically integrated on a single chip.
In practice, a DRAM includes a great number of storage capacitors C
arranged in matrix or array form along with row decoder and column decoder
circuitry. The storage elements of the array must be periodically
refreshed, and are typically refreshed on a row-by-row basis. The row
decoder and column decoder circuitry, as well as the read amplifiers and
write amplifiers, are typically integrated within the same semiconductor
chip with the individual storage elements of the array. FIG. 2 is a block
diagram of a type HM 511000 dynamic RAM available from Hitachi America,
Ltd., which includes eight 128 k memory cell arrays 10 connected through
read/write amplifiers 11 to I/O bus 12. Individual rows and columns of the
cell arrays 10 are selected by row decoder 13 and column decoder 14, under
control of address data contained on address bus 15 via row address buffer
16 and column address buffer 17, and under control of row access strobe
signal RAS, and column access strobe signal, CAS. Reading and writing is
controlled by read/write input, WE, and serial input and output data is
buffered in I/O buffer 18. Once again, elements within the dashed line in
FIG. 2 are integrated together on a single chip.
When logical operations are required to be performed on data stored in a
DRAM, data must be read from the desired storage elements of the array and
applied to the single-bit serial output of the DRAM for application to
logic circuitry external to the integrated circuit chip. After the logic
function is performed, the result is applied to the single-bit input of
the DRAM for buffering and storage in desired storage elements of the
array. Such operation of a dynamic RAM is found, for example, in
single-instruction-multiple-datastream (SIMD) computers wherein a single
logical operation is performed on a plurality of data elements. Such SIMD
operations may be performed cyclically in order to trade off cost for
speed. During cyclic operation, the same operation is performed in one or
more data cells, and within each data cell, the operation is performed
identically on one or more data words which are processed sequentially.
However, as mentioned above, periodic refreshing of the dynamic RAM is
necessary in order to avoid dissipation of the data indicating charge on
the storage capacitor. This refreshing is generally interleaved with any
logical operations performed on the data, which necessarily limits the
speed at which cyclic logical operations can be performed on data stored
in a dynamic RAM.
SUMMARY OF THE INVENTION
The present invention avoids the drawbacks of the prior art by
incorporating logic circuitry within the refresh circuitry of a dynamic
RAM which allows performance of cyclic logical operations on stored
volatile data, concurrent with the periodic refresh of the volatile data.
Thus, all data being refreshed is processed by a simple logical unit in
the refresh circuit. This combination of refresh with logical operation
eliminates the need for a separate refresh cycle by performing the logical
operation during the refresh cycle, and greatly improves the cyclic
processing speed of logical operations performed on stored data.
The present invention has particular application in data base or
associative systems wherein all stored data is accessed and tested, for
example, when conducting data string searches. In such a data base
searching system, a data comparator is inserted into the refreshing loop,
and is used to compare target data with data being cyclically refreshed in
order to simultaneously perform data refresh and target data searching.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1 and 2 are schematic representations of prior art dynamic random
access memories.
FIG. 3 is a dynamic random access memory employing logic in refresh
circuitry, according to the present invention.
FIG. 4 is a dynamic random access memory employing search logic in the
refresh circuitry, according to the present invention.
FIG. 5 is a block diagram of a 1 megabit dynamic random access memory
employing logic in refresh circuitry according to the present invention.
FIG. 6 is another block diagram of a dynamic random access memory employing
logic in refresh circuitry according to another embodiment of the present
invention.
FIG. 7 is a detailed block diagram of a word cell of FIG. 6.
FIG. 8 is a chain priority circuit usable in the present invention.
FIG. 9 is a priority tree circuit usable in the present invention.
FIG. 10 is a node in a data bus and priority tree usable in the present
invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to FIG. 3, a one megabit volatile memory employing
logic-in-refresh according to the present invention is disclosed. The
memory is organized within the chip as a 512 row, 2048 bit-per-row memory
in which an entire 2048 bit row is read, one after another, in each
refresh cycle. The refresh row unit length might be different from the
length of the associative memory word unit that can be searched or output
as a unit. Either the entire 2048 bit row, or a fraction of the 2048 bit
row, can be considered a single word in an associative memory. For
example, referring to FIG. 3, if an 8-bit byte is chosen as the length of
the associative memory word in a 1 megabit memory, 256 cells 19 result,
each having a 512 word memory array 20, 8-bits-per-word. Herein, a "word"
is a unit of data that is considered by the user as a whole, a "row"
refers to a unit of data read or written as a whole, and a "byte" is that
portion of a row contained in a word.
According to the present invention, each cell 19 includes logic circuitry,
such as comparator 21, to operate on the data as it is sequentially and
cyclically read out, refreshed and written back into memory. During a
refresh operation, a 9-bit counter, either external or internal to the
chip, provides 512 consecutive row addresses, one address per memory
refresh cycle. Thus, all words of each cell 19 of the memory are read in
512 memory refresh cycles and are searched during that time. For one mode
of operation, the bottom byte of each cell 19 is logically linked to the
top byte of the next cell 19 within a single chip by bus 22. In another
mode of operation, each word, as a sequence of 512 bytes, is considered
separately. Elements within the dashed line are integrated together in a
single semiconductor material integrated circuit chip. A plurality of
chips can be cascaded by logically linking the bottom word of the last
cell in one chip to the top of the next cell in the neighboring chip by
bus 23.
The configuration of each cell 19 is shown in more detail in FIG. 4.
Referring to FIG. 4, data stored in each byte can be, for example, ASCII
characters in text streams, which are each 7 bits wide together with a
mark bit which is the 8th bit. Initially, all mark bits are cleared, and
are subsequently set and cleared to mark the results of a search. Each
byte is sequentially read by the 8-bit wide read amplifier, RE, and the 7
data bits are applied to comparator 21 where the read 7-bit byte is
compared with the 7-bit comparand stored in comparand register 24. A
comparand is loaded into comparand register 24 through I/O bus 12.
The output of read amplifier, RE, is also applied to multiplexer 25 along
with data from I/O buffer 18 through I/O bus 12. The output of multiplexer
25 is applied to 8-bit write amplifier, WR, along with the single-bit
(mark bit) output of comparator 21. Read amplifier, RE, is also connected
to I/O bus 12 in a known manner through tri-state buffers, or the like, to
enable outputting of data. Thus, according to the present invention,
comparator 21 and comparand register 24 are added to the preexisting
refresh circuitry of a DRAM illustrated schematically in FIG. 1 (note that
switches S3 and S4 illustrate the function of multiplexer 25). All
components are integrated on the same semiconductor material integrated
circuit chip.
In operation, to search-and-mark byte, a byte-wide comparand is
simultaneously broadcast to all cells 19, and stored in respective
comparand registers 24. Then, the 512 bytes in memory array 20 of each
cell 19 are each cyclically read, refreshed and rewritten. The 8th bit of
each byte stores the result of any match with the comparand in comparand
register 24. The results of the match are stored in 8th bit of the next
byte in memory array 20 adjacent and below the one that the comparand
matches. This is repeated for all 512 bytes in each cell 19. The result of
a search on the last byte of a cell is effectively stored in the first
byte of the adjacent cell through bus 22.
If all mark bits are cleared, and the comparand searches for a 7-bit
character and a zero as the 8th bit, an unconstrained search for a
character is done. If the comparand searches for a character and a 1 in
the 8th bit, a search for the character will then match the comparand only
if the previous byte stored in memory array 20 matched the previous
comparand searched. Thus, a string of characters can be searched for, one
character in each successive refresh operation.
A variation of this operation is to continue to mark bytes in memory until
a match is found. In this variation, once the 8th bit (mark bit) of a byte
has been set, as bytes continue to rotate through the refresh circuitry,
the 8th bit of all subsequent bytes are set until a match for the next
comparand (for example, an end-of-text character) is found. This variation
is used to mark the remainder of a target string of characters, once a
character within the target string is found, and facilitates output of or
rewriting the target string.
The output of the result of a search from a single cell can simply be read
out as the character into I/O buffer 18 if the 8th bit is set. As a byte
passes the refresh logic, if the 8th bit is set, the byte is presented by
read amplifier, RE, to I/O buffer 18, and the 8th bit will then be
cleared. In a multiple cell system, if two cells have the 8th bit set in
the same word in each cell, a priority circuit connected to the cells will
prevent all but one of the outputs from feeding I/O buffer 18, and
clearing the 8th bit. Only one byte will be output at a time, and
remaining bytes will be output in later refresh cycles.
After power is applied, a means to fill memory with identical bytes is used
to empty the memory. To fill an empty memory with a string of characters,
a ripple priority mechanism can be used to modify the basic search and
match mechanism so that only the first byte that satisfies the search part
is modified, but no other bytes that satisfy the search are altered.
Within a single cell, a flip-flop is set as the bytes in the cell are
being searched, and is cleared after a successful search is detected. The
byte is modified in a successful search only if the flop-flop output is 1.
One byte can be written in each refresh cycle by this means. In a multiple
cell system, a ripple priority circuit is also used between cells. The
priority circuit causes all flip-flops except the flip-flop in the prior
cell to be cleared. This prioritized context-addressing mechanism is
needed to fill memory with different data in each byte.
The above-disclosed additional search logic can be easily implemented in
existing dynamic random access memories by using preexisting memory cells,
row decoders, read amplifiers, write amplifiers and multiplexers but
removing the column decoders and inserting search logic including the
comparator and comparand register into the read/write circuits. If this is
done, for example in the Hitachi HM511000 (a 1 megabit DRAM), the entire
memory can be read, searched and rewritten in approximately 60
microseconds (the time required to refresh the entire memory). Such a
memory is shown in FIG. 5 and illustrates placement of search logic 26. If
a system incorporates a number of memory chips, and a string of characters
is searched, the time required to search all data in memory will remain 60
microseconds per character searched.
Although content search and update, input and output are the logical
operations herein disclosed, it will be understood that other logical
techniques can also be implemented. For example, the various techniques
used for searching and updating a data base, such a relational data base,
as disclosed in "Architectural Features of CASSM; A Context Addressed
Segment Sequential Memory," Proc. 5th ISCA, pp 31-38, April 1978, authored
by the present inventor, and related work on the CASSM system cited in
that paper, can be implemented. Other modifications, additions or
deletions can also be made without departing from the scope of the
invention. For example, the present invention is equally applicable to
memories, only a portion of which is dynamic memory.
The invention thus allows associative searching of a dynamic memory
integrated circuit with a redesign of only a small part (removing column
decoders, and adding comparators and comparand registers to the refresh
circuitry) of a preexisting chip memory. This results in low development
cost, little if any increase in manufacturing cost, and utilization of
existing DRAM facilities without the need for extensive retooling. Use of
the invention will allow associative searching of very large data bases
stored entirely in fast dynamic memory with very little increase in cost
over an unmodified dynamic random access memory.
FIGS. 6 and 7 illustrate the organization of a semiconductor chip
incorporating another embodiment of the present invention. As mentioned
above, it is important to only slightly modify the architecture of an
existing DRAM chip (FIG. 1), keeping the memory array in tact, so that the
cost of modifying the design of an existing DRAM chip to produce the
present invention will be small relative to the cost of designing a full
chip.
Referring to FIG. 6, in a refresh operation, one column is refreshed
sequentially, one bit after another, using one sense amplifier. The data
in the column, stored in column cells 27, are collected together in groups
of four pairs of column cells each to form word cells 28. Thirty-two word
cells are arranged to within a pair of existing DRAM subarrays 29, and the
chip includes eight pairs 29 of DRAM subarrays. Thus, in a one megabit
memory, each column cell includes 512 bits.
As explained above, in a refresh operation, one column is refreshed
sequentially, one bit after another, by one sense amplifier. For
simplicity, as shown in FIG. 6, the eight column cells 27 forming each
word cell 28 can be considered as four columns in each of two neighboring
DRAM subarrays, thereby forming the four-column two-row rectangle shown to
read or write one byte at a time. Of course, any number of column cells
per word cell can be used. Connecting each of the column cells is a data
bus 31.
Referring to FIG. 7, a detailed block diagram of a word cell used in FIG. 6
is shown. In FIG. 7, eight identically configured column cells 27 are
presented. For clarity, only the upper left column cell 27 in FIG. 7 is
described. However, it is understood that each of the other seven column
cells in FIG. 7 are configured identically. Each column cell 27 includes a
mask flip-flop 32 including storage capacitor 33 which stores a mask bit
for each refresh cycle. Also included in each column cell 27 is a physical
512 bit memory subarray 34 and dedicated sense amplifier 36. In this
embodiment, each column cell 27 also includes a four transistor comparator
30. The output of each word cell is commonly connected in a wire-OR
configuration to a dual-rank (master slave) set-clear match flip-flop 37
which includes two NOR gates 38 and 39 whose inputs are set and clear
inputs of flip-flop 37. Capacitor 41 within flip-flop 37 is the slave of
dual-rank flip-flop 37.
As noted earlier, a refresh cycle is a period of time required to refresh
one bit of one column with one sense amplifier, and is performed
simultaneously for each column in the memory. A refresh cycle is divided
into a row address strobe time (TRAS), where row address strobe is
asserted, and a column address strobe time (TCAS), where column address
strobe is asserted. TCAS is distinct from and after TRAS. Also as noted
earlier, a refresh operation is the period of time required to refresh all
bits within a single column.
According to the present invention, during TRAS, a mask is sent on data bus
31 and is stored in mask flip-flop 32, and during TCAS, data is sent on
data line 31. This is directly analogous to the time-multiplexing of row
address and column address in a convention DRAM. In a refresh operation,
the large (4096 bit) data and mask values are time-multiplexed on 8-bit
data bus 31. For example, if in a refresh operation, the data value is a
4096 hexadecimal bit value of the form, for example, 1234 . . . , and the
mask value is a 4096 hexadecimal bit value, for example, 5678 . . . , then
in the first refresh cycle in the refresh operation, hexadecimal 56 is
sent during TRAS, and hexadecimal 12 is sent during TCAS. In the second
refresh cycle of the refresh operation, hexadecimal 78 is sent during
TRAS, and hexadecimal 34 is sent during TCAS, and so forth. In all, 512
pairs of bytes are sent sequentially as they are used to search or write
data as it is being refreshed inside each word cell. In a write step, the
pair of bits sent in the same position in the data and mask bytes during
TCAS and TRAS will be 10 when the comparand value is a 0, 11 when the
comparand value is a 1, and 00 when the comparand value is a don't care.
In a compare step, however, in order to reduce comparator logic, the pair
of bits sent during TCAS and TRAS will be 01 when the comparand value is a
0, 10 when the comparand value is a 1, and 00 when the comparand value is
a don't care.
According to the present invention, when the circuitry of FIG. 7 is added
to the refresh circuitry of a DRAM, an associative memory structure is
presented which allows the associative searching of data within the memory
as it is being refreshed.
Specifically, a No-op instruction which does nothing but refresh the memory
for one refresh operation, is accomplished by amplifying data with sense
amplifier 36 and writing that data back into the memory cell 34 without
modification. No data goes to or from data bus 31.
During a Word Compare instruction, a data and mask value bit is used for
each column, and each column is searched for all words in all memory chips
during one refresh operation. A match bit for a word is set if for each
column that the mask bit is 1, the data bit is the same as the bit in the
word and column. More specifically, for a Word Compare instruction, match
flip-flop 37 is set to 1 at the beginning of the refresh operation. In
each refresh cycle, the mask and data are sent, the left bit being sent
first during TRAS and stored in mask flip-flop 32 in each bit cell, with
the right bit being sent during TCAS. If the word has a 0 and the first
bit is a 1, then match flip-flop 37 is cleared. If the word has a 1 and
the second bit is a 1, then match flip-flop 37 is cleared. The control
signal Compare is asserted at the end of the refresh cycle when comparator
30 has stabilized, in order to clear match flip-flop 37 if a mismatch is
detected. Data in a cell is refreshed during a Word Compare instruction.
During a Word Write instruction, three-input AND gate 42 is utilized. The
mask data stored in mask flip-flop 32, and sensed data are sent during
TCAS and are used to rewrite data in the cell. If in a word cell the Mask
and Match bits are both high, data is rewritten into the cell. Otherwise,
data in the cell is refreshed. During a Word Output instruction, during
TRAS, a high signal is sent on data bus 31 so as to output all bits.
During TCAS, the Word Write instruction is asserted and data from sense
amplifier 36 is applied to data bus 31 and is also refreshed in the cell.
For the next set of instructions, words are considered linearly ordered
(top to bottom) and prioritized (higher words are considered to be of
higher priority). In addition, the first of these instructions take
advantage of the word structure mentioned earlier wherein the most
significant bit in a word is a mark bit distinct from the character bits
of a byte.
During a Character Compare instruction, the master of match flip-flop 37 is
initially set and the Word Compare instruction is executed on the whole
byte to clear match flip-flop 37 if there is a mismatch where the mask
bits are 1. Then, the slave of match flip-flop 37 is written into the mark
bit (high order bit) of the next byte using extra transistor 35 (by
delaying the signal from the slave match flip-flop 37 one refresh cycle
time), and finally, the master of match flip-flop 37 is copied into the
saved flip-flop. Data is refreshed in a Character Compare step.
In a Word Compare Up instruction, the Word Compare instruction is executed
during each refresh cycle of a refresh operation. The contents of the
match bits are then shifted upward one bit logically at the end of the
refresh operation. Similarly, a Word Compare Down instruction executes the
word Compare instruction during each refresh cycle of a refresh operation,
and then, at the end of the refresh operation, the contents of the match
bits are shifted downward one bit logically. A Word Compare Prior
instruction executes the Word Compare instruction during each refresh
cycle of a refresh operation, and then clears the match bits downward from
the first one that is set at the end of the refresh operation.
To execute a Word Output instruction, for the prior word cell having the
match bit set, one refresh operation is used to output one word, and at
the end of each refresh operation, the match bit of the word outputted is
cleared. The Word Output instruction is repeated until all match
flip-flops are cleared. To execute a Word Write instruction, for the prior
word cell having the match bit set, for each refresh operation, a word is
written and the match bit is cleared. The operation is repeated until all
match flip-flops are cleared.
A typical instruction begins with the transmission of an appropriate
instruction code on the data lines during a period of time that the memory
executes a No-op cycle. As mentioned above, during each refresh operation,
512 refresh cycles occur, and the instruction is executed during each of
the refresh cycles.
The memory requires comparand data to be supp | | |
