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Description  |
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FIELD OF THE INVENTION
The invention is a method and system for generating a bordered split screen
display for comparing a digitized film frame with a reference frame. The
system of the invention generates a composite signal from a digital signal
representing a reference image and a digital signal representing a scanned
film image, and generates a bordered split screen display from the
composite signal.
BACKGROUND OF THE INVENTION
Conventional motion picture film comprises frames that are commonly
displayed sequentially at a frame rate of 24 frames per second (24 fps),
30 fps, or some other rate. Required special effects may be embodied in
the displayed film.
Systems (including "telecone" systems) have been developed for converting
motion picture film into video signals. These systems generate a video
signal from motion picture film images by scanning the film frames
sequentially to generate digitized film images. They then convert the
digitized images into a video signal having a standard video frame rate
(25 video frames per second for PAL video, 29.97 fps for NTSC video, or 30
fps for SMPTE-240M high definition video). Each video frame consists of
two fields.
Conventional film scanning systems typically include circuitry for
performing color correction on scanned images in real time (either before
or after the images are digitized). To enable a user to perform color
correction in a convenient manner, some conventional systems of this type
are capable of generating a composite video signal comprising
complementary portions of a color corrected image and a reference image,
for split screen display on a video monitor.
During color correction, the user typically defines a "test" set of color
correction parameters, and the system generates a "test" color corrected
signal by processing one or more scanned film images in accordance with a
color correction algorithm determined by the test set of parameters. The
user then typically refines the test set of parameters to cause the system
to produce a color corrected signal which, when displayed as a "test"
image, has a color appearance matching that of a reference image.
In such a process, a split screen display usefully permits side-by-side
comparison of a reference image with the latest test image.
However, until the present invention, split screen displays of this type
had limited practical benefit. Often, the user could not readily
distinguish between the two picture regions of the split screen display
since the displayed reference and test images often differed only slightly
and subtly in visual appearance.
In some prior art analog color correction systems, the user can define a
window within a single digitized film image (for example, to select a set
of color parameters that are defined by the image portion within the
window). One such system is described in U.S. Pat. No. 4,694,329. In the
system of U.S. Pat. No. 4,694,329, a window (of the type mentioned in this
paragraph) can be surrounded by a border to distinguish the window from
the remaining portion of the displayed single image. However, this type of
conventional color correction system does not generate a composite signal
from two or more digital signals representing two or more different images
(for example, reference and scanned images) and does not generate a
split-screen display having a border between picture areas in which
different images are displayed. Thus, this type of conventional system
does not enable the user conveniently to compare a reference image and a
test image, and conveniently apply reference image color correction
parameters to the test image by entering appropriate commands to the
system.
SUMMARY OF THE INVENTION
The invention is a system and method for generating a bordered split screen
display for comparing a digitized film frame with a reference frame. In
preferred embodiment, the invention includes circuitry for generating a
composite signal from digital signals representing a reference image and a
scanned film image, and for generating a bordered split screen display
from the composite signal.
In one embodiment, the invention is a film scanning system including a
processor for digitally correcting a digital signal representing a
digitized film image (such as by performing digital color correction on
the digital signal). The system also includes field store circuitry for
storing the corrected digital signal (sometimes referred to herein as the
"test" signal) and a digital reference signal representing a reference
image, circuitry for generating a composite signal from the reference
signal and the stored test signal, and circuitry for generating a
composite video signal from the composite signal. In accordance with the
invention, the composite video signal is displayed as a splits screen
composite image having a distinctive border between distinct "test" and
"reference" picture areas.
In a class of preferred embodiments, the invention also includes means for
inserting a graphics cursor signal into the composite signal. When
displayed, the cursor signal overlays a cursor region of the split screen
composite image. The system is designed so that, when the displayed cursor
highlights a region of a displayed composite image, a user may readily
select color correction parameters to match the highlighted region by
entering appropriate commands to the system.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a film to video conversion system embodying
the invention.
FIG. 2 is a block diagram of a portion of the FIG. 1 system.
FIG. 3 is a block diagram of the input processor shown in FIG. 2.
FIG. 4 is a block diagram of an alternative preferred embodiment of the
input processor shown in FIG. 2.
FIG. 5 is block diagram of the digital signal processor shown in FIG. 2.
FIG. 6 is block diagram of the color processor shown in FIG. 5.
FIG. 7 is block diagram of the output processor shown in FIG. 2.
FIG. 8 is block diagram of the control processor shown in FIG. 2.
FIG. 9 is block diagram of the timing unit shown in FIG. 8.
FIG. 10 is a block diagram of a preferred embodiment of a portion of the
output processor of FIG. 7.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
The apparatus of the invention can be embodied in the apparatus disclosed
in each of the following patent applications, each assigned to the
assignee of the present application: "Non-Real-Time Film Scanning System,"
by P. Capitant, D. Hodgson, and V. Perry, filed Aug. 7, 1991, (Ser. No.
07/741,329); "Method and Apparatus for Flare Correction, " by D. Hodgson
and Y. Levy, filed Aug. 19, 1991 (Ser. No. 07/746,928); "Digital Color
Correction System and Method," by P. Capitant, et al., filed Jun. 5, 1991,
(Ser. No. 07,710,704); "Digital Video Color Processor with Anti-Aliasing
Filter," by D. Hodgson, filed Aug. 5, 1991, (Ser. No. 07/740,623)
"Film-to-Video Frame Image Conversion Apparatus and Method for Selectively
Identifying Video Fields and Frames," by P. Capitant, D. Hodgson and V.
Perry, filed May 14, 1991 (Ser. No. 07/699,928); and "Digital Video
Processing System with Mixer Prefilter," by D. Hodgson, filed Jul. 25,
1991, (Ser. No. 07/736,006). The specification of each listed application
is incorporated herein by reference.
We contemplate that the invention may be embodied in a film scanning and
processing system of the type shown in FIGS. 1-9. The system of FIG. 1
includes film scanner 10 and camera processor 12. Film scanner 10
transports motion picture film (color or black and white) past camera
processor 12, which includes a video camera and related analog video
signal processing circuitry. Camera processor 12 images each film frame
adjacent to it, and generates an analog signal representing each film
frame.
In a preferred embodiment, the motion picture film is imaged by camera
processor 12 at a rate of 1.875 frames per second ("1.875 fps"), as
scanner 10 transports the film past camera processor 12 at that rate
(1.875 fps). Camera processor 12 preferably generates analog high
definition video signals, such as analog high definition video signals
having SMPTE240M format.
The analog output of camera processor 12 is supplied to film scanning
processor 14, and is optionally also displayed on monitor 16. Within film
scanning processor 14, the analog video signals from camera processor 12
are digitized, and various digital signal processing operations (to be
discussed in detail below with reference to FIGS. 2-6) are performed
digitally on the digitized video data. Color correction will typically
also be performed by circuitry (to be discussed in detail below with
reference to FIG. 6) within processor 14. Flare correction is also
performed, preferably digitally, by circuitry within processor 14.
Computer 18 interfaces with, and controls processor 14 and device
controller 20. In response to user commands sent from computer input
device 28 to computer 18, computer 18 instructs processor 14 to perform
signal processing operations selected by the user, and computer 18
instructs controller 20 to send user-selected control signals to processor
12, scanner 10, frame storage units 30 and 31, 2.times.2 switch 32, and
video recording and playback unit 34.
In a preferred embodiment, computer 18 is a workstation (such as a NEWS
1850 workstation, available from Sony Corporation) connected by an SCSI
interface to processor 14, computer 18 is connected by an R5232 interface
to controller 20, and computer 18 is connected by an R5422 interface to
processor 12, scanner 10, frame storage units 30 and 31, switch 32, and
video recording and playback unit 34. In one preferred embodiment, units
30 and 31 are Model HDDF500 high definition video frame store units
available from Sony Corporation, and recording and playback unit 34 is a
Model HDD-1000 high definition video recorder available from Sony
Corporation.
Also connected to computer 18 are fixed data storage means 24 (which may be
a hard disk drive) and removable data storage means 26 (which may be a
floppy disk drive), and graphics display 22 (preferably, a high resolution
color graphics display).
Preferably, computer input device 28 includes a touch tablet for finger
selection of menu items and icons displayed on monitor 22, a trackball for
selecting color and image areas displayed on monitor 22, and a keyboard
for entering text, user notes, and processing parameters.
After the digitized video data are processed digitally in processor 14, the
processed data are stored on a frame-by-frame basis in frame stores 30 and
31. Switch 32, under control of controller 20, connects desired ones of
frame stores 30 and 31 to video recording and playback unit 34 and to
waveform monitor 36 and video monitor 38 (which is preferably a high
definition video monitor) To maximize the system's throughput rate, as a
frame of data is read out from one of frame stores 30 and 31, the next
frame of data should simultaneously be written into the other one of frame
stores 30 and 31. In such an operating mode, switch 32 connects
alternating ones of frame stores 30 and 31 to unit 34 (and optionally also
to monitors 36 and 38).
The preferred embodiment of film scanning processor 14 shown in FIG. 2
includes input processor 70 (which receives the analog output of camera
processor 70), digital signal processor 72, output processor 74, and
control processor 76. Input processor 70 digitizes the analog input
signal, performs preliminary corrections on the resulting digitized data,
and supplies the preliminarily processed digitized data to digital signal
processor 2 for color correction. The color corrected data generated in
processor 72 are supplied through output processor 74 to frame stores 30
and 31. Processors 70, 72, and 74 operate under control of control
processor 76, which in turn receives instructions from computer 18 over an
SCSI interface.
In one class of embodiments, control processor 76 generates a
synchronization signal for reading out (discharging) an image sensor means
within camera processor 12. Preferably, the image sensor means is read out
at a low rate (such as 1.875 fps) in response to a correspondingly low
rate synchronization signal ("slow sync`) from processor 76.
A preferred embodiment of input processor 70 is shown in FIG. 3. The analog
input signal supplied to processor 70 consists of frames, each comprising
2200.times.1125 pixels. There are 2200 pixels per line, including 1920
active video pixels, and 280 pixels which comprise the horizontal blanking
interval. Each frame consists of 1125 lines, including lines comprising an
even field and an odd field, and ninety lines comprising a vertical
blanking interval. The vertical blanking intervals contain synchronization
information.
The analog input signal is supplied from camera processor 12 (preferably
over a 75 ohm coax cable) to filter/amplifier circuit 100. Circuit 100
includes an amplifier for amplifying the analog input signal, circuitry
for separating the sync and video portions of the input signal, and a low
pass filter for filtering the video portion of the input signal to enhance
resolution during digitization. In one embodiment, the cutoff frequency of
the low pass filter within circuit 100 is about 7.5 MHz, with the filter
having a flat frequency response from 0 to 7.5 MHz, and the frequency
response of the filter declining in a steep slope from 7.5 MHz to 9.3 MHz.
The amplified, low-pass-filtered analog output from filter 100 is digitized
in analog-to-digital conversion circuit 102. In a preferred embodiment,
circuit 102 implements 10-bit quantization, in which case the digital data
generated by circuit 102 will comprise ten parallel digital data streams.
In order to perform 10-bit quantization with relatively simple,
inexpensive analog-to-digital conversion circuitry 102, we prefer that the
output frame rate of camera processor 12 should equal 1.875 fps. When the
output frame rate of camera processor 12 is 1.875 fps, the digital data
emerging from circuit 102 has a data rate of 18.56 MHz (one fourth the
proposed realtime SMPTE-240M high definition digital video clock rate,
74.25 MHz).
The digital video data generated by A/D converter 102 are supplied to green
frame buffer 104, blue frame buffer 106, and red frame buffer 108. The
output of camera processor 12 is time division multiplexed, typically in
the following sequence: two fields of blue data, then two fields of green
data, then two fields of red data, and finally two fields of gray data.
Input control logic circuitry 110 (operating under control of control
processor 76) causes frames of blue digital data ("B.sub.in "), green
digital data ("G.sub.in "), and red digital data ("R.sub.in ") from A-to-D
converter 102 to be written sequentially (on a frame-by-frame basis) into
buffer 106, then into buffer 104, and next into buffer 108. The gray
frames are not normally written into any of buffers 104, 106, and 108.
Blue, green, and red data are written sequentially into buffers 104, 106,
and 108 at the source rate (typically, 1.875 frames per second). Blue,
green, and red data are read out in parallel from buffers 104, 106, and
108 (to produce three parallel data streams, each representing a different
10-bit color channel) at four times the source rate. Thus, each color
channel output from buffers 104, 106, and 108 typically has a frame rate
of 7.5 frames per second (one fourth of the proposed standard SMPTE-240M
digital video frame rate). In order to achieve the described four-fold
increase in frame rate, each bit written into one of buffers 104, 106, and
108, is read out four times from that buffer.
Preferably, each of buffers 104, 106, and 108 is a double buffer, including
a first memory, and a second memory into which data can be written while
data (previously written into the first memory) is read from the first
memory.
As mentioned, the gray frames are not normally written into any of buffers
104, 106, and 108. However, in one class of embodiments, the system has an
optional operating mode in which gray frames are read from input processor
70 at four times the source rate at which they are supplied to processor
70. In one such embodiment, a double gray frame buffer is connected in
parallel with buffers 104, 106, and 108. One memory within the double gray
frame buffer is filled while the other memory therein is read (at four
times the source rate) to processor 72. In another of such embodiments,
the gray frames (rather than the red, green, and blue frames) are read
into one or more of buffers 104, 106, and 108.
In the embodiment of FIG. 4, input processor 70' includes means for
performing shading correction on the digital output of A-to-D converter
102. The shading correction is performed (by circuit 44) before flare
correction is performed (by circuit 47) on the data. In order to perform
shading correction, a set of black and white shading correction signals
must be generated. In contrast with flare correction signals which
compensate for undesired luminance variation due to optical scatter from
frame to frame within each color channel, the shading correction signals
compensate for undesired luminance variation within each frame due to CCD
pattern noise.
The black shading correction signals are preferably generated in the
following manner. Camera processor 12 and input processor 70' (or input
processor 70 of FIG. 2) are operated to generate red, green, and blue
digital data collectively representing a "black" motion picture frame.
This is conveniently accomplished by positioning a lens cap over the lens
of the camera within unit 12, and then operating unit 12 to generate a red
frame of data, a green frame of data, and a blue frame of data. The
average luminance of each frame is then computed. Then, for each frame,
the difference is computed between the luminance of each pixel of the
frame, and the frame's average luminance. These difference signals (scaled
by a pre-selected constant factor) are employed as "red," "green," and
"blue" black shading correction signals (which are added to the
corresponding red, green, and blue frames of data).
White shading correction is performed in a similar manner to black shading
correction, except that the white shading correction signals generated are
employed as multiplicative factor signals (rather than additive correction
signals) to correct the red, green, and blue data streams.
In one class of embodiments, each of frame buffers 104, 106, and 108
includes two memory blocks, each having 1M.times.12 bit capacity. Each
1M.times.12 bit block includes three commercially available 1M.times.4 bit
memory circuits. However, in a preferred embodiment within this class,
only the ten most significant bits of the data are utilized (in the sense
that each pixel read from any of buffers 104, 106, and 108, consists of
ten parallel bits).
A preferred embodiment of an input processor which includes flare
correction, shading correction, and lift variation correction circuitry
will next be described with reference to FIG. 4. Input processor 70' of
FIG. 4 is identical to input processor 70 of FIG. 3 except in the
following respects. The analog input signal is supplied from camera
processor 12 (preferably over a 75 ohm coax cable) to filter/amplifier
circuit 100'. Circuit 100' includes input amplifier 41, sync separation
circuit 42 for separating the horizontal sync, vertical sync, and video
data portions of the input signal, and low pass filter 43 for filtering
the video data portion of the input signal to enhance resolution during
digitization. In one embodiment, the cutoff frequency of low pass filter
43 is about 7.5 MHz, with the filter having a flat frequency response from
0 to 7.5 MHz, and the frequency response of the filter declining in a
steep slope from 7.5 MHz to 9.3 MHz.
The amplified, low-pass-filtered analog data stream output from filter 43
is digitized in analog-to-digital conversion circuit 102. In a preferred
embodiment, the H Sync signal from sync separation circuit 42 is
multiplied by 2200 in phase-locked loop 45 to generate an 18.56 MHz clock
signal, and this 18.56 MHz clock signal is supplied to A-to-D conversion
circuit 102, wherein it is employed to sample the input analog data at a
data rate of 18.56 MHz.
In one operating mode, the digital video data generated by A-to-D converter
102 are supplied directly to green frame buffer 104, blue frame buffer
106, and red frame buffer 108 at the source rate (typically, 1.875 frames
per second). Blue, green, and red data are read out in parallel from
buffers 104, 106, and 108 (to produce three parallel data streams, each
representing a different 10-bit color channel) at four times the source
rate. In order to achieve the described four-fold increase in frame rate,
each bit written into one of buffers 104, 106, and 108, is read out four
times from that buffer.
In a normal operating mode, the digital data from A-to-D converter 102 are
supplied to circuit 44 for shading correction and lift correction. The
corrected red, green, and blue frames output from circuit 44 are written
sequentially into frame buffers 104, 106, and 108. The data streams that
are read out from frame buffers 104, 106, and 108 undergo flare correction
in circuit 47.
In another operating mode of input processor 70', data from test signal
generator 40 (rather than A-to-D converter 102 or correction circuit 44)
are written sequentially into frame buffers 104, 106, and 108.
With reference next to FIG. 5, digital signal processor 72 of FIG. 2
preferably includes a noise reduction circuit 80, which receives the data
streams supplied from frame buffers 104, 106, and 108 of input processor
70 of FIG. 3 (or from flare correction circuit 47 of input processor 70'
of FIG. 4) Noise reduction circuit 80 should include a circuit for
reducing film noise (including film grain noise and scratches) and image
pick-up system noise (including noise relating to the system's optics and
image sensor, as well as associated electronic noise).
As indicated in FIG. 5, the output of noise reduction circuit 80 undergoes
digital color correction in color processor 82, and then digital image
enhancement in image enhancement circuit 84. Preferably, digital signal
processor 72 processes the digital data at an internal processing rate
substantially greater than the scanning rate of camera processor 12. For
example, if the scanning rate is 1.875 fps, the internal processing rate
of processor 72 may desirably be 7.5 fps.
FIG. 6 is a preferred embodiment of color processor 82. The FIG. 6
apparatus is designed to perform a limited type of color transformation,
namely the transformation of the colors of the digitized images generated
by camera processor 14 (as a result of scanning motion picture film) into
colors that would have been generated if the sub | | |
