 |
Description  |
|
|
FIELD OF THE INVENTION
The invention relates to a method and apparatus for high-density memory
array packaging and, more specifically, to a packaging technique having a
circuit board populated on both sides with high-density multichip memory
modules.
BACKGROUND OF THE INVENTION
Advances in modern semiconductor fabrication technologies have impacted the
computer industry and increased the demand for higher speed, lower cost,
and higher density computer systems. Integrated circuit (IC) feature sizes
have been reduced to approximately 1 micron, thereby facilitating an
increase in the scale of circuit integration. Today, the function of a
computer's central processing unit (CPU) can be implemented on a single IC
chip, making possible computer systems that operate at high speeds. In
order to maximize the benefit of such chip level capabilities, the
performance of a memory subsystem must closely match that of the computer
and, more specifically, that of the CFU.
The size and cost of the memory subsystem are major factors in the
price/performance of the computer system. The maximum size of main memory
is generally limited by the addressing capability of the CFU. With the
development of high performance CPU chips, fast and large memory
capabilities are required. However, modern random access memory devices or
RAMs are relatively expensive and may constitute a large percentage of the
total computer system size. Accordingly, high-density memory array
packaging techniques are desired, particularly ones that can utilize
older, less expensive memory chip technology without requiring redesign of
existing computer platforms or cabinets. In some cases, high-density
memory packaging may necessitate redesign of computer platform/cabinet
elements such as the backplane, due to violation of spacing requirements,
or the cooling system, due to an inability to remove heat from the
high-density packages.
Another requirement of main memory is a high speed interconnection between
the RAMS within the main storage subsystem and the CPU chips, since such
off-chip interconnection is a limiting factor in realizing overall system
performance. Memory devices, in general, are bus-oriented, thus making the
interconnection between main memory and the CPU less complex and less
prone to error. Nevertheless, the interchip interconnection strategy of
the RAMs must minimize the contribution of added inductances and stray
capacitances, so as to avoid decreasing memory subsystem performance.
Therefore, in accordance with an aspect of the present invention, a feature
is to provide a new and improved method and apparatus for high-density
memory array packaging which results in a larger and more economical
memory subsystem.
Additionally a feature of the present invention is to provide a
low-profile, thermally managed, high-density memory array package such
that the memory array package may be inserted into a standard computer
backplane without the need for redesign of the backplane or computer
cooling system due to violation of spacing requirements or cooling
specifications.
In accordance with another aspect of the present invention, a feature is to
provide a high-density multichip module interconnecting memory chips on a
multilayer interconnect member to a circuit board, thereby increasing the
performance and density of the memory subsystem.
A further feature of the present invention is to provide a new and improved
method and apparatus for high-density memory array packaging that
integrates less complex, higher yielding and less expensive RAM devices on
an interconnect member.
SUMMARY OF THE INVENTION
The foregoing and other features of the invention are accomplished by
providing a low-profile, high-density package for IC chips, the package
being configured for insertion into a computer backplane having connectors
at a predetermined equally spaced distance between each other. In general,
a first multichip memory module is provided for high density packaging of
IC chips to a circuit board. A first multilayer interconnect member is
constructed having a first side and a second side with the first side
having electrically conductive portions for transmitting and receiving
electrical signals. Low-profile memory chips are then mounted on the first
side in conductive relation with the conductive portions Likewise, a
second multilayer interconnect member is constructed having first and
second sides with the first side having electrically conductive portions
for transmitting and receiving electrical signals. Low-profile memory
chips are mounted on its first side in conductive relation with the
conductive portions. The second side of the second member is thereafter
affixed to the second side of the first member, and low-profile edge clips
are subsequently applied to electrically and mechanically connect the
conductive portions on the first sides of the members to respective
conductive portions on a first surface of a circuit board.
A second multichip memory module is also provided, the second multichip
memory module including first and second multilayer interconnect members
constructed in a manner similar to that described above. Low-profile
memory chips are mounted to the first sides of the members again in a
manner similar to the first multichip memory module described above. The
second sides of the members are joined together and low-profile edge clips
are subsequently applied to electrically and mechanically connect the
conductive portions on the first sides of the members to respective
conductive portions on a second surface of the circuit board. A thermal
management technique that distributes thermal loads is thereafter applied,
thereby creating a high-density package capable of insertion into a
standard computer backplane connector.
In an alternate embodiment of the invention, low-profile memory chips are
mounted to a first and second side of each of at least two interconnect
members, the interconnect members having electrically conductive portions
on their first and second sides. The memory chips are mounted in
conductive relation with the conductive portions of the interconnect
members. Low-profile edge clips are used to mechanically and electrically
connect one of the interconnect members to a first surface of a circuit
board and another of the interconnect members to a second surface of the
circuit board. The thus-assembled package is then capable of insertion
into a standard computer backplane without the need for redesign.
Therefore, in accordance with the purpose of the invention as embodied and
broadly described herein, a low-profile, high-density package apparatus
for integrated circuit chips is provided, the apparatus being configured
for insertion into a computer backplane having a plurality of equally
spaced connectors with a predetermined distance between adjacent ones
thereof. The connectors are configured for receiving a plurality of
adjacent boards. The apparatus comprises (i) a circuit board having
electrically conductive portions on a first surface and a second surface,
the circuit board being further configured for insertion into a connector
of the backplane; (ii) at least two generally planar multichip modules,
each having a first side and a second side, each of the multichip modules
having low-profile, integrated circuit chips mounted to the first and
second sides thereof in conductive relation with electrically conductive
portions on the first and second sides, the low-profile chips being
arranged so as to be activated and deactivated in a pattern that avoids
undue concentration of thermal dissipation, thereby distributing the
thermal loads created by the chips; and (iii) edge connection means for
mechanically connecting one of the at least two multichip modules to
selected points of said conductive portions of the first surface of the
circuit board and another of the at least two multichip modules to
selected points of the conductive portions of the second surface of the
circuit board, with the connection means being configured, dimensioned and
arranged for providing electrical connections from the selected points of
the conductive portions of the circuit board to selected points of the
conductive portions of the first and second sides of the multichip
modules. The thus-assembled, low-profile package is capable of insertion
into the backplane connector without the need of redesign to change the
predetermined distance to accomodate adjacent boards in adjacent
connectors of the backplane.
Other objects, features and advantages of the invention will become
apparent from a reading of the specification when taken in conjunction
with the drawings, in which like reference numerals refer to like elements
in the several views.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a front diagrammatic view of a computer backplane housing a
high-density memory array packaging apparatus according to the invention;
FIG. 2 is an exploded perspective view of the high-density memory array
packaging apparatus used in the backplane of FIG. 1;
FIG. 3 is a front view of an embodiment of a high-density multichip module
used in the memory array packaging apparatus of FIG. 1;
FIG. 4 is a cross-section view of a multilayer interconnect substrate
member used in the high-density multichip module of FIG. 3;
FIG. 5 is a perspective view of an alternate embodiment of the high-density
memory array packaging apparatus according to the invention; and
FIG. 6 is a front view of an alternate embodiment of a high-density
multichip module used in the memory array packaging apparatus of FIG. 5.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to the drawings, and particularly to FIG. 1, there is shown a
front plan view of the interior of a computer backplane 10, which is of
the type installed in a typical computer enclosure or cabinet (not shown).
The backplane 10 is a conventional backplane which includes a plurality of
adjacent, equally spaced edge connector receptacles 11-13 that define, in
part, backplane slots (not shown). Each connector 11-13 is configured for
receiving a circuit board capable of insertion into a backplane slot that
typically measures a distance S in the range of 0.5 to 1.0 inches from the
center of one connector 12 to the center of an adjacent connector 11,13.
Two adjacent circuit boards are shown in FIG. 1 and have been designated
generally by the reference numerals 15,85.
Circuit board 15 (85) is, for example, a printed wiring board of the
conventional type, that is, a generally rectangular, generally planar,
plate-shaped member having an electrical edge connector portion on one
edge thereof (not shown) for insertion into one connector 12 or slot of
the backplane 10. Circuit board 15 consists of an insulative substrate
material having conductive lamina on two major, opposite surfaces 14,16
thereof, with selected portions of the conductive lamina removed to define
conductive paths assembled on the two major surfaces. Circuit board 15 may
also have numerous internal conductive and non-conductive layers
sandwiched between the outer, opposite surfaces 14,16.
Referring now to FIGS. 1 and 2, there is illustrated an embodiment of the
high-density packaging apparatus of the present invention whereby circuit
board 15 is populated on both surfaces 16,14 with surface-mount electronic
components including IC devices or chips 18. Two multichip memory modules
20,21 are also shown in relation thereto. It is to be understood that the
invention is equally applicable to a high-density packaging apparatus that
does not have electronic components surface-mounted directly to the
surfaces 16,14 of circuit board 15, but that is populated with one or more
multichip modules 20,21 on both surfaces 16,14. Yet, the embodiment shown
in FIGS. 1 and 2 will be used to exemplify, among other things, the
thermal management issues associated with such packaging apparatus.
The elements in FIGS. 1 and 2 (and FIGS. 3-6) are somewhat exaggerated and
are not drawn to scale for purposes of ease of depiction and ease of
description. Specifically, no attempt has been made to depict the total
number of chips mounted on the circuit boards or multichip memory modules,
or the scale size of the chips and modules connected to the circuit board,
although the drawings depict the relationship relative to one another.
Mounted on both surfaces 16,14 of circuit board 15 are a plurality of
electronic components including IC chips 18. Each chip 18 may be either a
passive device, or a very large scale integration (VLSI) or ultra large
scale integration (ULSI) active device fabricated with one of a number of
different technologies, such as metal-oxide-semiconductor (MOS). It will
be apparent to those skilled in the art that other technologically similar
IC chips may utilize the teachings and advantages of the inventive
concepts described herein; however, for an embodiment of the present
invention, such devices are either static random access memory (SRAM) or
dynamic RAM (DRAM) chips 18.
The DRAM chips 18 are mounted in conductive relation to the conductive
portions of circuit board 15 using known surface mount techniques and
packages, some examples of which are Very Small Outline Package (VSOP),
Thin Small Outline Package (TSOP), and packages resulting from the Tape
Automated Bonding (TAB) process. These packaging techniques are referred
to as "low-profile" chip packaging technologies, that is, the height of
the packages, which typically measures less than 0.045 inches, is much
smaller than conventional Small Outline J-Lead (SOJ) packages, which
typically measure 0.15 inches. Low-profile chip packaging allows for
double-sided, surface-mounting of components on circuit boards without
violating conventional backplane slot spacing requirements.
In accordance with the teachings of the invention, a low-profile,
high-density memory packaging apparatus is provided, such apparatus
including a first high-density, multichip memory module 20 mounted to the
surface 16 of circuit board 15, the module 20 including chips 24 mounted
to a side 26 and chips 34 mounted to a side 36 thereof. Likewise, a second
high-density, multichip memory module 21, similar to module 20, is mounted
to the surface 14 of circuit board 15, the module 21 including chips 27
mounted to a side 29 and chips 37 mounted to a side 39 thereof. Multichip
modules 20,21 are configured, arranged and positioned in a manner
generally parallel to and in proximate relation to the surfaces 16,14 of
circuit board 15, that is, the distance P between the surfaces 16,14 of
circuit board 15 and the closest portions of modules 20,21 in acing
relation to circuit board 15 is generally equal and in the range of
approximately 0.050-0.100 inches.
Referring only to FIG. 1 at this point, circuit board 85 is shown inserted
into connector 11 of backplane 10 and adjacent to the high-density memory
packaging apparatus of circuit board 15. Adjacent circuit board 85 is
populated with chips 88 and multichip memory modules 80,81 in a manner
similar to that described for circuit board 15, and therefore provides, in
accordance with the teachings of the invention, another high-density
memory packaging apparatus. A feature of the present invention is to
provide a low-profile, high-density memory array package such that the
package can be inserted into standard, conventional computer backplanes
having spacing requirements that typically measure, worst case, a distance
S which is approximately 0.5 inches from the center of one connector to
the center of an adjacent connector. In accordance with this feature, the
relative dimensions of the full populated, high-density memory packages of
circuit boards 15,85 are compatible with the above-stated spacing
requirement and as such allow insertion of both packages into adjacent
connectors of conventional backplanes. In other words, the width R of
circuit board 15 (85) having at least two populated multichip modules
20,21 (81,80) mounted to surfaces 16,14 (86,84) thereof respectively is
approximately 0.360 inches or, stated differently, the distance 0 from the
center of circuit board 15 (85) to furthest point of surface 29 (89) of
multichip module 21 (81) in facing relation to each other is 0.180 inches.
These dimensions are well within the 0.5 inches spacing requirement of
conventional backplanes.
In FIG. 3, the high-density multichip memory module 20 of FIG. 2 is shown,
the multichip memory module 20 including a plurality of multilayer
interconnect members 22,32 having conductive portions 25,35 on sides 26,36
thereof, the conductive portions 25,35 interconnecting a plurality of
chips 24,34, which preferably use silicon as the semiconducting material.
Multilayer interconnect member 22 (32) is a generally rectangular,
generally planar member consisting of a plurality of conductive and
non-conductive layers deposited upon a base of substrate material, as will
be further described. In order to achieve high-density interconnections,
multilayer interconnect member 22 is constructed in a manner different
from traditional printed wiring boards, that is, the multilayer member 22
| | |
