Image reading and processing apparatus

What is claimed is:

1. In an image editing apparatus used with an image reading apparatus which outputs image data of an original in an editorially modified form, an image editing method comprising the steps of:

electronically reading an original at a first magnification ratio;

establishing edit data corresponding to the image data which is produced when the original is read at the first magnification ratio by the image reading apparatus, wherein said edit data is indicative of the output form of the image data and is electrically stored in a memory;

electronically reading the original at a second magnification ratio by the image reading apparatus, said second magnification ratio being different from the first magnification ratio;

fetching said edit data from the memory in synchronization with the reading of the original at the second magnification ratio, and

modifying the image data of the original read at the second magnification ratio on the basis of said edit data fetched from the memory.

2. An image editing method as claimed in claim 1, wherein said reading step comprises the steps of:

optically scanning the original;

converting the light image of the original into electrical data, and

processing the electrical data so as to output digital image data.

3. An image editing method as claimed in claim 2, wherein the magnification ratio is changed optically.

4. In an image editing apparatus used with an image reading apparatus which outputs image data of an original in an editorially modified form, an image editing method comprising the steps of:

reading the original at a first magnification ratio;

establishing edit data corresponding to the image data which is produced when the original is read at a first magnification ratio by the image reading apparatus, wherein said edit data is indicative of the output form of the image data;

storing said edit data in a memory;

reading the original at a second magnification ratio by the image reading apparatus, said second magnification ratio being different from the first magnification ratio;

fetching said edit data from the memory at the speed decided based on the second magnification ratio, and

modifying the image data of the original read at the second magnification ratio of the basis of said edit data fetched from the memory.

5. An image editing method as claimed in claim 4, wherein said reading step comprises the steps of:

optically scanning the original;

converting the light image of the original into electrical data, and

processing the electrical data so as to output digital image data.

6. An image editing method as claimed in claim 4, wherein the magnification ratio is changed optically.

7. An image editing method as claimed in claim 4, wherein the image data read at the first magnification ration is stored in an image data memory temporarily, and the image data is fetched from the image data memory in synchronization with fetching the edit data from the memory in order to edit the image data by using the edit data.

8. In an image editing apparatus used with an image reading apparatus which outputs image data of an original in an editorially modified from and has a memory, an image editing method comprising the steps of:

establishing edit data which is indicative of an output form of the image data and is stored in the memory;

setting a magnification ratio to be output from the image reading apparatus;

electronically reading the original by the image reading apparatus to produce image data corresponding to the original;

fetching said edit data from the memory at a speed which is changed on the basis of the set magnification ratio, and

modifying the image data of the original read by the image reading apparatus on the basis of said edit data fetched from the memory.

9. In an image editing apparatus which outputs image data of an original in an editorially modified form with the assistance of a memory, an image editing improvement comprising:

means for establishing edit data for the original when the original is read at a first magnification ratio, wherein said edit data is indicative of the output form of the image data after being modified and is stored in the memory;

means for reading the original at a second magnification ratio different from the first magnification ratio;

means for fetching said edit data from the memory in synchronization with the reading of the original at the second magnification ratio, and

means for editing the image data of the original read at the second magnification ratio on the basis of said edit data fetched from the memory.

10. An image editing apparatus as claimed in claim 9, wherein said means for reading includes:

means for optically scanning the original

means for converting the light image of the original into electrical data, and

means for processing the electrical data so as to output digital image data.

11. An image editing apparatus as claimed in claim 10, wherein the magnification ratio is changed optically.

12. In an image editing apparatus which outputs image data of an original in an editorially modified from, an image editing improvement comprising:

means for reading the original at a first magnification ratio;

means for establishing edit data for the original read at the first magnification ratio, wherein said edit data is indicative of the output form of the image data after being modified and is stored in a memory;

means for reading the original at a second magnification ratio different from the first magnification ratio;

means for fetching said edit data from the memory at a speed corresponding to the second magnification ratio, and

means for editing the image data of the original read at the second magnification ratio on the basis of said edit data fetched from the memory.

13. An image editing apparatus as claimed in claim 12, wherein said reading means mechanism comprises:

means for optically scanning the original;

means for converting the light image of the original into electrical data, and

means for processing the electrical data so as to output digital image data.

14. An image editing apparatus as claimed in claim 12, wherein the magnification ratio is changed optical.

15. An image editing apparatus as claimed in claim 12, wherein the image data read at the first magnification ratio is stored in an image data memory temporarily, and the image data is fetched from the image date memory in synchronization with fetching the edit data from the memory in order to edit the image data by using the edit data.

16. An image reading and processing apparatus comprising:

image data generating means for optically scanning an original image carrying medium to generate image data;

first memory means for storing the image data relative to discrete areas of the image carrying medium;

means for providing attribute data relative to the discrete areas of the image carrying medium for a predetermined image side;

second memory means for storing the attribute data;

means for providing a magnification/reduction ratio signal indication of a magnification/reduction ratio relative to the predetermined image size at which an image of the image carrying medium is to be generated;

means for retrieving the image data from the first memory means in response to the magnification/reduction ratio signal to enable an image reproduction at that ratio, and

means for retrieving the stored attribute data from the second memory means regardless of the specific magnification/reduction ratio and using that attribute data in a signal processing format relative to the discrete area so as to apply the attribute data to an image reproduction at the desired magnification/reduction ratio.

17. An image reading and processing apparatus comprising:

image data generating means for optically scanning an original image carrying medium to generate image data;

first memory means for storing the image data relative to discrete areas of the image carrying medium;

means for providing attribute data relative to the discrete area of the image carrying medium at a predetermined image size;

second memory means for storing the attribute data relative to the predetermined image size;

means for providing a magnification/reduction ratio signal indication of a magnification/reduction ratio relative to the predetermined image size at which an image of the image carrying medium is to be generated at a size other than the predetermined image size;

means for retrieving the image data from the first memory means;

means for retrieving the attribute data from the second memory means, and

means for processing the image data and attribute data in response to the magnification/reduction ratio signal so that the image data is modified on the basis of the attribute data of a predetermined image size so that the same image data is repeatedly output for a magnification ratio and a portion of the image data is output for a reduction ratio.

18. An image reading and processing apparatus as claimed in claim 17, wherein the means for processing includes means for regulating a time period for respectively addressing the first and second memory means in response to the means for providing a magnification/reduction ratio.

Description Submit all comments and votes

FIELD OF THE INVENTION

The present invention relates to an image reading and processing apparatus such as typically a digital color printer and, more particularly, to an image reading and processing apparatus in which images can be reproduced under conditions selected on the basis of "attribute" data representative of the various conditions in which images are to be duplicated or otherwise reproduced from a given original image-carrying medium.

BACKGROUND OF THE INVENTION

There is known and in use a digital printer of the type in which a fraction of the data generated through scanning of an original image can be disabled or inhibited from being output for actual use in reproducing the original image or the dark and light portions of the original image can be inverted to produce a blanked-out image area of a print sheet. These functions of the digital printer are executed on the basis of data stored in an image data storage memory capable of storing image data for the total area of a single page of image-carrying medium.

Thus, an image reading and processing apparatus of the described type has a problem in that the apparatus is required to use a memory device having such a large data storage capacity. An expedient useful for eliminating such a problem will be to use an "attribute" data storage memory for storing the characteristic conditions in which an original image is to be reproduced. An attribute data storage memory of this nature still has a drawback in that the attribute data stored in the memory is prepared on the basis of the image data for a specific magnification/reduction ratio for image reproduction and for this reason, one set of attribute data is required for the reproduction of an image at one magnification/reduction ratio and another set of attribute data is required for the reproduction of the same image at another magnification/reduction ratio.

SUMMARY OF THE INVENTION

Accordingly, it is an important object of the present invention to provide an image reading and processing apparatus in which the attribute data prepared for a particular magnification/reduction ratio can be used for the reproduction at different magnification/reduction ratios.

It is another important object of the present invention to provide an image reading and processing apparatus having an image reading and processing apparatus in which the attribute data once stored into an attribute data storage memory can be used without any modification for the reproduction of an image at any desired magnification/reduction ratio.

In accordance with a first outstanding aspect of the present invention, there is provided an image reading and processing apparatus comprising

a) image data generating means which is operative to optically scan an original image-carrying medium along a predetermined path in a line-by-line manner and, during each cycle of line scanning, generate image data from a line of pixels on the scanned image-carrying medium,

b) means for generating a first address signal and a second address signal,

c) image data memory means for storing the image data for each line of pixels on the scanned image-carrying medium, the image data memory means being responsive to the first address signal for outputting the image data stored therein,

d) an attribute data storage memory having a plurality of addressible memory spaces respectively corresponding to a plurality of scanning areas into which the coverage of the image data generating means is divided, each of the memory spaces having stored therein attribute data designating the conditions in which the image on the image-carrying medium is to be reproduced, the attribute data storage memory being responsive to the second address signal for outputting the attribute data corresponding to the second address signal,

e) data processing means for processing the image data output from the image data memory, the data processing means being operative to process the image data on the basis of the attribute data output from the attribute data storage memory,

f) means for generating a magnification/reduction-ratio signal indicative of a magnification/reduction ratio at which an image on an image-carrying medium is to be reproduced,

g) first timing regulating means responsive to the magnification/reduction-ratio signal for regulating the timings at which the first address signal is to be generated,

h) second timing regulating means responsive to the magnification/reduction-ratio signal for regulating the timings at which the second address signal is to be generated, and

i) control means for controlling each of the first and second timing regulating means.

An image reading and processing apparatus thus constructed and arranged in accordance with the first outstanding aspect of the present invention may further comprise j) means for determining whether both of the first and second timing regulating means are to be operative or only the first regulating means is to be operative with the second regulating means held inoperative.

In accordance with a second outstanding aspect of the present invention, there is provided an image reading and processing apparatus comprising

a) image data generating means which is operative to optically scan an original image-carrying medium along a predetermined path in a line-by-line manner and, during each cycle of line scanning, generate image data from a line of pixels on the scanned image-carrying medium,

b) image data memory means for storing the image data for each line of pixels on the scanned image-carrying medium and outputting the image data stored therein,

c) a first address generator for supplying a data-write address signal to the image data memory means,

d) a second address generator for supplying a data-read address signal to the image data memory means, the second address generator being operative to supply the data-read address signal to the image data memory means at a timing regulated on the basis of data indicative of a magnification/reduction ratio at which an image on an image-carrying medium is to be reproduced,

e) an attribute data storage memory having a plurality of addressible memory spaces respectively corresponding to a plurality of scanning areas into which the coverage of the image data generating means is divided, each of the memory spaces having stored therein attribute data designating the conditions in which the image on the image-carrying medium is to be reproduced, the attribute data storage memory being responsive to an attribute data address signal for outputting the attribute data corresponding to the attribute data address signals,

f) data processing means for processing the image data output from the image data memory, the data processing means being operative to process the image data on the basis of the attribute data output from the attribute data storage memory, and

g) attribute data address supply means for supplying the data-read address signal to the attribute data storage memory as the attribute data address signal.

In an image reading and processing apparatus thus constructed and arranged in accordance with the second outstanding aspect of the present invention, the attribute data address supply means may be operative to supply each of the data-write address signal and the data-read address signal to the attribute data storage memory as the attribute data address signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of an image reading and processing apparatus according to the present invention will be more clearly appreciated from the following description taken in conjunction with the accompanying drawings in which:

FIGS. 1A, 1B and 1C are block diagrams showing the general construction and arrangement of the signal processing system of an image reading and processing apparatus embodying the present invention;

FIG. 2 is a block diagram showing the circuit arrangement of a latch timing generator network which forms part of a data-read address generator included in the signal processing system illustrated in FIGS. 1A to 1C;

FIG. 3 is a timing chart showing the timings at which data-write and data-read address signals and latch timing clock pulses are to be generated responsive to system clock pulses and horizontal scan synchronizing pulses used in the signal processing system illustrated in FIGS. 1A to 1C;

FIG. 4 is a block diagram showing the circuit arrangement of a "Y" data-read address generator provided in the signal processing system illustrated in FIGS. 1A to 1C;

FIG. 5 is a timing chart showing the timings at which a "Y" data-read address signal is to be generated responsive to the horizontal scan synchroniszng pulses used in the signal processing system illustrated in FIGS. 1A to 1C;

FIG. 6 is a plan view showing an example of an original image-carrying medium which may be duplicated in the apparatus embodying the present invention, the image-carrying medium shown having a multi-colored image area surrounded by a white background area;

FIG. 7 is a view similar to FIG. 6 but shows an address map of an attribute data storage memory forming part of the signal processing system of the apparatus embodying the present invention; and

FIG. 8 is a flowchart showing an example of a routine program to be executed by the microprocessor incorporated in the signal processing system illustrated in FIGS. 1A to 1C when an image is to be reproduced with a magnification or reduction ratio.

DESCRIPTION OF THE PREFERRED EMBODIMENT

An image reading and processing apparatus according to the present invention may be provided in any of various forms and may thus be implemented in an image duplicating apparatus, a microfilm reader/printer apparatus or a digital printer apparatus. In which form an image reading and processing apparatus according to the present invention may be provided, there is used an original image-carrying medium which may be a printed or otherwise image-carrying document or a microfilm strip or fiche carrying an image frame of a series of image frames. Such an image reading and processing apparatus ordinarily comprises image data generating means which is operative to optically scan the original image-carrying medium along a predetermined path in a line-by-line manner and, during each cycle of line scanning, generate image data from a line of pixels on the scanned image-carrying medium.

FIGS. 1A, 1B and 1C show a signal processing system of a colored image reading and processing apparatus embodying the present invention. The colored image reading and processing apparatus is used to read images on an original image-carrying medium (not shown) bearing multi-colored images thereon and the image data generating means of the apparatus comprises a source of light which is typically implemented by a white-light illuminating lamp schematically indicated at 10 in FIG. 1B. The original image-carrying medium is held in a predetermined position with respect to the illuminating lamp 10 and is irradiated with a beam of light emanating from the lamp 10. The beam of light incident on the image-carrying medium is reflected therefrom and the resultant beam of light bearing the images picked up from the image-carrying medium is directed to an image sensor 12 which is also held in a predetermined position with respect to the image-carrying medium. The image sensor 12 is typically implemented by three linear arrays of charge-coupled devices (CCD's) arranged in parallel with each other. The three linear arrays of charge-coupled devices are provided in combination with color filter elements for red, green and blue, respectively. The direction in which the charge-coupled devices are arranged in an array is herein referred to as primary or "horizontal" image scanning direction in the apparatus embodying the present invention.

At least one of the image-carrying medium and the illuminating lamp 10 is driven to travel with respect to the other in a direction perpendicular to the horizontal image scanning direction so that image data is to be produced for one line of pixels after another on the image-carrying medium. The direction in which the successive lines of pixels on the image-carrying medium are to be scanned is herein referred to as a secondary or "vertical" image scanning direction in the apparatus embodying the present invention. A device operative to scan an image-carrying medium in these horizontal and vertical image scanning directions is per se well known in the art from, for example, U.S. Pat. No. 4,751,376.

Activated by the incident information-carrying beam, the image sensor 12 produces light intensity signals V.sub.r, V.sub.g and V.sub.b of voltage levels representing the intensities of light of the red, green and blue components, respectively, of the light which has passed through the color filter elements. These voltage signals V.sub.r, V.sub.g and V.sub.b are supplied to a signal processing system comprising first, second and third analog-to-digital converters 14a, 14b and 14c and are thereby converted into corresponding eight-bit digital signals D.sub.r, D.sub.g and D.sub.b, respectively. For this purpose, each of the analog-to-digital converters 14a, 14b and 14c samples the input voltage signal V.sub.r, V.sub.g or V.sub.b at a predetermined frequency and cyclically produces digital output signals D.sub.r, D.sub.g or D.sub.b each consisting of a sequence of eight "0" and "1" bits representative of a numerical value corresponding to the sampled voltage signal. To the analog-to-digital converters 14a, 14b and 14c are applied different reference voltages V.sub.Rr, V.sub.Rg and V.sub.Rb, respectively, from a microprocessor 16 (MPU, FIG. 1B). These reference voltages V.sub.Rr, V.sub.Rg and V.sub.Rb are selected so that the digital output signal D.sub.r, D.sub.g or D.sub.b produced by each of the analog-to-digital converters 14a, 14b and 14c represents a predetermined numerical value for the maximum value of the supplied voltage signal V.sub.r, V.sub.g or V.sub.b.

The digital light intensity signals D.sub.r, D.sub.g and D.sub.b thus output from the analog-to-digital converters 14a, 14b and 14c are supplied through parallel signal lines to first, second and third shading generator circuits 18a, 18b and 18c, respectively, each of which is operative to compensate for the spurious response components which may be contained in the input signal D.sub.r, D.sub.g or D.sub.b. The corrected digital light intensity signals, now denoted D.sub.R, D.sub.G and D.sub.B, are transferred to first, second and third magnification/reduction line memories 20a, 20b and 20c, respectively, which implement image data storage means of an image reading and processing apparatus according to the present invention. On the other hand, the illuminating lamp 10, image sensor 12, analog-to-digital converters 14a, 14b and 14c, and shading generator circuits 18a, 18b and 18c implement image data generating means of an image reading and processing apparatus according to the present invention. Each of the magnification/reduction line memories 20a, 20b and 20c typically consists of a random-access memory (RAM).

Each of the magnification/reduction line memories 20a, 20b and 20c has independently addressable first and second memory sections such as first and second memory sections 22a and 24a forming the first magnification/reduction line memory 20a, first and second memory sections 22b and 24b forming the second magnification/reduction line memory 20b, and first and second memory sections 22c and 24c forming the third magnification/reduction line memory 20c. Each of these memory sections of the magnification/reduction line memories 20a, 20b and 20c has a storage capacity for storing a plurality of bit sequences each representing a numerical value which may be represented by the digital light intensity signal D.sub.R, D.sub.G or D.sub.B. Each of the magnification/reduction line memories 20a, 20b and 20c has data-write address input terminals connected to a data-write address generator 26 so that the data represented by the supplied light intensity signal D.sub.R, D.sub.G or D.sub.B is written into any of the first and second memory sections 22a and 24a, 22b and 24b, or 22c and 24c at an address designated by an address signal ADW supplied from the address generator 26. The data-write address generator 26 is responsive to clock pulses CKA supplied from a clock generator 28 and is enabled to generate a data-write address signal ADW each time a clock pulse CKA is received from the clock generator 28. The data-write address signal ADW thus output from the address generator 26 is incremented in response to the clock pulses CKA so that the data represented by the light intensity signals D.sub.R, D.sub.G and D.sub.B are written into the first memory sections 22a, 22b and 22c of the magnification/reduction line memories 20a, 20b and 20c, respectively.

After the data represented by the light intensity signals D.sub.R, D.sub.G and D.sub.B are thus written into the respective first memory sections of the magnification/reduction line memories, a horizontal scan synchronizing pulse H.sub.sync is output from the clock generator 28. In response to this horizontal scan synchronizing pulse H.sub.sync, each of the first memory sections 22a, 22b and 22c of the magnification/reduction line memories 20a, 20b and 20c is conditioned to operate in a data-read cycle and, in turn, the address signal ADW is supplied to each of the second memory sections 24a, 24b and 24c of the magnification/reduction line memories 20a, 20b and 20c. The data represented by the light intensity signals D.sub.R, D.sub.G and D.sub.B output from the shading generator circuits 18a, 18b and 18c are now written into the second memory sections 24a, 24b and 24c of the magnification/reduction line memories 20a, 20b and 20c, respectively.

Each of the magnification/reduction line memories 20a, 20b and 20c has further data-read address input terminals connected to a data-read address generator 30 which is also responsive to the clock pulses CKA supplied from the clock generator 28 and which is thus enabled to generate an address signal ADR each time a clock pulse CKA is received from the clock generator 28. As the address signal ADW from the address generator 26 is incremented in response to the clock pulses CKA, the data represented by the light intensity signals D.sub.R, D.sub.G and D.sub.B which have been written into the first memory sections 22a, 22b and 22c of the magnification/reduction line memories 20a, 20b and 20c, respectively, are read out from the memory sections 22a, 22b and 22c while data are being written into the second memory sections 24a, 24b and 24c. After the data represented by the light intensity signals D.sub.R, D.sub.G and D.sub.B are all written into the second memory sections 24a, 24b and 24c of the magnification/reduction line memories 20a, 20b and 20c, respectively, the memory sections 24a, 24b and 24c are conditioned to operate in a data-read cycle and, in turn, the first memory sections 22a, 22b and 22c of the magnification/reduction line memories 20a, 20b and 20c are conditioned to operate in a data-write cycle. The data represented by the light intensity signals D.sub.R, D.sub.G and D.sub.B are now written into the first memory sections 22a, 22b and 22c of the magnification/reduction line memories 20a, 20b and 20c, respectively, and concurrently the data which have been written into the second memory sections 24a, 24b and 24c of the magnification/reduction line memories 20a, 20b and 20c, respectively, are read out from the memory sections 24a, 24b and 24c.

In these manners, data-write and data-read modes of operation are established alternately in the first and second memory sections 22a and 24a, 22b and 24b or 22c and 24c of each of the magnification/reduction line memories 20a, 20b and 20c in response to a horizontal scan H.sub.sync from the clock generator 28. While, thus, the data represented by the light intensity signals D.sub.R, D.sub.G and D.sub.B are being written into the first memory sections 22a, 22b and 22c or the second memory sections 24a, 24b and 24c of the magnification/reduction line memories 20a, 20b and 20c, respectively, the data which have been written into the second memory sections 24a, 24b and 24c or the first memory sections 22a, 22b and 22c, respectively, are read out.

The data-read address signal ADR generated by the data-read address generator 28 as above described may be incremented in cycles each corresponding to a predetermined number of clock pulses CKA when a magnification/reduction-ratio signal VR supplied from the microprocessor 16 is indicative of any magnification ratio. The data-read address generator 28 is further operative to generate latch timing clock pulses CKB in cycles which vary with the magnification/reduction-ratio signal VR from the microprocessor 16.

Referring temporarily to FIG. 2, the data-read address generator 30 to generate the data-read address signal ADR as above described has incorporated therein a latch timing generator network 32 which comprises an adder 32a and a latch circuit 32b which is operative to latch an output signal from the adder 32a in response to a clock pulse CKA from the clock generator 28 (FIG. 1A). The adder 32a has one input terminal "A" responsive to the magnification/reduction-ratio signal VR supplied from the microprocessor 16 and another input terminal "B" responsive to an output signal from the latch circuit 32b. The adder 32a further has a carry output terminal "C" from which is to be output latch timing clock pulses CKB.

Assume, now, that the magnification/reduction-ratio signal VR currently supplied to the adder 32a from the microprocessor 16 is indicative of a reduction ratio of, for example, 1:1/n and accordingly there is a signal N/n produced at one input terminal "A" of the adder 32a, wherein N is an integer larger than n and N/n is herein assumed to be equal to 5. In response to the first clock pulse CKA which the latch circuit thereafter receives from the clock generator 28, the latch circuit 32b latches therein the data representative of the numerical value "5" and supplies the data to the other input terminal "B" of the adder 32a. As a consequence, the adder 32a is responsive to the data representing the numerical value "5" at both of its input terminals "A" and "B" and generates data representative of the numerical value "10" as the sum of the two pieces of input data. This newly produced data representative of the numerical value "10" is transferred to and latched into the latch circuit 32b in response to the subsequent clock pulse CKA. In these manners, the adder 32a is enabled to output data incremented by "5" each time a clock pulse CKA is received by the latch circuit 32b. When a carry thereafter occurs in the adder 32a, a latch timing clock pulse CKB is generated and is output through the terminal "C" of the adder 32a.

Assume, on the other hand, that there is a signal N/n' produced at one input terminal "A" of the adder 32a on the basis of the magnification/reduction-ratio signal VR currently supplied to the adder 32a, wherein N/n' is now assumed to be equal to 2. In this instance, the adder 32a is enabled to output data incremented by "2" each time a clock pulse CKA is received by the latch circuit 32b so that carries occur in the adder 32a and accordingly the latch timing clock pulses CKB are generated in longer cycles than in the first case. This means that, if the numerical value by which the output signal from the adder 32a is to be incremented in response to the clock pulse CKA is specified for a prescribed magnification ratio such as typically the 1:1 magnification ratio, the latch timing clock pulses CKB can be output in cycles which are dictated by the magnification/reduction-ratio signal VR supplied from the microprocessor 16 to the adder 32a. The relationship between the latch timing clock pulses CKB and the data-read address signal ADR will be described later.

Turning back to FIGS. 1A, the latch timing clock pulses CKB generated by the data-read address generator 30 as hereinbefore described are supplied to a parallel combination of latch circuits 34a, 34b and 34c which are connected to the magnification/reduction line memories 20a, 20b and 20c, respectively. Each of these latch circuits 34a, 34b and 34c is responsive to a latch timing clock pulse CKB from the data-read address generator 30 and has latched therein the data released from the associated one of the magnification/reduction line memories 20a, 20b and 20c. The data thus latched in the latch circuits 34a, 34b and 34c and representative of the digital light-intensity signals D.sub.R, D.sub.G and D.sub.B, respectively, are then unlatched and supplied to a color data processing control circuit 36 illustrated in FIG. 1C.

The data represe