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BACKGROUND OF THE INVENTION
Programmable controllers are typically connected to industrial equipment such as assembly lines and machine tools to sequentially operate the equipment in accordance with a stored program. In programmable controllers such as those disclosed in
the above cited patents, for example, the control program is stored in a memory and includes instructions which are read out in rapid sequence and executed to examine the condition of selected sensing devices on the controlled equipment, or to energize
or de-energize selected operating devices on the controlled equipment contingent upon the status of one or more of the examined sensing devices.
The processor for these controllers is designed to rapidly execute programmable controller type instructions which in medium to large sized controllers includes not only instructions that manipulated single-bit input and output data, but also
arithmetic instructions, file handling instructions, timers and counters, sequencers and other, more complex instructions. Such instructions have become quite standardized in the industry and they may be directly associated with elements of a ladder
diagram which is easily understood by control engineers. Program panels such as those disclosed in U.S. Pat. Nos. 3,798,612 and 3,813,649 and in U.S. Pat. No. 4,070,702 have been developed to assist the user in developing and editing ladder diagram
type control programs comprised of such programmable controller instructions.
To insure that the programmable controller can respond quickly to change in the status of sensing devices on the controlled system, it is imperative that the controller execute the control program repeatedly at a very high rate. The rate at
which a programmable controller can execute the instructions in its instruction set, as well as the size of the control program, are the primary factors which determine the rate at which the programmable controller can repeatedly execute, or "scan", the
control program.
While ladder diagram control programs ar particularly easy to create and edit for relatively small to medium scale control tasks, they become cumbersome and inefficient to use in large control tasks. Large ladder diagram control programs are
difficult to understand, difficult to trouble shoot, and require a long time to execute.
As manufacturing control became more complex, greater demands were placed on programmable controllers. In addition to operating manufacturing equipment, programmable controllers have been asked to keep track of production data, such as
production quantities, rates and defects, and report that data to a central host computer. Controllers have also been set up to perform other computational tasks which often tied up their processor for relatively long periods of time, delaying the
execution of the manufacturing equipment control program. This delay could result in the controlled equipment not being supervised frequently enough for fail-safe operation. Furthermore, the reporting and computational tasks typically are not as time
critical as the equipment control function.
SUMMARY OF THE INVENTION
A programmable controller is configured to execute several priority levels of program tasks. These tasks include a fault handling routine, different levels of interrupt routines, a complex machine operation control program, and various types of
background routines, such as reporting and computational tasks. These routines and programs are all definable by the user, who is able to write them for the needs of the specific functions being performed by the programmable controller.
The controller provides a means for the user to allocate the amount of processing time which is devoted to the machine operation control program and the amount of time devoted to executing background tasks. This allocation is dependent upon the
time necessary for the user's machine operation control program to adequately govern the machine. Complex time consuming tasks can be executed as background tasks in a time slice manner without adversely interfering with the execution of the control
program.
A general object of the present invention is to provide a programmable controller in which non-time critical tasks may be performed as background operations in a manner which does not adversely impact the primary function of executing a machine
operation control program.
To this end, an object is to enable the user to define how much processing time during a given interval is allotted to handling such background tasks. This enables sufficient time to be devoted to managing the operation of the machinery
controlled by the controller while allocating the maximum permissible amount of time to background tasks for a specific machine control application.
Another object of the invention is to allow the machine operation control program to utilize any unused portion of the processing time allocated to background tasks.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings which illustrate the embodiments of the present invention:
FIG. 1 is a perspective view of a programmable controller which employs the present invention;
FIG. 2 is a schematic block diagram of the programmable controller system shown in FIG. 1;
FIG. 3 is a schematic block diagram of the System Controller for the programmable controller of FIG. 2;
FIG. 4 is a schematic block diagram of a Program Execution Processor of the programmable controller shown in FIG. 2;
FIG. 5 is a schematic block diagram of the random access memory of the Program Execution Processor of FIG. 4;
FIG. 6 is a schematic block diagram of the remote input/output scanner of the FIG. 2 programmable controller;
FIG. 7 is a diagram of the System Controller memory data structure;
FIG. 8 is a diagram of the I/O Scanner memory data structure;
FIG. 9 is a diagram of the Program Execution Processor memory data structure;
FIG. 10 is an exemplary function chart diagram;
FIGS. 11 A, B and C are illustrations of the descriptor file data structures generated from the function chart program of FIG. 10;
FIGS. 12 A and B show the entries in the mailboxes of FIG. 14 for different types of messages;
FIG. 13 is a flow chart of the programmable controller initialization routine;
FIG. 14 is a schematic representation of a portion of the system of FIG. 1 used to describe the communication of messages between modules of the programmable controller;
FIG. 15 depicts a flow chart of the program steps to initiate the sending of a message from one module to another in the programmable controller;
FIGS. 16, 17, 18 and 19 are flow charts of portions of the software for interpreting function chart data and executing user control programs;
FIG. 20 depicts the memory data structure for the task priority queue;
FIG. 21 illustrates the data structure of the portion of the program execution processor memory which stores the task control blocks;
FIG. 22 depicts the memory data structure for the program execution processor housekeeping interrupt jump table;
FIG. 23 is a flowchart of an operating system routine for selecting the highest priority level program to execute;
FIG. 24 is a flowchart of the housekeeping interrupt routine of the program execution processor module's operating system; and
FIG. 25 is a flowchart of the time-slice routine.
DETAILED DESCRIPTION OF THE INVENTION
With initial reference to FIG. 1, a programmable controller 10 of the present invention is housed in a rack 12 which includes a series of slots that receive a plurality of printed circuit board modules. These functional modules connect to a
mother board which extends along the back surface of the rack 12 to provide a backplane 11. The backplane 11 has a plurality of module connectors which are interconnected by a conductive pattern on the backplane. The backplane 11 provides a series of
signal buses to which the modules connect. The rack 12 contains a power supply module 14, a system controller 16, a number of program execution processor modules 18 and a plurality of remote input/output (I/O) scanner modules 20, although only one
scanner module is required. The remaining locations in rack 12 are empty and the slots are covered by blank plates until additional functional modules are to be inserted in these slots. The physical construction of the rack 12 is disclosed in U.S.
Pat. No. 4,716,495, and assigned to the same assignee as the present invention.
Up to four remote I/O scanner modules 20 interface the controller 10 to external remote I/O racks 17 via serial I/O data links, such as link 15. Each remote I/O rack 17 has a plurality of local I/O modules 19 which are coupled to individual
sensors and actuators on the controlled equipment. The local I/O modules 19 may take many forms and may include, for example, D.C. inputs or outputs, A.C. inputs or outputs, analog inputs or outputs, and open or closed loop positioning modules. The
I/O racks 17 and networks 15 employ conventional interface and communication technology. The remote I/O rack 17 also contains an adapter module 19'; such as the one described in U.S. Pat. No. 4,413,319, which controls the transmission of data via the
I/O network 15 between the I/O modules 19 and the scanner modules 20.
The system controller 16 is connected through cable 25 to a programming terminal 24, which is used to load the user programs into the programmable controller and configure its operation, as well as monitor its performance. The terminal 24 is a
personal computer programmed to enable the user to develop the control programs on the terminal, which programs are then downloaded into the programmable controller. Once the programs have been loaded into the programmable controller 10 and its
operation debugged, the terminal 24 may be disconnected from the system controller 16 if further monitoring is not required. The system controller 16 may be also connected via a cable 26 to a local area network 28 over which it may receive data and
programming instructions, as well as issue status information and report data to a host computer. This enables a central host computer or central terminal to program and control the operation of a plurality of programmable controllers on a factory
floor.
Different steps of a function chart program are assigned to various ones of the program execution modules 18. The user control program for each step is stored in the local memory of the corresponding program execution module 18. For example,
the user control program may be a conventional ladder program. Several user control programs may be executed simultaneously on different ones of the program execution modules. At other times a "background task" may be executed on one program execution
module 18 while another module 18 executes a user control program.
During the course of carrying out a user control program, the program execution module 18 reads input status data from the input image tables in one or more of the I/O scanner modules 20. As called for by the program instructions, the program
execution module also writes output state data to the output image table in the I/O scanning module 20 that services the respective output device. Access to the I/O tables is obtained via the rack backplane 11.
When a program execution module completes a function chart step, it sends a command to the program execution module 18 containing the next step to be executed. The command identifies the next step and instructs that program execution module 18
to begin executing it.
Hardware
In order for the data and commands to be transferred among the modules of the programmable controller, the modules are interconnected as shown in FIG. 2.
Each of the blocks in FIG. 2 contains a reference to other Figures of the drawings that contain the details of the component represented by the block. Each module is connected to the rack backplane 11 which consists of separate control, data and
address buses, 21-23 respectively. The control bus 21 consists of a number of separate lines to which a module may connect to depending upon the control signals required for that type of module. The data bus 22 is thirty-two bits wide and the address
bus is 27 bits wide.
In the preferred embodiment, the system controller 16, program execution processor modules 18 and remote I/O scanner modules 20 each includes a removable daughter board containing a local memory for data and operating instructions for that
module. The daughter board contains a battery to sustain the memory when power is removed from the controller. The memory 134 in each remote I/O scanner module contains an I/O image table that indicates the state of each of the sensor devices and the
desired state of each of the controlled actuators connected to the scanner module 20. The system controller's memory 69 contains various segments that store data regarding the system status and configuration as well as information relating to specific
system operations. Each of the processor modules 18 has a random access memory 106 which stores the function chart data, user control programs and their operating variables.
Each of the functional modules of the programmable controller 10 will be described in detail in the following sections.
System Controller
As noted previously, the system controller module 16 provides a communication interface for the programmable controller to external terminals and local area networks. The system controller 16 also performs system housekeeping functions, such as
providing an indication of the system status and supervising access to the backplane 11.
During normal operation of the programmable controller, the system controller takes care of communication with the external devices that are connected to it, such as network 28 and programming terminal 24. The most significant task is
communicating with the terminal 24 to provide information allowing the operator to monitor the system performance and to detect faulty sensors or actuators. Another task supervised by the system controller is the exchange of data with a host computer or
a peer programmable controller via the local area network 28. This enables the host computer to collect statistics from one or a number of programmable controllers regarding their operation. In addition to these functions, the system controller 16
receives all programming changes and supervises updating the program in the corresponding program execution module 1. For example, this includes adding, deleting and changing various rungs of the ladder program.
The system controller as shown schematically in FIG. 3 connects to the backplane buses 21-23 and is divided into three sections (delineated by dashed lines) for backplane interface, processing and communication operations. The backplane
interface section supervises the backplane access for all the rack modules and interfaces the controller module 16 to the backplane 11. The processor section executes a supervisory program for the controller 10. The communication section is primarily
responsible for communicating with external terminal 24 and local area networks, such as LAN 28. Each of the processor and communication sections includes a set of internal buses, communication buses 31-33 and processor buses 61-63 respectively.
Various circuits connected to the communication buses control the interfacing of the system controller 16 to the programming terminal 24 and the local area network 28. The communication buses consist of control bus 31 having a number of
individual control lines running between various components in the communication section, an eight bit wide data bus 32 and a sixteen bit wide address bus 33. The communication section is built around a microprocessor 30, such as the model Z80
manufactured by Zilog, Incorporated. The microprocessor 30 executes machine language instructions which are stored in a read-only memory (ROM) 34. The instructions are fetched from the ROM, decoded and then executed by the microprocessor 30 to carry
out the communication functions. The program controlling these functions is similar to that employed in previous programmable controllers.
A conventional address decoding circuit 36 receives each address issued by the microprocessor 30 and decodes it to produce the proper set of signals on control lines 31. For example, if the microprocessor 30 is accessing the ROM 34, the address
decode circuit 36 will recognize that the address sent by the microprocessor 30 on bus 33 is within the range of addresses at which the ROM is located. Once it has recognized which device in the communications section is to be accessed, the address
decode circuit 36 produces control signals for the device to carry out the access.
Two serial input/output devices, UART 46 and serial input/output controller (SIO) 48, are also connected to the three communication buses 31-33. The UART 46 may be any of several commercially available universal asynchronous receiver/transmitter
integrated circuits. The UART 46 converts the parallel data which is present on the communication data bus 32 into a properly formatted serial signal which is fed to an input/output line driver/receiver 50. The line driver 50 provides output signals
corresponding to any one of several serial signal standards, such as RS232, RS423 or RS422. The serial I/O communication controller 48 may be any of several commercially available integrated circuits which service two synchronous serial communication
channels. The SIO 48 interfaces the communication section of the system controller 16 to local area networks connected to the line drivers 52 and 54, such as network 28 of FIG. 1. The programming terminal 24, shown in FIG. 1, is connected to one of
these line driver 52 or 54.
Also located within the communication section is a random access memory (RAM) 38 for temporary storage of data received from or to be sent to the various external devices connected to the system controller. The RAM 38 may be accessed via address
bus 33 so that data may be written into or read from the memory via bus 32 depending upon enabling signals from control bus 31. RAM 38 incorporates a parity circuit which analyzes each digital byte being stored in the RAM and produces a parity bit using
conventional techniques. This parity bit is employed to check the integrity of the data read from the random access memory 38. A direct memory access (DMA) circuit 42 is provided to enable rapid data exchange between the SIO 48 and the RAM 38 during
the communication process. The DMA circuit 42 allows the SIO 48 to access RAM 38 to store or obtain data which have been received or will be transmitted over their respective external communication channels.
Access to the communication buses 31-33 is controlled by an arbitration circuit 40 which resolves conflicts when several devices request access to these buses at the same time. The arbitration circuit 40 determines which component of the
communication section will have access to the shared buses 31-33. A device seeking the buses sends a request signal to the arbitration circuit 40 via a line of the control bus 31 and the arbitration circuit grants the request to one device at a time by
producing an access signal on another control line for that device.
A counter/timer circuit (CTC) 44 connects to the communication buses 31-33 and to an interrupt terminal on microprocessor 30 in order to process interrupt requests from the other components within the communications section. The CTC 44 is also
configured as a timer to produce an interrupt request to the microprocessor 30 at a given periodic interval, such as every 10 milliseconds, so that various routines may be periodically executed regardless of the task then being performed by
microprocessor 30. In response to an interrupt request from the CTC 44, the microprocessor 30 reads a vector from the CTC 44 directing the microprocessor to the appropriate interrupt service routine stored in ROM 34, such as performing a data I/O
request from either UART 46 or SIO 48.
Referring still to FIG. 3, the processor section is linked together by a set of buses that comprise control lines 61, a sixteen bit data bus 62 and a twenty-three bit address bus 63. Access to these buses is controlled by an arbitration circuit
64 similar to circuit 40 on the communication buses. Two sets of data gates 56 and 58 extend between the communication buses 32 and 33 and processor buses 62 and 63 of the system controller module 16. Specifically, the first set of gates 56 provides an
eight bit bidirectional connection of the communication section data bus 32 to the data bus 62 of the processor section; and the second set of gates 58 connects the two address buses 33 and 63. The data gate 56 consists of two sets of eight individual
tri-state data gates, each set controlling data flow in one direction between the two buses 32 and 62. Only the lower eight lines of the processor data bus 62 are coupled to the eight bit communication section data bus 32. As addressing will only occur
from the processor section to the communication section, address gates 58 consist of one set of sixteen tri-state signal gates coupling the sixteen communication address bus lines 33 to the lower sixteen address lines in the processor section. An
interbus control circuit 60 is connected to control lines 61 and 31 from the processor and the communication sections, respectively, and in response to access request signals from arbitration circuits 40 and 64, the control circuit 60 enables the data
and address buffers 56 and 58.
The processor section is built around a sixteen-bit microprocessor 66, such as a model 68010 manufactured by Motorola Inc., which executes program code stored in read only memory 68. The 68010 microprocessor is essentially a memory mapped device
and does not have any input/output lines directly connected to it. Therefore, its access to other components on the processor bus must be accomplished through issuing addresses on bus 63. The address sent from the microprocessor 66 is decoded in an
address decode circuit 70 to produce the proper control signals for the accessed component. The processor address decoder 70 functions in much the same manner as the communication section address decoder circuit 36. The processor section also contains
an interrupt processor 72 which controls interrupts to the microprocessor 66 and provides the proper instruction address vectors.
A data transfer acknowledge and bus error (DTACK/BERR) circuit 74 is also connected to the processor control bus 61. Circuit 74 responds to signals from the various components in the processor section to acknowledge the completion of a data
transfer and issue bus error signals in the event of improper addressing or failure of data transfer. These signals are acted on by the microprocessor 66 which takes corrective action. The processor section also includes clock circuit 89 that contains
the main system clock and a real time clock. A system status circuit 88 receives input signals related to the status of the entire system 10 and provides an indication of that status.
The main random access memory (RAM) 69 for the system controller 16 is also connected to the processor buses 61-63. The RAM 69 is a static memory containing 393,216 (384K) memory locations each of which is 16 bits wide and serves as the system
memory for the entire controller 10. The system memory 69 can be directly accessed via the backplane 11 by other modules in the system without the intervention of the central processing unit 66 within the system controller.
FIG. 7 illustrates the data structures within the main system memory 69 included in the system controller module 16. The system memory 69 stores separate data files, which contain data for performing specific functions during the operation of
the programmable controller. The data structures include various forms of data such as integers, floating point numbers, ASCII characters and various control structures. The first file 200 is a directory of the other files stored in the system
controller memory 69. The remaining memory is divided into a system status file 201, system data table 202 and a set of system support files 203.
The system status file 201 contains data relating to the configuration of the entire programmable controller 10. Included in this file is information identifying the various user selectable features of the programmable controller that have been
enabled by the system operator. The real time clock data regarding the time of day, month, day and year are also included in this portion of the system memory. Digital words indicating the occurrence and type of various system faults and errors, as
well as pointers indicating the program instruction being executed when the fault occurs are stored within another sub-file of this section. A section of the system status file 201 also lists the number and type of all the active modules on the system
as well as the relative module number and address pointers necessary to access each module. For example, if more than one program processor module 18 or remote I/O scanner module 20 is present in rack 12, the user must assign a unique number via a thumb
wheel on the module to distinguish the various modules of that type. The thumb wheel setting is read by the system controller during initial start-up of the system and stored in this portion of the system status file 201.
The system data table 202 contains data that is shared by more than one module. For example, results of various computations from one program processor module 81 may be stored in this portion of the system memory so that other program processor
modules may readily access the data. Memory space is allocated within the system data table 202 to store the data that was received or that will be transmitted via the various external communication links of the system controller's communication
section. Other modules in the system 10 are directly able to access these storage locations.
The system data table 202 also contains the value of various system counters and variables which are either used by the system controller 16 or which are commonly used by a number of other modules such as program processor modules 18 or the I/O
scanner modules 20. The final sub-file within the system data table 202 is a space allocated for the user defined data for various programs that the user has loaded into the programmable controller.
The final section 203 of the system controller main memory 69 is dedicated to the system support files. These files include the source program information for the function chart program. The programmable controller 10 does not directly execute
the function chart program. However, as will be described later, the function chart is employed during the programming step to generate data which is used to direct the operation of the program execution modules 18. In order to permit the subsequent
editing of these programs, a source version of the function chart must be available for display on the programming terminal. As also will be described hereinafter, the support files 203 contain simultaneous counters for execution of various branches of
the function chart. Although the local memory in each module contains data regarding its status, in some instances these memories do not have a battery to sustain them. In order to retain such volatile information after a power shut-down, the status
information for these modules is replicated in a sub-file of section 203 of the system memory 69.
Communication parameters are also stored in this section 203 for configuring the UART 46 and the serial I/O module 48 within the communication section of the system controller 16. Among other things these parameters include baud rate, word size
and control bits for the serial data signal format. For example, parameters for communicating with the operator terminal 24 are stored in this portion of the system memory. In addition, as noted previously, a number of programmable controllers may be
connected via the local area network 28, in which case, parameters must be provided in each controller instructing them how to communicate over the network.
Referring again to FIG. 3, the processor section of the system controller 16 interfaces with the backplane buses of rack 12 via a plurality of components that are coupled to both sets of buses. Specifically, the backplane data bus 22 is
connected to the processor data bus 62 by a set of bidirectional data transmission gates 78 and the backplane address bus 23 is connected to the processor address bus 63 by another set of bidirectional gates 76. When the system controller 16 seeks to
exercise control over the backplane 11 of the programmable controller 10, a master mode control circuit 81 responds to signals on the control lines of the processor bus 61 and issues the proper control signals over the backplane control bus 21 to access
other modules within the rack 12.
When another module within the rack 12 seeks access to the system controller 16, in order to read the contents of main RAM 69, for example, the system controller becomes subordinate to the control of the backplane 11 by this other module. In
this circumstance, a slave mode control circuit 82 within the system controller 16 responds to the address of the system controller that appears on the backplane address bus 23 and to control signals on the control lines of the backplane bus 21 which
lead from the other module. In response the slave mode control 82 issues signals to transmission gates 76 and 78 enabling the other backplane module to access the system controller 16. In this latter instance, the master mode control circuit 81 is in a
dormant state. The two bus gates 76 and 78 receive enabling control signals from the master or slave mode control circuits 81 and 82 via the lines of control bus 61 depending upon the mode of backplane communication. A backplane arbitration circuit 84
supervises access to the backplane and resolves conflicting requests for access from the modules in the system.
As noted above the system controller module 16 executes programs which control the initialization of the system and communication with external computers. It does not execute the user control programs.
Program Execution Processor
The program execution processor modules 18 store and execute specific user control programs, such as ladder programs. One of these modules is shown schematically in FIG. 4. During this execution the modules 18 read the state of the sensing
devices from input image table in the memory 134 of the various I/O scanner modules 20, and write output data from their memory to the output image tables in the I/O scanner modules. Data is also obtained from the system memory in the system controller
16.
In order to perform these tasks, each processor module 18 has a set of internal buses 91-93 which are coupled to the backplane 11. Specifically the processor module 18 has a thirty-two bit internal data bus 92, a set of control lines 91 and a
sixteen bit address bus 93. These are coupled to the data and address buses of the backplane 11 by respective sets of tri-state, bidirectional transmission gates 94 and 96. The operation of these gates 94 and 96 is governed by an interbus control
circuit 95 coupled to backplane control lines 21 and the module control lines 91. It should be noted that both the internal data bus 92 and the backplane data bus 22 are thirty-two bits wide. Therefore, thirty-two bit data from the processor module 18
can be sent over the backplane as one thirty-two bit word if the recipient module has a thirty-two bit wide data bus. In some processing functions the module 18 operates on sixteen bit data, and in such cases sixteen-bit words are applied to the
backplane 11.
The remaining components of the processor module 18 are connected to the internal buses 91-93. These internal buses are driven by a thirty-two bit microprocessor 98, such as the one sold commercially by Motorola, Inc. as the 68020
microprocessor. The microprocessor 98 has an interrupt port which is coupled to an interrupt interface circuit 99. This interface circuit receives signals from four external interrupt lines connected to terminals on the front of the processor module
18. These external interrupt lines permit devices which sense high priority events to be interfaced directly to the processor module for fast response. Three other interrupt lines on the interface circuit 99 connect to internal circuits within the
processor module 18. One of the internal interrupt input lines receives a pulse every one millisecond derived from the master clock 89 in the system controller 16. The function of this timed interrupt shall be described later. A signal on any of these
external or internal interrupt lines causes the microprocessor 98 to immediately interrupt normal program execution and execute a routine that corresponds to that interrupt line. The user may program the routines for the external interrupts, but the
internal interrupts are serviced by dedicated interrupt service routines in the controller's operating system.
The program execution capability of the processor module 18 is also supported by a floating point co-processor 100, and by a bit co-processor 102. The floating point co-processor 100 is commercially available from Motorola, Inc. as the 6881,
and it is specifically designed to work with the 68020 microprocessor 98. The bit co-processor 102 is a custom integrated circuit for carrying out Boolean logic operations on individual bits of the data words. Bit co-processors have been used in
programmable controllers in the past to execute a set of ladder diagram instructions using hardwired logic as described in U.S. Pat. No. 4,742,443 entitled "Programmable Controller with Function Chart Interpreter".
The three processors 98, 100 and 102 operate in tandem to execute specific types of instructions included in the control program. The microprocessor 98 may begin execution of the control program and when it encounters a floating point arithmetic
function, the floating point co-processor 100 is enabled and the CPU 98 relinquishes the internal buses 91-93 to it. The floating point co-processor 100 takes over the processing function until the arithmetic operation is complete at which time the
microprocessor 98 resumes program execution. If the control program calls for bit processing (i.e. contains an instruction in the set for the bit co-processor 102), the microprocessor immediately relinquishes control to the bit co-processor 102 by
writing the address of the control program instruction into a program counter in the bit co-processor 102. The bit co-processor 102 then removes the microprocessor 98 from the internal buses 91-93 and executes the subsequent control program instructions
until a stop instruction is encountered. At this point the bit co-processor 102 signals the microprocessor 98 via the control bus 91 to resume control of the buses and execution of the control program. Approximately 85-90 percent of a typical "ladder"
type control program may be executed by the bit co-processor 102. The operation of the custom Boolean logic bit co-processor 102 in conjunction with a microprocessor is fully described in U.S. Pat. No. 4,742,443.
The processor module 18 includes a data size acknowledge (DASACK) circuit 108. This circuit provides a two-bit code on two of the control bus lines which indicates the "width" of the data on the data bus 92. As will be described in more detail
below, this data may be a long word consisting of thirty-two bits, a regular sixteen bit word, or a single eight bit byte. This data size information is used by the various module components in this data processing.
The final component of the processor module 18 is a control and status circuit 110 which monitors the status of the processor module and provides proper control signals on various lines of the control bus 91 to enable various components in a
conventional manner.
Both a read only memory (ROM) 104 and a read-write random access memory (RAM) 106 are connected to all three internal buses 91-93 within the processor module 18. The ROM 104 contains 16 bit storage locations for instructions and constants for
the three processors 98, 100, and 102. The RAM 106 provides storage for the operands and the results of the various computations performed by the processor module 18. The control programs to be executed by the module 18 are also contained in its RAM
106.
The details of the RAM memory 106 are shown in FIG. 5. The random access memory 106 is divided into lower and upper banks 112 and 114. Each bank contains a number of storage locations, for example 196,608 (192K) memory addresses. The memory
location in each bank is sixteen bits wide and both banks can be enabled simultaneously to provide storage for thirty-two bit data words. As noted above the width of the data processed by the execution module 18 may be sixteen or thirty-two bits wide.
In order to optimize the storage capacity when sixteen bit words are processed, a transmission gate multiplexer is incorporated into the random access memory 106 to allow separate sixteen bit words to be stored in both the upper and lower memory banks.
Specifically, the multiplexer consists of three sets of tri-state bidirectional transmission gates 116-118, each of which provides bidirectional control of sixteen data lines. The first set of transmission gates 116 couples the sixteen least significant
bits (bits 0-15) of the data bus 92 to the data terminals of the lower memory bank 112. Similarly, the third set of transmission gates 118 couples the sixteen most significant bits (bits 16-31) of the data bus 92 to the data terminals of the upper
memory bank 114. The second set of transmission gates 117 cross couples the sixteen least significant bits of the data bus to the data terminals of the upper memory bank 114. The three sets of transmission gates receive control signals from the DASACK
108 via control bus 91 which enables the various transmission gate sets depending upon the width and address of the word being sent on data bus 92. All of the address bus lines 93 go to each memory bank 112 and 114.
If thirty-two bits of data are being sent on the data bus 92, the DASACK 108 enables the first and third sets of transmission gates 116 and 118. This stores the sixteen least significant bits in the lower memory bank 112 and the sixteen most
significant bits of the data in the upper memory bank 114. When a sixteen bit word is being sent on the data bus 92 it may be stored in either of the memory banks 112 or 114. If it is to be stored in the lower memory bank 112, the DASACK 108 enables
only the first set of transmission gates 116 to pass the data to that memory bank. To maximize the storage capability for sixteen bit words, the separate data may also be stored at the same address in the upper memory bank 114, in which case DASACK 108
enables only the second set of transmission gates 117 which couples the sixteen least significant bits of data to the upper memory bank. When sixteen bits of data are being processed, the third set of transmission gates 118 is never enabled.
FIG. 9 represents the data structure of the RAM memory 106 for each program execution processor module 18. The memory 106 includes a section 310 which contains status information regarding the module's operation. This section 310 stores program
task queues and other data, as will be described, relating to the execution of programs and routines by the module. Each program execution processor module 18 also contains its own data table 312 which is stored in the RAM 106. The data table 312
includes memory locations for various counters, timers and intermediate computation values.
The largest share of the RAM memory 106 is devoted to storing the control programs. The actual program contents, as will be described in detail later, comprise compiled user control programs, independent background tasks and various interrupt
routines to be processed by the processor modules 18. In order to properly carry out the user control programs, support files containing the function chart data, called "descriptors," are also contained within the program area 313.
In one mode of operation of the program execution processor module 18, referred to herein as the "synchronous mode", the processor module 18 periodically copies the entire input image table from the I/O scanner module 20 into its own memory 106.
Space for this copy of the I/O image table is provided in memory section 314.
Remote I/O Scanner Module
As noted above, the I/O scanner modules gather input sensor data for use by the program execution processor modules 18. Referring to FIG. 1, 2 and 6, a remote I/O scanner module 20 couples the programmable controller 10 to one or more remote
input/output racks 17 containing individual I/O modules 19 which interface the sensors, or input devices, and actuators, or output devices, to the programmable controller 10. Each scanner module 20 periodically requests input data pertaining to the
status of the input devices connected to the remote I/O racks 17 and stores it in the module's input image table for reading by other controller modules, such as the processor modules 18. The scanner module 20 also contains an image table of output data
that it receives from other controller modules, such as the processor modules 18. At regular intervals the updated output data in the scanner module's output image table is transferred to the respective remote input/output racks 17 to control the
various actuators connected to these racks.
Referring specifically to FIG. 6, each remote I/O scanner module 20 connects to the three backplane buses 21-23. The I/O scanner 20 contains three sets of internal buses: memory access buses 121-123, microprocessor buses 131-133 and I/O buses
141-143. The three memory buses 121-123 are connected to the backplane 11 by a set of address bus gates 124 and a set of data bus gates 126. Both of these transmission gates are controlled by an inter-bus control circuit 128 which sends signals to the
gates 124 and 126 via the memory control bus 121. A local random access memory, referred to as main RAM 134, is coupled to the three memory buses 121-123. It stores the input image table for the sensor information being input to the I/O scanner 20 from
the remote I/O racks 17 and it also stores the output image table for the output data being output to the remote I/O racks 17.
FIG. 8 shows in detail the data structures stored in the main RAM 134 of each I/O scanner module 20. These data structures include an I/O image table for the remote sensors and actuators serviced by that module 20. The input image table 210
represents the sensor data and consists of three separate sections 212-214. The first section 212 is the image of the actual state of the various sensing devices. The information relating to the inputs that are forced on is contained in the second
section 213 within the input image table 210. As with previous programmable controllers, the user may force the status of a given sensor to appear to be either on or off regardless of its actual state. This enables the bypassing of faulty sensors, for
example. Forced on sensors are designated by a binary one in an address for each such input.
The sensors that are forced off are indicated in the third section 214 of the input image table 210 by a logical zero stored for those sensors. Although by definition the user may write into the forced data tables 213 and 214, the user is
prohibited from writing into the actual input image table 212. During the operation of the programmable controller, the user programs can read either the actual input image data from section 212 or the forced image of the sensor. If the forced image is
read, the scanner module 20 logically OR's the actual sensor input state with the forced on data from section 213, then that result is ANDed with the forced off data for that sensor from section 214.
The output image table 211, also stored in the main RAM 134, includes the output image data table 215 which represents the status for the output devices connected to the remote I/O racks 17 serviced by the I/O scanner module 20. Typically, this
output data is determined by the execution of the user control program in the processor module 18. A second section 216 representing the forced on output data and a third section 217 representing the forced off output data are also included in the
output table 211. This allows the user to define a given actuator as always being on or off regardless of the results from the execution of the user control program. For example, this is useful where a portion of the controlled equipment may have to be
shut down for maintenance and should not be turned on by the user control program. The control program may read each of the output tables 215-217 individually. If the forcing of the output states is disabled the data sent to the remote I/O racks 17 for
activating or deactivating the various controlled devices is obtained from the output image table 215. If output state forcing is enabled then the data sent to the remote I/O racks 17 is a logical combination of the three output tables 215-217 using
Boolean logic that is identical to the combination of the three input tables 212-214 described above.
Referring still to FIG. 8, the data structure in the main RAM 134 of the I/O scanner module 20 also includes a block 218 that contains data regarding the status of the communication adapter in each of the remote I/O racks 17 serviced by the
module 20. This data is used during the transfer of information over the I/O links 15 with those remote I/O racks.
Although the state of most of the sensor and operating devices may be represented by a single binary bit, certain devices, such as position sensors and analog devices, produce or require information that comprises a plurality of digital words.
These data may be | | |
