A system comprises an encoder, a precoder, a PRML channel, a detector, and a decoder. An input signal is received by the encoder. The encoder generates a code string by adding one or more bits and outputs the code string to the precoder. The encoder applies encoding such that the code string after passing through the precoder has a Hamming distance greater than one to eliminate error events with a small distance at the output of the PRML channel. The present invention also provides codes that after precoding have Hamming distance of 2 and 0 mod 3 number of ones. These codes when used over a PRML channel in an interleaved manner preclude +/-( . . . 010-10 . . . ) error events and error events +/-( . . . 01000-10 . . . ). The code string also has a predetermined minimum number of ones at the output of the PRML channel to help derive a clock from the input signal. The encoder provides a "systematic" encoding scheme in which for many code strings the encoded bits are the same as the input bits used to generate the encoded bits. This systematic approach of the present invention provides an encoder that is easy to implement because a majority of the bits directly "feed through" and non-trivial logic circuits are only needed to generate the control bits. The systematic encoding also dictates a decoder that is likewise easy to construct and can be implemented in a circuit that simply discards the control bit. The encoder preferably comprises a serial-to-parallel converter, a code generator, and a parallel-to-serial converter. The code generator produces a rate 16/18 or 16/17 code. The present invention also includes a method that is directed to encoding bit strings and comprises the steps of: 1) converting the input strings to input bits, and 2) adding at least one bit to produce an encoded string with many ones and a Hamming distance greater than one after precoding.

Apparatus for decoding an input digital signal by replacing successive n-bit groups of the input digital signal with respective ones from an ensemble of m-bit data words, each m-bit data word having an associated n-bit code word, where n is greater than m, comprises: means for determining the Hamming distance between an n-bit group of the input digital signal and each of the n-bit code words associated with the ensemble of m-bit data words; and means for replacing that n-bit group of the input digital signal with an m-bit data word from the ensemble of m-bit data words for which the Hamming distance between the n-bit code word associated with that m-bit data word and that n-bit group is the lowest.

An analog to digital converter (ADC) circuit suitable for processing serial data at a fast rate includes a clock control block for receiving a reference strobe signal REF_STB, a reference clock signal REF_CLK, and number of bit control signals CONT.sub.-- 1, CONT.sub.-- 2. The clock control block outputs first and second internal clock signals CLK_A, and CLK_B, and a forwarding direction control signal CONT.sub.-- 3. The ADC circuit also includes a parallel analog to digital converter for receiving and converting analog signal into a parallel digital data synchronously with the first internal clock signal CLK_A. A parallel to serial transform logic control block then transforms the parallel digital data into serial digital data synchronously with the second internal clock signal CLK_B.

The four tables P, Q, R and S contained in an ROM 2 for 16-24 modulation have a total number of data in which the continuing bits are 2 bits, that is not larger than i bits among the 24 bits, so that the number of continuing bits having the same code is from 2 to 8 bits, so as to have the same characteristics as the (1, 7) code, and to stably lock the PLL. A comparator/selector circuit 5 selects an optimum table out of the tables P, Q, R and S.

A clock signal is easily extracted from a signal transmitted corresponding to a partial response transmission method so as to securely identify bits. As a structure of a recording side, an 8-to-9 converting circuit is connected in series with a pre-coding circuit and a recording amplifier. An output signal of the recording amplifier is recorded on a magnetic tape. A signal reproduced from the magnetic tape is supplied to a reproducing amplifier. On a reproducing side, the reproducing amplifier is connected to a partial response equalizing and Viterbi decoding circuit and a clock extracting circuit. The clock extracting circuit is connected to the partial response equalizing and Viterbi decoding circuit.