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BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of power line communications and, more
particularly, transceivers enabling such communications.
2. Prior Art
U.S. Pat. No. 4,918,690 describes a system for providing sensing
bidirectional communications and control. Communications between a
plurality of cells enables, for example, control for switching and the
like. The present invention provides a transceiver for power line
communications which may be used with the system described in U.S. Pat.
No. 4,918,690.
A major problem with power line communications is background noise
including impulse noise. This noise originates not only from the power
source and distribution network, but also from the loads. The noise is not
constant with respect to time and moreover, it varies from place to place
in a power distribution network. A theoretical analysis of impulse noise,
particularly for a twisted pair, is described in "Errors-and-Erasures
Coding to Combat Impulse Noise on Digital Subscriber Loops", IEEE
Transactions on Communications, Vol. 38, No. 8, August 1990, beginning at
page 1145. The present invention, as will be seen, employs snubbing or
blanking to eradicate noise impulses. Applicant is not aware of this
technique being applied to a digital system. Snubbing or blanking has been
used in connection with radio receivers and its use is described in U.S.
Pat. No. 4,124,819.
One commercially available system "X-10" provides sensing, control and
communications over power lines. Coded patterns are transmitted twice,
once in true form and a second time in complementary form on a modulated
carrier. This technique provides only limited immunity to power line
noise. One problem with this system and other systems is that the carrier
detection threshold level is fixed. In selecting a threshold level for
such a system, the level must be relatively high to provide some immunity
from expected noise. This limits the operation of the system, for
instance, where both the noise and signal are low. As will be seen, the
present invention provides an adaptive carrier detection level.
In some communications systems, it is known to transmit information
redundantly on on two channels and then to select the channel with the
strongest signal at the receiver. This technique is used in wireless
microphone systems. As will be seen, the present invention uses two
channels, however, selection between one or the other (or both) channels
is based on noise levels, not signal strength.
Data is often encoded with error correcting codes (ECC) such as Hamming
codes to permit the detection and correction of errors. In the present
invention, this coding is extended through use of a "hint" signal to
locate possible errors. The hint signal is generated from an impulse noise
detection circuit.
Another technique sometimes employed in power line communications is to use
a spread spectrum. Once such power line communications apparatus is
disclosed in U.S. Pat. No. 4,815,106.
SUMMARY OF THE INVENTION
An apparatus for receiving a modulated carrier modulated with binary
signals and transmitted over a power line to the apparatus is described.
Detection means are used for detecting noise pulses on the power line. A
pulse generation means generates control pulses of predetermined duration,
the duration of the pulses being independent of the duration of the noise
pulses. A snubbing means for suppressing the carrier signal under control
of control pulses is used. Means are also provided for limiting the number
of snubbing pulses that can occur. Also, the snubbing is adaptive in that
detection threshold levels are automatically adjusted to be above certain
interfering signals.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram used to illustrate problems associating with power line
communications.
FIG. 2 is a block diagram of the invented power line communications
apparatus.
FIG. 3 is a block diagram of the pulse detector and snubber of FIG. 2.
FIG. 4 illustrates several waveforms used to explain the operation of the
pulse detector and snubber of FIG. 3.
FIG. 5 illustrates several waveforms used to describe the effect of
snubbing on a modulated carrier.
FIG. 6 illustrates the flow of data, Hamming code, and a parity bit in the
present invention.
FIG. 7 is a diagram illustrating the implementation of a Hamming code in
the present invention.
FIG. 8 is a circuit diagram of the snub hint generator of the present
invention.
FIG. 9 illustrates several waveforms used to explain the operation of the
circuit of FIG. 8.
FIG. 10 is a state diagram used to describe the mechanism for updating the
carrier detection threshold level.
FIG. 11A illustrates a plurality of waveforms used to describe the
condition when the carrier detection threshold level is above the average
noise level.
FIG. 11B illustrates a plurality of waveforms used to describe the
condition when the carrier detection threshold level is above the level of
the carrier signal.
FIG. 11C illustrates a plurality of waveforms used to describe the
condition when the carrier detection threshold level is below the noise
level.
FIG. 12 is a diagram used to describe the locations of data constellations
for a quadrature modulated signal.
FIG. 13 is a graph similar to that of FIG. 12 used to indicate the target
areas where data should be located.
FIG. 14 is a block diagram of the currently preferred embodiment of a
portion of the adaptive carrier detection circuit.
FIG. 15 is a graph illustrating the coefficient values used in the score
table of FIG. 14.
FIG. 16 is a circuit diagram of the channel selection or addition circuit
of FIG. 2.
FIG. 17 is a graph of the characteristics of a filter used in the pulse
detector of FIG. 2.
DETAILED DESCRIPTION OF THE INVENTION
A power line communication (PLC) apparatus is described which enables
communications over power lines between cells or other devices. The
apparatus may be realized either with discrete components or as an
integrated circuit formed on a single substrate employing well-known
complimentary metal-oxide-semiconductor (CMOS) technology or other
semiconductor processing technologies.
In the following description numerous specific details are set forth, such
as specific frequencies. These details are provided to enable one to fully
appreciate and understand the present invention. It will be obvious to one
skilled in the art that the present invention may be practiced without
these specific details. In other instances, well-known circuits have been
shown in block diagram form in order not to unnecessarily obscure the
present invention in detail.
Most blocks are described here as circuits implying an analog
implementation. It will be obvious to one skilled in the art that many of
the blocks may be implemented as continuous time analog circuits, as
discrete-time analog circuits (i.e., switched capacitor circuits), as
dedicated digital signal processing hardware, or as software on a digital
processor with no change to their overall function and purpose. The
continuous time analog descriptions in some cases in this application is
adopted for clarity of description and in order to provide a better
understanding and appreciation of the present invention.
Problem Associated with Power Line Communications
To appreciate the present invention, it will be helpful to understand some
of the problems associated with communicating over power lines. The power
lines referred to are typically used to distribute 50 or 60 Hz A.C. power,
although in some cases higher frequencies are used such as 400 Hz in
aircraft or lower frequencies such as 25 Hz in some rail systems. The
power line communication signals are transmitted over the same lines that
carry the power by modulating a higher frequency carrier signal. For
instance, a 150 kHz carrier may be used to communicate digital signals
over the power lines at a baud rate of 10 kB.
In co-pending application Ser. No. 586,458, entitled METHOD AND APPARATUS
FOR POWER LINE COMMUNICATIONS, assigned to the Assignee of the present
application, a method and apparatus is disclosed for coupling power line
communication devices into a power distribution network. Such coupling may
be used in conjunction with the present invention. Also in U.S. Pat. No.
4,918,690, a system for sensing, communicating and controlling is
disclosed which includes cells that may be coupled to power lines through
the apparatus of the present invention.
Referring to FIG. 1, a power line communication transmitter 8 is
illustrated connected into a typical household electrical receptacle. The
transmitter 8 may be embedded within the receptacle to control another
outlet. For purposes of discussion, assume the transmitter 8 transmits
signals to a PLC receiver 10 which controls an appliance coupled into the
receptacle associated with receiver 10. The communications path between
the transmitter 8 and receiver 10, as illustrated, passes through a
circuit breaker panel. This is often the case where one of the receptacles
is on one branch circuit and the other on another branch circuit. A signal
transmitted by transmitter 8 at, for example, 150 kHz may be attenuated by
more than 40 dB before reaching the receiver 10. As can be appreciated, if
the transmitter 8 is transmitting with a one volt output, the voltage at
receiver 10 will be substantially diminished.
There are numerous sources of noise and other transients associated with
power lines distribution system that make it difficult to receive and/or
reconstruct signals from a PLC transmitter. One source of noise is an
electronic dimmer which "chops" the A.C. waveform. Another example of
noise is a switching power supply, frequently used in personal computers,
which produce high frequency noise bursts (e.g., 25 kHz or greater). Other
sources of noise found in a home or commercial environment include
intercoms, electric motors, televisions and numerous others. Consequently,
the receiver 10 must be able to ferret out the communications signal from
the noise on the power line. (While in the above discussion, a separate
transmitter and receiver are shown, typically the functions of
transmitting and receiving are combined into a single device.)
Overall Block Diagram of the Currently Preferred Embodiment of the Invented
Power Line Communications Apparatus
Referring now to FIG. 2, the upper portion of the block diagram is the
transmit section of the PLC apparatus while the lower portion of FIG. 2 is
the receive section. The transmit section is included here for clarity.
The transmit section is not the subject of the present invention. This
latter section receives signals over the power line 41, processes them,
then couples the resultant digital signal to the I/O buffer and control
circuit 17. From there, the signals are coupled over lines 40 to a cell or
other device. The lines 40 may communicate with a cell such as described
in U.S. Pat. No. 4,918,690. Certain aspects of the circuit 10 are
described in copending application "Transceiver Interface", Ser. No.
676,948, filed Mar. 28, 1991, assigned to the Assignee of the present
invention.
The data to be transmitted, which arrives from the cell over lines 40 is
coupled to an error correcting code encoder 11. The data is encoded, in
the currently preferred embodiment, with a (15,11) Hamming code, meaning
that 4 bits of error correction code are appended to each 11 bit data
word. The encoding may be done in an ordinary manner, however, since 8-bit
data words are encoded, means are provided for incorporating "dummy" or
placeholder bits with each byte both during encoding and decoding as will
be described in conjunction with FIG. 6. A parity bit is also transmitted
with each word. Data is transmitted from the cell onto the power line in
packets with the preamble generator 12 providing a preamble for the
packets. At summer 13 the preamble is positioned in front of the packets
of encoded data from the encoder 11. Consequently, the summer 13 performs
a multiplexing function in that it selects either the data or preamble.
Details of the preamble generator 12 and preamble decoder 35 of the
currently preferred embodiment are described in co-pending application
"Data Rate Detection" Ser. No. 698,445, filed May 10, 1991, assigned to
the Assignee of the present application.
The output of the summer 13 is coupled to a waveshaping and modulating
circuit 14. In the currently preferred embodiment, this circuit includes a
read-only-memory, digital-to-analog converter and two filters. (The
filters in the integrated circuit embodiment of the present invention are
switched capacitor filters.) Certain aspects of the waveshaping and
modulation circuit 14 are described in co-pending application "Carrier
Frequency Derivation" Ser. No. 698,676, filed May 10, 1991, assigned to
the Assignee of the present invention. Other circuits for performing these
functions are well-known in the prior art.
With the invented apparatus, the data is transmitted in its entirety on two
channels, that is, there is redundancy in the transmission. All the data
(including the preamble) modulates both a 118 kHz carrier and a 133.7 kHz
carrier for PLC apparatuses designed for use in the United States. (Other
carrier frequencies are used for other countries to comply with different
regulations.) The frequency separation between the frequencies is
discussed in conjunction with the channel selection or addition circuit 33
of FIG. 16. While the data is transmitted on both channels, the receiver
selects one or both channels, as will be described.
Quadrature phase shift keying (QPSK) is used to modulate the carriers under
most operations. However, BPSK is also used as described in the above
mentioned applications. BPSK signaling, at half the bit rate of QPSK
signaling, is more immune to noise than QPSK but slower. The BPSK
signaling scheme has the same receiver structure as QPSK, but uses only a
two-point subset of the fourpoint QPSK signaling constellation. The BPSK
signaling scheme communicates one bit of digital information in every
signaling baud period. (Data bit rate and baud rate are equal.) The QPSK
signaling scheme communicates two bits of digital information in every
signaling baud period (data bit rate is twice the baud rate). The
signaling baud rates for BPSK and QPSK signaling determined by physical
parameters of the receiver filters are the same. In some of the examples
below BPSK is discussed since it is easier to understand of the present
invention when the bit rate is equal to the baud rate.
The output of the waveshaping and modulation circuit 14 is coupled to an
amplifier 15 and from there to the power line 41 through a power line
coupling network 16. As currently preferred, the amplifier 15 and network
16 are fabricated from discrete components. The amplifier 15 and network
16 are described in copending application "Improved Power Line Coupling
Network" Ser. No. 678,525, filed May 10, 1991 and Drive Amplifier for
Power Line Communications Ser. No. 698,455, filed May 10, 1991, both are
assigned to the Assignee of the present invention.
Signals received on the power line 41 are coupled through the network 16 to
the filters 18. Filters 18 again comprise switched capacitor filters for
the integrated circuit embodiment. The filters 18 comprise a high pass
filter and a low pass filter. The high pass filter has a cut-off frequency
of approximately 90-110 kHz, and the low pass filter, a cut-off frequency
of approximately 320 kHz. The filters 18 thus pass the modulated carriers
and additionally the filters 18 pass certain noise.
The pulse detector 20 receives the output of the filters 18 (node 42). The
detector 20 detects anomalies in the waveform such as noise pulses or
other excursions of the waveform above or below certain threshold levels.
For example, the pulse detector 20 detects noise associated with a light
dimmer and other sources of noise pulses. The pulse detector 20 provides a
snubber control signal to a snubber 22 on line 61. The snubber 22 blanks
or snubs the signals from filters 18 for predetermined periods when a
pulse representing a disturbance (noise pulse) is present in the received
signal.
The pulse detector 20 and snubber 22 are described in conjunction with FIG.
3. The output of the snubber 22 which is the main received signal path is
coupled to demodulator 28 on line 64. The carrier synchronization circuit
26 provides COS .function.c1, SIN .function.c1, COS .function.c2 and SIN
.function.c2 to the demodulator 28. Four signals are coupled from the
demodulator 28 to the circuit 26 (two for each channel). As mentioned
above, two carriers are used and hence two channels are needed; one for
the 118 kHz signal and the other for the 133.7 kHz signal. The demodulator
28 under control of the output of detector 26, demodulates the two carrier
signals and provides both an in-phase and quadrature phase signal for each
of the two channels to the filters 32. The output of the demodulator 28 is
also coupled to a bit (baud) synchronization circuit 30. This circuit
provides baud synchronization to the decoder 34 as well as other circuits.
Circuit 30 also provides snub frame timing signals shown in FIG. 9 and
elsewhere. The demodulator 28 and bit synchronization circuit 30 are
ordinary, well-known circuits except as discussed herein. The two channel
carrier detect and adaptive carrier detect threshold circuit 29 uses an
adaptive threshold level which is described in conjunction with FIGS.
10-15.
The filters 32 comprise four matched filters, two for each channel. These
filters may be of ordinary design for the illustrated use.
The output of the filters 32 are coupled to the channel selection or
addition circuit 33. This circuit receives two control (selection) signals
from the circuit 29. Within circuit 33, the data from one channel or the
other from filters 32 is selected and forwarded to the bit slicer 31, or
the data in both channels is added together and forwarded to the bit
slicer 31. (Note: the same data in present in both channels.) In summary,
if the noise in one channel is high, relative to noise in the other
channel, the channel with the lesser noise is selected. If the noise is
both channels is approximately equal, the signals in the channels are
added. Details of this circuit are described in conjunction with FIG. 16.
The output from circuit 33 is coupled to the slicer 31 where the waveform
is converted to a digital form in an ordinary manner under control of the
bit synchronization signal. The output of circuit 33 is shown by the
waveform on line 96 of FIG. 5. The slicer 31 provides the binary 1 or 0
levels by detecting the signal level at, for example, time 100. (This
diagram shows BPSK for purposes of explanation. In the QPSK case two
signals are forwarded from the channel selection circuit 33 to the slicer
31 and the slicer outputs two bits per signaling baud.)
The signal from slicer 31 is coupled to the preamble decoder 35 where the
preamble is stripped off. The output of decoder 35 is coupled to the ECC
decoder 34. Here, it is determined whether an error occurred in the
transmission and if so, it is corrected with the Hamming code as will be
explained. Additionally, a parity bit is transmitted with each word
enabling the detection of a second error in each byte. One novelty of the
present invention is the use of a "hint" from the pulse detector 20 which
permits correction of a second transmission error in each byte under
certain conditions. In summary, the position along the modulated waveform
where an unsnubbed noise pulse occurs provides the hint as to where an
error may have occurred in the data. A hint signal is transmitted on line
36 to the decoder 34 allowing the decoder to know where in the data stream
the noise pulse occurred, and thus, where it is likely that an error may
have occurred. The use of the hint in connection with the decoder 34 is
described in conjunction with FIGS. 3 through 9.
The decoded data is coupled from the decoder 34 to the input/output buffer
and control circuit 17 and from there to the cell or other device over
lines 40.
While in the following description analog signals are sometimes discussed
since they are used in the currently preferred embodiment, the present
invention may be realized using digital signal processing (DSP)
techniques. For instance, as mentioned the signal path from the output of
filters 18 through the slicer 31 can be fabricated with DSP techniques.
Pulse Detection and Snubbing Circuits and Their Operation
In FIG. 3, the pulse detector 20 and snubber 22 of FIG. 2 are shown in
detail. The input to the snubber 22 of FIG. 2 (node 43), is shown in FIG.
3 on the right edge of the figure. Node 43 is coupled to a delay circuit
73 to delay the modulated carriers for reasons which will be explained.
The delayed signal is the output signal on line 64. This signal is snubbed
through an analog switch 63; that is, the received signal (carriers and
noise pulses) are selectively blanked under control of the snub control
(SNUBCTL) signal which signal operates the switch 63. The remainder of the
circuitry of FIG. 3 generates the SNUBCTL signal.
The input to the pulse detector 20 (node 42) of FIG. 2 is shown in the
upper left corner of FIG. 3. Node 42 is coupled to the inputs of filters
44 and 45. The high pass filter 44 has a cut-off frequency of
approximately 150 kHz hence, the output of filter 44 consists
approximately of the band 150-320 kHz (this band excludes the carriers).
The output of the filter 44 is coupled to a positive envelope detector 47
and a negative envelope detector 48. Also, this filter's output is coupled
directly to a window comparator 53. The outputs of the positive and
negative envelope detectors provide envelope threshold signals which are
proportional to the background noise. Signals at the output of the filter
44 which are greater than the envelopes by a certain amount (either in the
positive or negative sense) are detected within the window comparator 53.
A signal occurs at the output of comparator 53 whenever the output of the
filter 44 exceeds by the certain amount the threshold levels established
by either the positive or negative envelope detectors. In effect, one may
look at the positive and negative envelope detectors along with the window
comparator as a full wave rectifier with a threshold level established by
the background signal. What is occurring is that the threshold levels are
established by the noise; pulses which are greater than the established
threshold levels are detected and provided an output to one terminal of OR
gate 56.
The signal in the path from the output of filter 44 directly to the
comparator 54 is attenuated in the comparator by a factor of four
(assuming there is unity gain in the detectors 47 and 48). Consequently,
only pulses four times or greater than the noise envelope triggers the
comparator 53. In the currently preferred embodiment, the detectors 47 and
48 have an approximately 850 microsecond charging time constant and a 6.8
millisecond discharging time constant; detectors 50 and 51 have an
approximately 150 microsecond charging time constant and a 300 microsecond
discharging time constant.
The low pass notch filter 45 in the currently preferred embodiment,
provides a low pass filter which significantly attenuates (25dB or
greater) signals above 200 kHz. The reason for this filter will be
described shortly. The output of filter 45 is processed in a similar
manner to the output of filter 44. Specifically, filter 45's output is
coupled to a positive envelope detector 50, a negative envelope detector
51 and a window comparator 54. Once again, pulses exceeding the threshold
levels established by detectors 50 and 51 by the certain amount, produce
signals from comparator 54; these signals are coupled to the other
terminal of the OR gate 56. However, in this case the carrier signal of
received packets set the threshold levels.
Bearing in mind that the purpose of the pulse detector is to blank the
modulated carriers when a noise pulse occurs, it would seem that the
output of window comparator 53 is all that is needed. It has been found
however, that continuous interference may occur at 200-400 kHz since this
is the carrier frequency range associated with some power line intercoms.
If an intercom is in use, pulses occurring at 200 kHz and above, raise the
threshold levels established by detectors 47 and 48, substantially
preventing the detection of any noise pulses.
The circuit of FIG. 3 is adaptive in that it compensates for the existence
of the intercom disturbance at 200 kHz or above. The intercom signals as
shown by FIG. 17, are significantly attenuated by the filter 45. The
threshold levels established by the detectors 50 and 51 are primarily set
by the signals below 200 kHz. Consequently, when the intercom signal is
present, the output of comparator 54 substantially controls the snubbing
through the OR gate 56. This is less desirable than using the output of
comparator 53, but is a substantial improvement over losing all snubbing
during the presence of the intercom signal.
It is more desirable to have the threshold level established by the
background noise (as with comparator 53). However, with the intercom
signal present, this threshold level is high. For this case, noise
exceeding (by a factor of 4) the threshold levels established by the
carrier signals in comparator 54 is detected.
The output of the OR gate 56 (SNUBTRY) is coupled to one input terminal of
an AND gate 57. The output of the AND gate is coupled to the RST terminal
of a flip-flop 59. The Q/output of this flip-flop is the snub control
(SNUBCTL) signal on line 61. The S terminal of flip-flop 59 is coupled to
the output of a counter 67 through line 72. The clock terminal of the
flip-flop 59 receives a high frequency (higher than the baud rate)
clocking signal. The clocking signal is used throughout the apparatus and
is not shown in FIG. 2.
The flip-flop 59 is used to extend the period of the signals from gate 56.
Referring to FIG. 4, two pulses 80 and 81 are shown on line 74 which, for
purposes of explanation, are assumed to be noise (the modulated carrier is
not shown in this drawing). A typical pulse includes ringing and thus
there is a tail extending from the main source of energy. Ideally, as
shown along line 75, waveform 82 should be used to snub the pulse 80. Line
76 illustrates the output of the gate 56. This output has a main pulse 84
associated with the peak level of the noise pulse and one or more
additional pulses 85 that occur if the tail of the noise is detected. In
the currently preferred embodiment, as illustrated on line 77, the width
is selectable in the range from 30 to 45 microseconds. This assures that
the entire noise pulse is snubbed. As will be seen later, the 30 to 45
microsecond period is not sufficiently long when compared to the baud rate
to disturb the detection of a bit or bits which is partially snubbed with
one SNUBCTL signal. The input to the S terminal of the flip-flop 59 (line
72) determines when SNUBCTL ends; this input is provided by the counter
67.
The counter 67 receives a 5-bit word from the multiplexer 66. These bits
designate one of four times (30, 35, 40 or 45 microseconds). Two bits
received from the cell selected one of the four times. An additional
signal is used to indicate whether the apparatus is to be used in the
United States or Europe to adjust the five bit value due to different
clock frequencies. The five bit output of the multiplexer 66 is coupled to
the counter 67. Counter 67 is enabled and reset when the Q/output from
flip-flop 59 goes high; this output is coupled through a rising edge
detector 70. Counting occurs under control of a clock signal. (The main
clock signal which is relatively fast, is divided down by the divider 69
before being coupled to the counter 67.) The period of the counting is a
function of the five bit input from MUX 66. Once a predetermined count is
reached in the counter 67, a signal on line 72 sets the flip-flop 59,
ending the snubbing. In this way, the duration of the snubbing pulses are
user selected as 30, 35, 40 or 45 microseconds. (One of these periods may
be used as a default period if no selection signals are received by the
multiplexer 66.)
The SNUBCTL signal will not be in time coincidence with the beginning of
the noise pulse because of delays in the filters 44 or 45 and other
circuits. This is shown on line 76 of FIG. 4 by time 83. To compensate for
this, the modulated carriers, along with the embedded unwanted noise
pulses, are delayed by the delay circuit 73. The delayed noise pulses are
shown on line 78 of FIG. 4. Line 79 again illustrates the SNUBCTL signal
and as can be seen, snubbing occurs in time coincidence with the beginning
of the pulse 80 of line 78.
Another consideration is that if too much snubbing occurs, data will be
lost. In the currently preferred embodiment, each SNUBCTL pulse results in
a hold-off period of a fixed duration during which another SNUBCTL pulse
is prohibited. This fixed duration measured from the beginning of the
SNUBCTL pulse, in the currently preferred embodiment, is approximately 100
microseconds. This period is shown in FIG. 4.
Assume that a second noise pulse 81 occurs after the first noise pulse 80
within 100 microseconds of the first pulse 80. The output of gate 56
caused by pulse 81 is shown as waveform 86. One might expect that an
additional snubbing pulse (shown as dotted line waveform 87) occurs. This
is not the case since the circuit of FIG. 3 prevents a second snubbing
pulse during the hold off period. Referring to FIG. 3, once a SNUBCTL
pulse occurs, flip-flop 60 is set, thus its Q/output drops. This prevents
gate 57 from passing signals such as waveform 86 of FIG. 4 onto the
flip-flop 59. The beginning of the SNUBCTL pulse also resets and enables
counter 91 because of the output from detector 70. Once a predetermined
count is reached in counter 91 (corresponding to 110 microseconds), a
signal on line 88 occurs resetting flip-flop 60. The Q/output of flip-flop
60 goes high, allowing signals to be passed through gate 57. Consequently,
once a SNUBCTL signal occurs, no additional snubbing is possible for 110
microseconds.
The fact that a second noise pulse 81 occurred and was not snubbed, is used
in the invented apparatus. The occurrence of the pulse 81 and the waveform
86 (without snubbing) causes the generation of the hint signal at time 89
shown in FIG. 4. This signal is transmitted over line 36 to the decoder 34
(FIG. 2). As will be discussed later, if an error is detected in a word
associated with unsuppressed noise, the noise may have changed the state
of the data occurring at the time of the noise. That is, for the single
frame shown along line 83, if a binary 0 is detected for that bit, and a
second impulse 81 is detected, one step that may be taken in the
correcting process is to change the state of this bit from a binary 0 to a
binary 1. Circuit 34 determines whether this state change is required
while the snub hint acts as a pointer indicating which bit to change. (The
circuit that generates the hint signal and its timing are discussed in
conjunction with FIGS. 8 and 9.)
Referring to FIG. 5, the effect of the snubbing on a received signal is
illustrated for a BPSK case. A single noise pulse is shown on line 92
which is assumed to occur with a carrier. Waveform 93 shows the modulated
carrier during two baud intervals; the first baud interval is modulated
with a binary 0 and the second baud interval is modulated with a binary 1.
(Note the phase shift in the carrier between the first and second baud
time.) Line 94 illustrates the SNUBCTL signal generated as described
above. On line 95 the effect of the snubbing signal on the demodulation
signal is shown. During the period 99 there is no signal to detect because
the carrier signal is interrupted by the switch 63 of FIG. 3. The detected
signal is illustrated on line 96 at the output of filters 32. The binary 0
is detected at time 100 by the slicer 31. The binary 1 following this
binary 0 should cause the signal to follow the waveform indicated by the
dotted line 97, assuming no disturbance occurred and no snubbing occurred.
However, since a portion of the waveform on line 95 was snubbed, the
actual waveform on line 96 falls short of its expected amplitude by the
amount 98. Nonetheless, a binary 1 is detectable since the voltage
represented by 98 is relatively small compared to the total magnitude of
the waveform 97. If, on the other hand, a hold-off period was not
implemented, additional energy may be lost from the modulated signal from
more snubbing, and the binary 1 may not be detectable. (Depending upon the
relative duration of the bit period and snubbing period, two or more
snubbing pulses may be used during a single frame in some systems.)
The relative amplitudes shown in FIG. 5 are for purposes of explanation and
are not necessarily representative of actual amplitude. For instance, the
amplitude of the disturbance causing pulse is often much larger than the
modulated carriers. This is particularly true for the examples set out in
FIG. 1 where the transmitter is far from the receiver and the source of
the noise close to the receiver. The energy associated with the
disturbance pulses is often sufficiently large (if not snubbed) to prevent
the correct detection of the binary data.
SNUB Hint Generator Circuit
Referring to FIG. 8, the snub hint generator includes an AND gate 112; the
output of this gate is coupled to the reset terminal of the flip-flap 113.
The Q/output of the flip-flop 113 is coupled to the D input of the
flip-flop 113. The Q output of flip-flop 114 is coupled to the D terminal
of the flip-flop 115. The Q output of flip-flop 118 provides the snub hint
on line 36 of FIG. 2.
The inputs from FIG. 3 to the AND gate 115 are the SNUBTRY signal, the
SNUBCTL signal (line 61) which is coupled to an inverting terminal and the
SNUBENABLE signal which is also coupled to an inverting terminal. The
SNUBFRAME signal is coupled to the S terminal of the flip-flop 113 and the
CE terminal of the flip-flop 114. The main clock from FIG. 3 is coupled to
the clock terminals of flip-flops 113 and 114. The baud clock from FIG. 3
is coupled to the flip-flop 115.
As will be described in conjunction with FIG. 9, the flip-flop 113, in
essence, provides an asynchronous reset controlled by the output of gate
112. The flip-flops 114 and 115 resynchronize the hint signal to bring it
into the baud boundary so that it can be used by the ECC decoder.
In FIG. 9, the top waveform illustrates received signal at the snub switch;
two bits for data X and Y are used for purposes of explanation. The
relationship between the baud clock and snub frame signal is shown in FIG.
9. The SNUBFRAME signal is coupled from the bit synchronization circuit 30
of FIG. 2 to the snubber 22. As can be seen, the SNUBFRAME signals occur
before each baud clock. The SNUBTRY waveform (the output of the OR gate 56
of FIG. 3) indicates that during the X frame two disturbances are detected
as indicated by the pulses 117 and 118. When the first pulse occurs, the
SNUBENABLE signal | | |
