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Description  |
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This invention is in the field of integrated circuits, and is more
specifically directed to semiconductor memories having modes for fast
access.
BACKGROUND OF THE INVENTION
A continuing trend in the semiconductor field is the increase in the
density of storage bits per chip in semiconductor memory devices. This
trend has continued for high density, medium performance, memories such as
dynamic random access memories (dRAMs). In the past decade, each new
generation of dRAM has provided an increase in storage capacity of a
factor of four over the prior generation, with the newest generation of
chips containing 4 Mbits each. The rapid increase of the density of such
memories has created increased pressure to increase memory bandwidth,
i.e., the speed at which the user can access the bits in the memory.
Without improvement of memory bandwidth along with the increase in the
density of the memory, the additional bits provided by a new memory
generation have decreasing utility to the user.
This bandwidth pressure has also led to increased emphasis on increasing
the density and also the performance of static random access memories
(sRAMs) which can be used not only for main memory in a system, but also
as large high speed caches in a memory system. With the advent of high
performance CMOS and BiCMOS process technologies, high density sRAMs with
access times less than 10 nsec have been fabricated, as described in Tran
et al., "An 8ns BiCMOS 1Mb ECL SRAM with a Configurable Memory Array
Size," 1989 IEEE ISSCC Digest of Technical Papers (IEEE, 1989), pp. 36-37.
sRAM devices such as these can be used not only for main memory in a
system, but also as large high speed caches in a memory system.
As is well known, a cache memory is a common technique used in data
processing systems for improvement of system memory performance. A cache
memory is a relatively small and high-speed memory which stores data from
a number of main memory locations surrounding a memory location which has
been addressed. The theory of cache operation is that the system central
processing unit (CPU) will frequently address a memory location which is
adjacent, or near (in terms of address value), a memory location that it
has recently addressed. Each group of data stored in the cache is
associated with a "tag", or a portion of the memory address which is
common to the data stored in the cache, and a comparator compares a
portion of the memory address presented by the CPU with the tag or tags
associated with the data stored in the cache. If the desired memory
address matches a tag value (i.e., a cache "hit" occurs), the cache can be
accessed to more quickly provide the desired data than if the main memory
were addressed, thereby improving the effective memory bandwidth of the
system.
In the event that the appropriate portion of the desired memory address
does not match the tags associated with the data stored in the cache
(i.e., a cache "miss" occurs), the main memory must be accessed, resulting
in a delay relative to a cache access. Generally a portion of the cache is
then refilled with data from main memory in the locations proximate to the
newly addressed main memory location. The additional time required to
access main memory instead of the cache, plus the additional time required
to fill the cache with the new data from the proximate addresses to the
new memory address (if done for each miss), is commonly referred to as the
"miss penalty". It should be noted that the time required to refill the
cache, as well as the initial access to main memory for the desired memory
address, depends upon the main memory cycle time, and is directly
proportional to the number of bits in the cache (or portion of the cache
associated with a given tag, such portion commonly referred to as a "line"
of the cache). As a result, if the miss penalty becomes large, the
effective memory bandwidth of the system will decrease, even with
relatively low miss rates. In improving the system performance by
improving the cache bandwidth, it is therefore important not only to
reduce the rate of cache misses, but also to reduce the miss penalty
associated with each cache miss.
It is desired, for purposes of reducing system cost, as well as system
complexity, to incorporate cache accesability within the main memory
device itself in order to reduce the miss penalty. It has been proposed
that dRAMs having the static column decode feature be used in a cache
organization. See J. Goodman and M-C Chiang, "The use of Static Column RAM
as a Memory Hierarchy," The 11th Annual Symposium on Computer Architecture
(IEEE Computer Society Press, 1984), pp. 167-74. However, a cache miss in
such a memory will require that the dRAM operation of precharging the
dynamic row decoding and sense circuitry, followed by presentation of a
row address together with a row address strobe be performed prior to the
access of a bit associated with the new row address. It should be noted
that dRAMs such as this have multiplexed address pins, so that the
presentation of the column address must wait until after the presentation
of the row address. Accordingly, the time penalty for such an operation in
the event of a cache miss reduces the benefits of using such a memory in a
"cache" mode.
Due to the non-multiplexed and static (i.e., non-clocked) operation of
conventional sRAMs, the disadvantages of using static column decode dRAMs
as an integrated memory with on-chip cache can be somewhat reduced. This
is especially the case for some conventional sRAM devices which utilize
address transition detectors for detecting a change in the address
presented thereto, so that decoding of the address need only occur when a
new address is received. In addition, for those static memories which
utilize some dynamic features, such as bit line precharge and dynamic
address decoding, these dynamic operations will be initiated by the
address transition detection circuitry so that they are done only in the
event of a memory address transition.
In conventional memories which utilize address transition detection,
however, a change of address will cause the memory to precharge and to
decode the address even for those cycles for which the row address does
not change. For the example of a 64kbit sRAM having 256 rows and 256
columns, where a single column is associated with a single sense
amplifier, a large number of bits (e.g., 256 bits in a 64 kbit memory) are
potentially accessible from a single row. However, if address transition
detection is performed on the entire address, as is conventionally done, a
full memory cycle will be performed in such conventional memories even
when the desired data is already present in the sense amplifiers, and when
precharge and row address decoding is unnecessary.
The performance of a full memory cycle will dissipate more power than will
a cycle consisting of column decode and output of the state of the
selected sense amplifier, since the full memory cycle includes additional
operations such as precharge, energizing of the selected row, and sensing.
Accordingly, if a full memory cycle is not performed in those instances
when only an access of previously sensed data from a previously selected
row is desired, the power dissipation of the memory, measured over normal
system operation, can be reduced.
It is therefore an object of this invention to provide a memory which
allows for faster bit access from a previously sensed row, without
requiring a new row to be selected and sensed.
It is a further object of this invention to provide such a memory using
address transition detection on only a portion of the memory address for
initiating a precharge portion of the cycle, so that a faster access mode
is available for the data bits accessible by transitions of the remainder
of the memory address.
It is a further object of this invention to provide such a memory wherein
the address transition detection can be disabled, ensuring that the memory
remains in the fast access, or cache, mode.
It is a further object of the invention to provide such a memory which is
organized into blocks, each having cache operation therefrom, to improve
the cache hit performance of the memory.
Other objects and advantages of the invention will be apparent to those of
ordinary skill in the art having reference to the instant specification
together with the drawings.
SUMMARY OF THE INVENTION
The invention may be incorporated into a random access memory, such as a
static random access read/write memory, which uses address transition
detection on a portion of its received address for initiating precharge of
the memory and decoding of that portion of the address. The memory is
constructed so that access of multiple bits from a previously sensed
portion of the memory (e.g., a row) can be accomplished from the remainder
of the memory address without initiation of precharge. The memory may also
be constructed with the ability to disable the address transition
detection circuit, to ensure that the cache mode is maintained regardless
of transitions of the previously detected portion of the address.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a static RAM constructed according to a first
embodiment of the invention.
FIG. 2 is an electrical diagram, in schematic form, of a column in the
memory of FIG. 1, illustrating its association with the precharge and
sense amplifier circuitry.
FIG. 3a is an electrical diagram, in schematic form, of sense amplifier
latch control circuitry in the memory of FIG. 1.
FIG. 3b is a timing diagram illustrating the operation of the circuitry of
FIG. 3a.
FIG. 4 is a timing diagram illustrating the operation of the memory of FIG.
1.
FIG. 5 is a block diagram of a static RAM constructed according to a second
embodiment of the invention.
FIGS. 6a and 6b are electrical diagrams, in schematic form, of control
circuitry in the memory of FIG. 5.
FIGS. 7a and 7b are timing diagrams illustrating the operation of the
circuitry of FIGS. 6a and 6b, respectively.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to FIG. 1, a memory 10 constructed according to a first
embodiment of the invention will be described. The following description
will be for the example of a static random access memory (sRAM), although
it should be noted that the invention is equally applicable to other types
of read/write memories, as well as read-only memories, both mask
programmable and electrically programmable. Memory 10 has an array 22 of
memory cells, in this case static memory cells, which are organized in
rows and columns. An exemplary organization of array 22, for the case of a
64 kbit memory, is 256 rows and 256 columns. Row decoder 15 receives a row
address on bus 4 from those address terminals associated with the row
address, and is operable to energize the row in array 22 which corresponds
to the received row address.
Each of the columns in array 22 of this embodiment are associated with a
sense amplifier 38, which is for sensing the data state stored in the
memory cell of the column which is in the selected row. In this first
preferred embodiment, as will be explained in greater detail hereinbelow,
sense amplifiers 38 are associated with the columns in array 22 on a
one-to-one correspondence; other organizations of the sense amplifiers 38
may alternatively be used. Column decoder 18 receives the column address
portion of the address from the terminals associated with the column
address, and decodes the same in order to select one or more of sense
amplifiers 38 to be read from or written to, according to the value of the
column address. Access is accomplished by communication of the selected
sense amplifier 38 with input/output buffer 40 which, in turn,
communicates the data from the selected sense amplifier 38 to output
terminal Q in a read cycle, and communicates data from input terminal D to
the selected sense amplifier 38 in a write cycle; terminal R/W.sub.--
receives a read/write signal to control the direction of the data flow, in
the conventional manner. While memory 10 of FIG. 1 is illustrated as
having single dedicated input and output terminals D and Q, respectively,
memory 10 may alternatively be organized in a wide word (e.g., by-four,
by-eight) manner, and also alternatively utilize single or multiple common
input and output terminals, if desired.
Associated with array 22 is precharge and timing control circuitry 24, for
precharging the bit lines in array 22 associated with the columns therein.
My copending application Ser. No. 213,814 filed Jun. 30, 1988 and assigned
to Texas Instruments Incorporated illustrates an example of such
circuitry. In this preferred embodiment, as will be described in greater
detail below, the bit lines in array 22 on which the data is to be
communicated between sense amplifiers 38 and the memory cells in array 22
are to be precharged prior to the sensing of a newly selected row. This is
advantageously done upon receipt of a new row address. In addition,
precharge and control circuitry 24 receives an externally driven
read/write signal on line R/W.sub.--, so that the sensing operation is
controlled according to the desired operation. During precharge of the bit
lines, it is preferable that the sense amplifiers 38 associated therewith
are disconnected from the bit lines, so that the previously sensed data
state does not affect the potential to which the bit lines are to be
precharged. Accordingly, the sense amplifiers 38 are to be controlled to
so operate in conjunction with the precharge and control circuitry 24.
In this embodiment of the invention, the operation of row decoder 15,
precharge and control circuitry 24, and sense amplifiers 38 is dependent
upon the receipt of a new row address at the row address terminals.
Accordingly, address transition detection circuit (ATD) 14 is connected to
bus 4 to receive the row address. Responsive to a transition of the state
of the row address at the row address terminals, ATD 14 issues signals
(preferably a pulse, as will be described hereinbelow), on line 5 to row
decoder 15, on line 6 to precharge and control circuitry 24, and on line 8
to sense amplifier latch control circuitry 17. Accordingly, the detection
of a transition of the row address will cause ATD 14 to initiate the
precharge portion of the memory cycle, to disconnect the sense amplifiers
38 from the bit lines in the array 22, and to initiate decoding of the row
address by row decoder 15. ATD 14 is constructed according to any of the
various conventional address transition detection circuits known in the
art.
As described in my copending application Ser. No. 213,814, and as will be
described in detail hereinbelow, a transition of the row address detected
by ATD 14 will initiate a precharge and equalization operation, by which
precharge and control circuitry 24 will set the potential of the bit lines
in array 22 to a predetermined potential, prior to selection of the row by
row decoder 15. In accomplishing this operation, as well as the sensing
operation itself, sense amplifiers 38 must be controlled so that they
remain latched to the selected memory cell in the column, or isolated from
the bit lines, depending upon the desired operation. Sense amplifier latch
control circuitry 17 generates a signal on line SAL responsive to a pulse
on line 8 from ATD 14, so that sense amplifiers 38 are disabled during the
precharge operation and are enabled thereafter to sense and retain the
data from the selected row. Alternatively, ATD 14 can directly control
sense amplifiers 38, without requiring additional sense amplifier latch
control circuitry 17, so long as the signal presented by ATD 14 responsive
to a transition has the appropriate timing and duration within the memory
cycle.
If row decoder 15 is dynamic, ATD 14 will initiate the decoding operation
by sending the appropriate signal on line 4 responsive to a transition of
the row address. It should be noted, however, that static decoding of the
row address may alternatively be used, in which case it is not necessary
that ATD 14 initiate the decoding operation of row decoder 15. It should
also be noted that it is not necessary that the portion of the address to
which ATD 14 is responsive to initiate the precharge operation correspond
to the row address, with the remainder of the address to which ATD 14 is
not responsive corresponding to the column address, although such use of
the row and column addresses is especially beneficial in this embodiment.
Other organizations of memories which can achieve the benefits of the fast
access mode described herein will be apparent to those of ordinary skill
in the art having reference to this specification. For example, the
embodiment described above has one of sense amplifiers 38 associated with
a single column in array 22. An alternative organization which is
especially suitable for static RAMs is to have one of sense amplifiers 38
associated with multiple columns in array 22. In this arrangement, a
portion of the column address is used to select which of the multiple
columns is to be selected for communication with each sense amplifier 38.
For this alternative organization, the portion of the address to which ATD
14 would be responsive would include not only the row address, but also
that portion of the column address which is used to select one of the
multiple columns associated with each one of sense amplifiers 38 for
communication therewith.
Since ATD 14 detects a transition on only a portion of the address
presented to memory 10 (e.g., the row address), the precharge, sense
amplifier disable, and row decode operations will not be initiated for a
transition in the state of the remainder of the address (i.e, the column
address). This provides the fast access, or cache, mode of operation of
memory 10 constructed according to the instant invention, as changes in
the portion of the address which selects a bit from sense amplifiers 38
(i.e., the "cache" of the memory) does not cause the operation of ATD 14.
Once sense amplifiers 38 have latched therein the data state of the memory
cells in array 22 which are in the selected row, column decoder 18 in
memory 10 is operable to decode the received column address for
communication to buffer 40 and from there to the D and Q terminals. A
change in the column address presented to memory 10 will merely cause such
communication to a different sense amplifier 38, which can be done in a
significantly shorter time than would be required were the precharge, row
decode and sensing operations to be performed. Accordingly, memory 10
provides a fast access, or cache, mode so long as the value of the portion
of the address received by ATD 14 does not change.
In addition to providing a faster access of the desired bit, the access is
performed without requiring the operations of precharge, row decoding and
selection, and sensing of the newly selected row, each of these operations
consuming power. Accordingly, the provision of the fast access, or cache,
mode not only improves the memory performance from a speed standpoint, but
also improves the memory performance relative to overall power
dissipation. The reduced power dissipation will result from the efficiency
of not performing access of the memory array for those cycles which do not
require array access; over the course of a large number of memory
operations, the power dissipation will thus be reduced by a factor which
correlates to the cache hit rate.
The decoding of the column address by column decoder 18 is done statically,
in this first preferred embodiment. It should be noted that a second ATD
circuit may be provided which operates responsive to transitions in the
column address, for selecting the desired one of sense amplifiers 38 to be
accessed. Such a second ATD circuit can control the operation of other
circuitry in memory 10, for example enabling the input/output buffer 40
responsive to a change in the column address, or also initiating dynamic
decoding of the column address by column decoder 18. Provision of such a
second ATD circuit is fully compatible with the invention described
herein, so long as a transition of the column address does not initiate
the operations required for access of memory array 22, such as the
precharge, row decode and selection, and sensing operations described
herein which are initiated by a row address transition detected by ATD 14.
In this first preferred embodiment, ATD 14 is further responsive to signals
presented to terminal EN/DIS.sub.--. In this example, during such time as
terminal EN/DIS.sub.-- is at a low logic level, ATD 14 is disabled from
detecting transitions of the row address, and accordingly no precharge,
row decoding and sensing operations can be initiated. In addition, sense
amplifier latch control circuitry 17 is further responsive to the state of
terminal EN/DIS.sub.--, as will be described below, for causing data
sensed and stored by sense amplifiers 38 to remain there during such time
as the state of terminal EN/DIS.sub.-- remains low, i.e., while ATD 14 is
disabled. Accordingly, memory 10 has a second way by which it can operate
a fast access, or cache, mode. So long as line EN/DIS.sub.-- has disabled
ATD 14, with sense amplifiers 38 retaining the data stored therein, memory
10 will remain in the cache mode with column decoder 18 selecting the
sense amplifiers 38 for external communication responsive to the column
address, regardless of transitions in the row address from the value
selecting the row stored in sense amplifiers 38. It should be noted that a
memory may be constructed according to this invention without the feature
of disabling address transition detection; the feature of disabling ATD 14
provides yet further control of the operation of the memory.
Enable circuitry 12 receives an external chip select signal from terminal
CS, for controlling the operation of the various elements in memory 10
according thereto. Enable circuitry 12 will disable (by connections not
shown in FIG. 1 for the sake of clarity) operative portions of memory 10
in the event that memory 10 is not selected, for example by a low logic
level at terminal CS. As is conventionally done, by way of memory
selection via a chip select signal at terminal CS, multiple ones of
memories 10 may have its address terminals, data terminals and control
terminals connected in parallel, with unselected ones of memories 10
neither affected by nor affecting the operation of the selected ones of
memory 10.
In this embodiment, column decoder 18 is a static column decoder; as is
well known in the art, a static column decoder 18 constantly decodes the
column address presented thereto, so that a transition in the column
address will result, after the time necessary for decoding, in the
immediate selection of a different column in array 22. Static decoding is
preferred in this embodiment for column decoder 18, as it is believed that
the cache access mode performance is maximized by static column address
decoding. However, it should be noted that address transition detection
can also be applied to the column address, in the event that the column
decoding is to be done dynamically. In order to continue to allow the
cache access mode in this arrangement, however, the address transition
detection on the column address must be independent from that which
initiates the precharge and sensing operation (i.e., the row address
transition detection).
For purposes of explaining the construction and operation of memory 10 in
greater detail, FIG. 2 illustrates the operation of a column in array 22,
together with one of sense amplifiers 38 associated with the column The
construction of the column of FIG. 2 is preferred for use in a static
memory 10 constructed according to the invention, but other construction
and arrangements of memory cells 2 with a sense amplifier 38 may of course
be alternatively used in memory 10 according to the invention. The circuit
of FIG. 2 is explained in greater in my copending application Ser. No.
252,287 filed Sep. 30, 1988 and assigned to Texas Instruments Incorporated
Each column in array 22 contains a number of memory cells 2, with each of
memory cells 2 associated with a different row in array 22. Memory cells
in conventional sRAMs are generally constructed of cross-coupled
inverters. The static memory cell 2 of FIG. 2 is of the CMOS variety, with
each inverter comprising an n-channel drive transistor 30 and a p-channel
load transistor 32 having their gates connected together and to the drains
of the transistors 30 and 32 of the opposing inverter in the cell 2. The
sources of the p-channel load transistors 32a and 32b are connected to the
V.sub.dd power supply, and the sources of the n-channel drive transistors
30a and 30b are connected to ground. Each of the columns in array 22 is
associated with a pair of bit lines BL and BL.sub.-- which communicate a
differential signal thereupon corresponding to the data state stored by
the selected memory cell 2. Connection of the memory cells 2 to bit lines
BL and BL.sub.-- is controlled by pass transistors 34 having their
source/drain path connected between the node at the drains of the
transistors 30 and 32 for each of the inverters and complementary bit
lines BL and BL.sub.--, respectively As is typical in conventional sRAM
devices, a word line WL, driven by the output of row decoder and controls
the gate of the pass transistors 34 so that the memory cell 2 associated
therewith will be in communication with the bit lines BL and BL.sub.--
responsive to the word line WL for the particular row being energized by
row decoder 15 according to the row address.
The sense amplifier 38 of FIG. 2 is connected directly to bit lines BL and
BL.sub.-- and, similarly as memory cells 2, consists of a pair of
cross-coupled CMOS inverters. Each inverter has an n-channel drive
transistor 40 and a load device, here consisting of a p-channel transistor
42. The inverters consisting of transistors 40a and 42a and of transistors
40b and 42b have their gates connected together and to the drains of the
opposing inverter in conventional cross-coupled fashion. The sources of
transistors 42a and 42b are biased to V.sub.dd, and the sources of
transistors 40a and 40b are connected to a pass transistor 44, which
controls the biasing of the sources of transistors 40 to ground responsive
to a latch signal SAL received at the gate thereof from sense amplifier
latch control circuitry 17. Accordingly, if a memory cell 2 is connected
to bit lines BL and BL.sub.-- responsive to the activation of a word line
WL, sense amplifier 38 will receive a differential signal on bit lines BL
and BL.sub.-- and, if line SAL is at a high logic level, will latch a
data state corresponding to the stored data state in the selected memory
cell 2.
P-channel transistors 46a and 46b have their source/drain paths connected
between bit lines BL and BL.sub.--, respectively, and V.sub.dd. The gates
of p-channel transistors 46a and 46b receive a signal at line PC.sub.--
from precharge and control circuitry 24. As is indicated by its
nomenclature, line PC.sub.-- carries a signal which, in its active low
logic level, will cause transistors 46a and 46b to conduct, connecting the
V.sub.dd potential to both bit lines BL and BL.sub.-- to precharge them.
Equalization transistor 48 is also a p-channel transistor, and has its
source/drain path connected between bit lines BL and BL.sub.--, with its
gate controlled by line PC.sub.--. Accordingly, during the precharge
operation, transistor 48 is also in the conductive state, in effect
connecting bit lines BL and BL.sub.-- together so that they are
precharged to the same potential. Such equalization of the bit lines is
preferred so that mis-sensing due to bit lines BL and BL.sub.-- having
different potentials at the time that a memory cell 2 is connected thereto
by row decoder 15 is avoided.
As described above, memory 10 constructed according to the invention has
the capability of a fast access, or cache mode, by appropriate control of
the WL, PC.sub.-- and SAL lines. In this embodiment, the signal on line
WL corresponding to the selected row will remain at a high logic level for
so long as the same row address is at the row address terminals, or for so
long as ATD 14 is disabled, so that a write operation performed to the
selected sense amplifier 38 will also effect a write of data to the memory
cell 2 in the selected row associated therewith. Responsive to a row
address transition at such time as ATD 14 is enabled by line EN/DIS.sub.--
at a high level, line WL for all rows must be at a low state prior to
precharge of the bit lines BL and BL.sub.--, so that an indeterminate
state is not written into memory cells 2.
It is preferable that the output of ATD 14 is a pulse having a
predetermined pulse width which occurs upon the detection of a row address
transition. For generating the control signal on line PC.sub.--, ATD 14
can, for example, generate a low logic level pulse on line 6 responsive to
a row address transition with terminal EN/DIS.sub.-- at a high logic
level, where line 6 directly drives the gates of transistors 46 and 48,
accomplishing the precharge and equalization for each of the columns in
array 22. Of course, other circuitry for generating the necessary
PC.sub.-- signal responsive to a detected row address transition can
alternatively be used. With no row address transition detected, or with
ATD 14 disabled by the state of EN/DIS.sub.--, line PC.sub.-- will remain
at a high logic level.
It should be noted that line PC.sub.-- can alternatively remain at an
active low state during the entire cycle, if transistors 46 and 48 are
sufficiently small that they will not upset the ability of sense amplifier
38 to sense and latch the data state of memory cell 2. Such an arrangement
would of course reduce the control circuitry necessary for control of the
PC.sub.-- line, but would increase the power dissipation of memory 10,
and would also tend to degrade the amplitude of the differential signal on
bit lines BL and BL.sub.--.
In order to operate according to the invention, sense amplifier latch
control circuitry 17 must control line SAL so that sense amplifier 38 is
disabled from bit lines BL and BL.sub.-- during such time as the memory
is being precharged, and during the decoding of the row address and
energizing of the selected word line WL. Accordingly, line SAL is to be
driven low after a row address transition while ATD 14 is enabled. In
addition, in order to effect the fast access mode according to the
invention, line SAL is to be at a high logic level, enabling sense
amplifiers 38, during such time as no row address transion has been
received, and during such time as ATD 14 is disabled. In addition, it is
preferable in this embodiment that the data latched by sense amplifiers | | |
