Simultaneous voice and data system using the existing two-wire inter-face

What is claimed is:

1. A data adapter for simultaneously providing a low speed channel, a first high speed channel, and a second high speed channel over a two wire connection, said two wire connection connects said data adapter to a telephone system, said data adapter comprising:

a line transceiver means connected to said two-wire connection, said line transceiver means provides a full duplex transmission link with said telephone system over said two-wire connection, said full duplex transmission link comprised of said low speed channel, said first high speed channel, and said second high speed channel;

a protocol controller means connected to said line transceiver means, said protocol controller means performs a packet protocol on said low speed channel and, said protocol controller means routes said first high speed channel to a telephone interface means and said second high speed channel to a rate adapter means;

said telephone interface means connected to said protocol controller means, said telephone interface means converts data between said first high speed channel and a telephone instrument;

said rate adapter means connected to said protocol controller means, said rate adapter means converts data between said second high speed channel and a data processing equipment, said rate adapter means performs a rate adaption protocol while converting said data between said second high speed channel and said data processing equipment, said rate adapter means including a signal processor means arranged to perform said rate adaption protocol; and

a processor means connected to said line transceiver means, said protocol controller means, said telephone interface means, and said rate adapter means, said processor means arranged to receive and transmit messages through said protocol controller means over said low speed channel to said telephone system, and in response to information received over said low speed channel, and information received from said rate adapter means, said processor means controls said data adapter.

2. A data adapter as claimed in claim 1, said data adapter further comprising:

a tone generator means connected to said protocol controller means, said tone generator means creates sounds used to convey information; and

a speaker arranged to make said sounds from said tone generator means audible.

3. A data adapter as claimed in claim 1, said data adapter further comprising:

a display means connected to said processor means, said display means arranged to convey visual information;

a keyboard means connected to said processor means, said keyboard means arranged to allow information to be entered.

4. A data adapter for simultaneously providing a low speed channel, a first high speed channel, and a second high speed channel over a two wire connection, said two wire connection connects said data adapter to a telephone system, said data adapter comprising:

a line transceiver means connected to said two-wire connection, said line transceiver means provides a full duplex transmission link with said telephone system over said two-wire connection, said full duplex transmission link comprised of said low speed channel, said first high speed channel, and said second high speed channel;

a protocol controller means connected to said line transceiver means, said protocol controller means performs a packet protocol on said low speed channel and, said protocol controller means routes said first high speed channel to a telephone interface means and said second high speed channel to a rate adapter means;

said telephone interface means connected to said protocol controller means, said telephone interface means converts data between said first high speed channel and a telephone instrument;

said rate adapter means connected to said protocol controller means, said rate adapter means converts data between said second high speed channel and a data processing equipment, said rate adapter means performs a rate adaption protocol while converting said data between said second high speed channel and said data processing equipment, said rate adapter means including a signal processor means arranged to perform said rate adaption protocol, said rate adapter means including a Read Only Memory (ROM) means for storing a rate adaption protocol program used by said signal processor means, and a Random Access Memory means used by said signal processor means for temporary storage; and

a processor means connected to said line transceiver means, said protocol controller means, said telephone interface means, and said rate adapter means, said processor means arranged to receive and transmit messages through said protocol controller means over said low speed channel to said telephone system, and in response to information received over said low speed channel, and information received from said rate adapter means, said processor means controls said data adapter.

5. A data adapter as claimed in claim 4, said rate adapter means further comprising:

a first serial transceiver means connected between said signal processor means and said data processing equipment, said first serial transceiver means converts data between said signal processor means and said data processing equipment;

a parallel to serial converter means connected to said signal processor means, said parallel to serial converter means accepts parallel data from said signal processor means and converts said parallel data to serial data; and

a second serial transceiver means connected between said signal processor means and said parallel to serial converter means, said second serial transceiver means arranged to receive said serial data and extract a complete data byte from said serial data, said complete data byte is then converted to a parallel format and transmitted to said signal processor.

6. A data adapter as claimed in claim 4, said rate adapter means further comprising an interchange circuit means connected to said signal processor means, said interchange circuit means monitors a first plurality of signals between said data adapter and said data processing equipment and generates a second plurality of signals between said data adapter and said data processing equipment, where said first plurality of signals and said second plurality of signals indicate whether data can be exchanged between said data adapter and said data processing equipment.

7. A data adapter as claimed in claim 4, said rate adapter means further comprising:

a transmit First-In-First-Out (FIFO) means arranged to transmit data from said signal processor means over said second high speed channel; and

a receive FIFO means arranged to receive data from said second high speed channel and send said received data to said signal processor means.

8. A data adapter as claimed in claim 4, said telephone interface means further comprising:

a combo means for converting a received analog signal to a transmitted digital signal, and converting a received digital signal to a transmitted analog signal, said combo means receives said received analog signal and transmits said transmitted analog signal to said telephone instrument, said combo means is further arranged to communicate with said processor means;

a Dual Tone Multi-Frequency (DTMF) receiver for detecting and decoding a received pair of tones, said DTMF received receives said pair of tones from said telephone instrument and transmits said decoding to said processor means;

a serial-to-serial converter means for converting said transmitted digital signal to said first high speed channel and converting said first high speed channel to said received digital signal; and

a clock generator means for generating a plurality of signals used by said serial-to-serial converter means.

9. A data adapter for simultaneously providing a low speed channel, a first high speed channel, and a second high speed channel over a two wire connection, said two wire connection connects said data adapter to a telephone system, said first high speed channel carries a digitized analog signal from, and to, a telephone instrument and said second high speed channel carries data from, and to, a data processing equipment, said data adapter comprising:

a line transceiver means connected to said two-wire connection, said line transceiver means provides a full duplex transmission link with said telephone system over said two-wire connection, said full duplex transmission link comprised of said low speed channel, said first high speed channel, and said second high speed channel;

a control interface means connected to said line transceiver means, said control interface means arranged to provide a communications channel to said line transceiver;

a protocol controller means connected to said line transceiver means, said protocol controller means performs a packet protocol on said low speed channel and, said protocol controller means routes said first high speed channel to a telephone interface means and said second high speed channel to a signal processor means;

said telephone interface means connected to said protocol controller means, said telephone interface means converts data between said first high speed channel and said telephone instrument;

said signal processor means connected to said protocol controller means, said signal processor means arranged to perform a rate adaption protocol on said second high speed channel and said data from, and to, said data processing equipment;

a first serial transceiver means connected between said signal processor means and said data processing equipment, said first serial transceiver means converts data between said signal processor means and said data processing equipment;

a parallel to serial converter means connected to said signal processor means, said parallel to serial converter means accepts parallel data from said signal processor means and converts said parallel data to serial data;

a second serial transceiver means connected between said signal processor means and said parallel to serial converter means, said second serial transceiver means arranged to receive said serial data and extract a complete data byte from said serial data, said complete data byte is then converted to a parallel format and transmitted to said signal processor;

an interprocessor interface means connected to said signal processor means, said interprocessor interface means arranged to provide a communication channel to said signal processor means; and

a processor means connected to said control interface means, said protocol controller means, said telephone interface means, and said interprocessor interface means, said processor means arranged to receive and transmit messages through said protocol controller means over said low speed channel to said telephone system, and in response to information received over said low speed channel, and information received from said signal processor means through said interprocessor means, said processor means controls said data adapter, said processor means controls said line transceiver means through said control interface means.

10. A data adapter as claimed in claim 9, said data adapter further comprising:

a tone generator means connected to said protocol controller means, said tone generator means creates sounds used to convey information; and

a speaker arranged to make said sounds from said tone generator means audible.

11. A data adapter as claimed in claim 9, said data adapter further comprising:

a display means connected to said processor means, said display means arranged to convey visual information;

a keyboard means connected to said processor means, said keyboard means arranged to allow information to be

12. A data adapter as claimed in claim 9, said data adapter further comprising:

a transmit First-In-First-Out (FIFO) means arranged to transmit data from said signal processor means over said second high speed channel; and

a receive FIFO means arranged to receive data from said second high speed channel and send said received data to said signal processor means.

13. A data adapter as claimed in claim 9, said telephone interface means further comprising:

a combo means for converting a received analog signal to a transmitted digital signal, and converting a received digital signal to a transmitted analog signal, said combo means receives said received analog signal and transmits said transmitted analog signal to said telephone instrument, said combo means is further arranged to communicate with said processor means;

a Dual Tone Multi-Frequency (DTMF) receiver for detecting and decoding a received pair of tones, said DTMF receiver receives said pair of tones from said telephone instrument and transmits said decoding to said processor means;

a serial-to-serial converter means for converting said transmitted digital signal to said digitized analog signal and converting said digitized analog signal to said received digital signal; and

a clock generator means for generating a plurality of signals used by said serial-to-serial converter means.

Description Submit all comments and votes

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is related to the following co-pending U.S. patent applications all being assigned to the same assignee, entitled:

"A NETWORK INDEPENDENT CLOCKING CIRCUIT WHICH ALLOWS A SYNCHRONOUS MASTER TO BE CONNECTED TO A CIRCUIT SWITCHED DATA ADAPTER", Ser. No. 07/615,524 filed on Nov. 19, 1990;

"A CIRCUIT AND METHOD OF HANDLING ASYNCHRONOUS OVERSPEED", Ser. No. 07/615,525 filed on Nov. 19, 1990;

"A METHOD OF IMPLEMENTING ECMA 102 RATE ADAPTION", Ser. No. 07/615,661 filed on Nov. 19, 1990; and

"A METHOD OF IMPLEMENTING ECMA 102 RATE DEADAPTION", Ser. No. 07/617,848 filed on Nov. 19, 1990.

FIELD OF THE INVENTION

The present invention relates in general to telecommunication systems, and more particularly a data adapter which simultaneously provides a voice and high speed data channel over an existing two-wire interface.

BACKGROUND OF THE INVENTION

Prior to the present invention, high speed data could only be provided by special leased lines. Even with these special leased lines, data rates were limited to relatively low baud rates, (i.e. <19.2 Kbaud). Nor did these special leased lines provide voice capacity. It was necessary to bring in tie-lines to achieve the higher data rate and Local Area Networks (LAN) to achieve substantially higher data rates.

A LAN system can provide a very high data rate but requires that each location be connected to a new, special LAN wire. This makes LANs only practical for a small area such as an office building, hence, the name local area networks.

Both tie-lines and leased lines overcome the local restriction but have there own restrictions. Unless the telephone company has spare special lines running between the Central Office (CO) and the location desiring service, new lines must be laid. The laying of new lines is generally an expensive process.

It therefore becomes the object of the present invention to provide an apparatus which simultaneously provides voice and high speed data channels over the existing tip-and-ring two-wire interface.

SUMMARY OF THE INVENTION

In order to accomplish the object of the present invention there is provided a data adapter for simultaneously providing a low speed channel, a first high speed data channel, and a second high speed channel over a two wire connection. The two wire connection connects the data adapter to a telephone system. The data adapter consists of:

A line transceiver connected to the two-wire connection; the line transceiver provides a full duplex transmission link with the telephone system over the two-wire connection. The line transceiver is controlled through a control interface. A telephone instrument transmits and receives information from a telephone interface.

A signal processor that performs a rate adaption and de-adaption protocol program on the second high speed channel and the data from/to the data processing equipment. A serial transceiver connected between the signal processor and the data processing equipment, where the serial transceiver converts data between the signal processor and the data processing equipment. A parallel to serial converter connected to the signal processor, the parallel to serial converter accepts parallel data from the signal processor and converts the parallel data to serial data. A serial transceiver connected between the signal processor and the parallel to serial converter, the serial transceiver receives the serial data and extract a complete data byte from the serial data, the complete data byte is then converted to a parallel format and transmitted to the signal processor.

A protocol controller that performs a packet protocol on the low speed channel, and routes the first high speed channel to the telephone interface and the second high speed channel to the signal processor.

A processor that receives and transmits messages through the protocol controller over the low speed channel to the telephone system, and in response to information received over the low speed channel, alternatively information received from the signal processor, the processor controls the data adapter.

DESCRIPTION OF THE DRAWINGS

A better understanding of the invention may be had from the consideration of the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of the Data Adapter in accordance with the present invention.

FIGS. 2A and 2B are a more detailed block diagram of the Data Adapter of FIG. 1.

FIG. 3 is a block diagram of the Data Adapter's phone interface.

FIG. 4 is a schematic diagram of the serial interface for the Data Adapter's phone interface.

FIG. 5 is a block diagram of the Rate Adapter

FIG. 6 is a block diagram of the rate adaption/de-adaption process.

FIG. 7 is a state diagram of the rate adaption process for low speed.

FIG. 8 is a state diagram of the rate adaption process for high speed.

FIG. 9 shows some of the messages passed between the RA, MP, and the CO during a normal data call.

FIG. 10 shows a timing diagram for the generation of the RA2 data clock (SFCLK).

FIG. 11A is a schematic diagram of the Start/Stop bit circuitry.

FIG. 11b is a schematic diagram of the Start/Stop bit circuitry.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Introduction

The present invention requires only two-wires, yet, provides a total of four channels, two 64 Kbps channels (one voice and one data), a 16 Kbps channel for communications between the DA and the CO, and a 8 Kbps auxiliary channel for communications with other devices on the line, i.e. repeaters.

Turning now to FIG. 1 a general description of the Data Adapter will be given.

The DA simultaneously provides a high-speed data channel and a voice channel over the existing two-wire interface. The data interface 107 supports either synchronous or asynchronous data, in a V.35 or RS-232 EIA format. The voice channel is provided by a standard DTMF phone 116. Calls can be originated or terminated by using either the attached computer equipment 115, the attached phone instrument 116, or the DA's keypad 113.

Data from DATA INTERFACE 107 is passed to RA 106 where the data is "Rate Adapted" in accordance to the European Computer Manufacturers Association (ECMA) standard, onto one of the 64 Kbps channels. The voice signal is converted to a 64 Kbps Pulse Coded Modulation (PCM) signal by PHONE INTERFACE 109 and occupies a second 64 Kbps channel. Both 64 Kbps channels are multiplexed along with data from MICROPROCESSOR 112 for the 16 Kbps channel by MUX 118 and then shifted into Digital Subscriber Controller (DSC) 104. These three channels are converted to an analog signal suitable for transmission over a four-wire interface, one such format is the Integrated Services Digital Network (ISDN) S interface signal. The analog signal from the DSC is received by Digital Exchange Controller (DEC) 103 and converted back to a digital Time Division Multiplexed (TDM) signal. At this point, a 64 Kbps control channel from C-CHANNEL INTERFACE 108 is multiplexed into the TDM data stream. The C-CHANNEL is used to control and determine status of LINE INTERFACE 102. Note: the 8 Kbps auxiliary channel is part of this control channel.

The digital TDM data stream from DEC 103 and the 8 Kbps auxiliary channel are converted into an appropriate signal for transmission over a twisted-pair line. The signal from LINE INTERFACE 102 is transmitted through a PROTECTION circuit 101 to the Central Office (CO), where an identical line interface receives the signal and reconstructs the digital data.

Information received from the CO is processed in the reverse order of that stated above.

The DA includes a LOUDSPEAKER 105 for conveying call progress tones, ring tones, etc to the user. A KEYPAD 113 and mode select switches allow for various call-setup and programming alternatives. LEDs 114 are used to convey information about the status of the DA.

Functionally, the DA consists of two separate circuits: The Call Processing Computer (MP) and the Rate Adapter (RA). The former operates under control of MICROPROCESSOR 112; the later operates under a digital signal processor. The two intelligent processors communicate with each other via a bi-directional 8-bit registers. Each circuit will be described separately in the following sections.

Simultaneous voice/data involves a PHONE INTERFACE 109 to the DA to allow the connection of a standard DTMF phone as shown in FIG. 1. The phone is used for the voice connection as well as for tone dialing of voice calls. Because the appropriate voltage required for ringing is not available, the speaker on the DA itself is used for voice call alerting as well as data call alerting (separate ring frequencies are used to distinguish between the two types of calls). The PHONE INTERFACE is contained on a Data Adapter Phone Interface (DAPI) baby board.

Data Interface

The RS-232C/V.35 interface (DATA INTERFACE 107) circuits reside on DARI/DAVI baby boards, respectively. Note: only a RS-232C or V.35 is equipped at any one time. Serial communication to/from RS-232C and V.35 is controlled by RA 106. Data transfer rate is switch selectable via DIP-switches mounted on KEYPAD 113 baby board, or, automatic if Data Adapter operates in auto-baud mode. The RS-232C baby board is strap selectable to operate in one of the following modes:

DTE synchronous

DTE asynchronous

DCE synchronous

DCE asynchronous

The V.35 baby board is strap selectable to operate in one of the following modes:

DTE synchronous

DCE synchronous

Keypad Input

The KEYPAD 113 resides on the Data Adapter Keypad Interface (DAKI) baby board and is connected to a keypad encoder 74C922 chip. The encoder provides two key roll-over, debounce, and code conversion functions. When a key is pressed, the encoder registers the key and then issues an interrupt to MICROPROCESSOR 112 via the DSC's 104 hook switch line. A series of DIP switches also reside on the DAKI but are read by RA 106. These DIP switches are used to configure the DA.

Power Supply

The POWER SUPPLY 110 for the DA automatically allows for two different input voltages. For general usage, the input voltage is 24 VAC from a wall mounted transformer. If operation of the DA is desired during AC power outages (e.g. to enable emergency voice calls), then the power input can be -48 VDC from a centralized, battery backed-up power source. Internally, the power supply provides +/-5 VDC, +/-15 VDC, and -48 VDC.

Central Office Interface

Still referring to FIG. 1, the LINE INTERFACE 102 circuit is comprised of a Digital Interface Circuit (DIC) and associated circuitry, and is transformer coupled to a two wire line to the CO. The DIC provides a high-speed, full duplex digital transmission link using echo-cancelling techniques. This circuit in turn interfaces to the DEC 103 and DSC 104. The later device provides an interface to the SPEAKER 105 and PHONE INTERFACE 109.

Two channels at 64 Kbps, one channel at 16 Kbps, and an 8 Kbps maintenance or utility channel are transported between the DIC and equivalent circuit at the CO. One 64 Kbps channel is allocated for circuit switch data transmission, the other is for voice transmission. The 16 Kbps channel is used for the interchange of information between the CO and DA for call setup, release, ringing, call progress tone, etc..

The DIC chip, a MITEL 8972, operates in the slave mode. Phase Locked Loop (PLL) 117 locks onto the C4 (4.096 Mhz) clock from the DIC and generates a 1.344 Mhz for use by the baud rate generator in RA 106. This allows the clock signal and thus the USER equipment 115 to be synchronized to the CO. The DIC's C-CHANNEL is used for transferring control and status information between the DIC and MICROPROCESSOR 112. All of the DIC's internal registers ar accessed through C-CHANNEL INTERFACE 108.

C-CHANNEL INTERFACE 108 is described in detail in U.S. Pat. No. 5,023,870, "AN INTERFACE CIRCUIT FOR DATA TRANSMISSION BETWEEN A MICROPROCESSOR SYSTEM AND A TIME-DIVISION-MULTIPLEXED SYSTEM". Additional information about the DIC chip can be found in MITEL's data book issue 5.

Digital Exchange and Subscriber Controllers (DEC, DSC)

The two circuit blocks are implemented with two VLSI chips from AMD, a 79C30 and a 79C31A (DSC and DEC respectively). As indicated in FIG. 1, the connection between the two parts is functionally an "S" reference point, as defined in CCITT recommendations for ISDN. This is a four-wire interconnection, with a pair for each direction and a predefined data rate and framing format. The principal function of the DEC is to adapt the "T" format data stream at the DIC interface to the "S" reference.

The DSC extracts two 64 Kbps (Bd and Be) channels (channels Bd and Be are assigned for data and voice, respectively) and provides them to the external data and voice circuits. The two channels can be programmed for connection to either one of the B1, B2 channels of the Line Interface Unit (LIU), inside the DSC itself.

The DSC also provides D channel features such as X.25 packet protocol, and interfaces to MICROPROCESSOR 112 for further D channel data processing. It also provides an analog interface to LOUDSPEAKER 105 for conveying audible signal information such as call progress tones, ring tones, etc., all under MICROPROCESSOR 112 control. Operation and release of keys on the keypad generate MICROPROCESSOR 112 interrupt via the HSW (Hook-SWitch) input to the DSC. Additional information can be obtained from AMD.

Rate Adapter Block

FIG. 2 shows the Rate Adapter RA section in more detail. A high level description of data flow in the RA will be given now. Data from the far end enters the RA from DSC 20 as explained above. This data is first converted from serial to parallel data by SERIAL-TO-PARALLEL CONVERTER 21. The parallel data is then loaded into RECEIVE FIFO 22. DSP 23 reads the data from RECEIVE FIFO 22 and "De-Adapts" the data based on ECMA-102. If an asynchronous rate is being used, DSP 23 writes the data into PARALLEL-TO-SERIAL CONVERTER 24. Data from PARALLEL-TO-SERIAL CONVERTER 24 is shifted into ASTRO#2 25 where the start and stop bits are removed. Once ASTRO#2 25 has reconstructed a data byte, DSP 23 is interrupted. The DSP then reads the data byte from ASTRO#2 25. The data is written to ASTRO#1 26 if ASTRO#1 26 is ready for more data. If ASTRO#1 26 is not ready, the data byte is stored in RAM until ASTRO#1 is ready. Synchronous rates do not undergo the bit striping.

In the other direction, data is first received by ASTRO#1 26 where the start and stop bits are removed. The DSP 23 reads the data from ASTRO#1 26 and "Adapts" it based on ECMA-102. This rate adapted data is then written into TRANSMIT FIFO 28. At the appropriate time, the data is transfer from TRANSMIT FIFO 28 into PARALLEL-TO-SERIAL CONVERTER 29. One, two, four, or eight bits are shifted out of PARALLEL-TO-SERIAL CONVERTER 29 into DSC 20 each frame.

Microprocessor

Still referring to FIG. 2 the MICROPROCESSOR (MP) 203 is an Intel 80C88, and operates at approximately 8 Mhz with four clock cycles per read/write operation, some slower devices may be accessed in five or six clock cycles. MP 203 provides a 20 bit address bus, of which the low order byte is multiplexed with data. EPROM 206 and RAM 208 are provided for program and data storage.

The 82C84 CLOCK GENERATOR 202 uses an external 24.576 Mhz crystal input which is divided by three to provide an 8.192 Mhz clock described above. The 24.576 Mhz out of the 82C84 OSC pin is divided by CLOCK DIVIDER 210 to supply 12.288 Mhz clock required by the DSC chip. On the Data Adapter Phone Interface (DAPI) baby board (802 of FIG. 3), this clock is divided further to supply 1.536 Mhz clock required by the COMBO chip.

The 80C88 is interrupt driven via Programmable lo Interrupt Controller (PIC) 211. The eight interrupt inputs to PIC 211, which are individually maskable, are

Loss of sync from DIC

DSC interrupt

DEC interrupt

PIT timer 0 output interrupt

PIT timer 1 output interrupt

PIT timer 2 output interrupt

DSP interrupt

Utility channel interrupt

The 80C88 also interfaces to a number of on-board peripheral devices such as PIT 205, PIC 211, DEC, DSC, LED 207 etc. and several external baby boards such as DAKI (keypad 207) and DAPI (phone).

Interprocessor Register

MICROPROCESSOR 203 communicates with DSP 23 of the RA section through INTERPROCESSOR REGISTER 212. INTERPROCESSOR REGISTER 212 is a bi-directional eight bit register mapped into the I/0 space of both MICROPROCESSOR 203 and DSP 23. Seven bits are used to convey information and the eighth bit is used as an interrupt signal. Therefore, for example, when MICROPROCESSOR 203 sends a message to DSP 23, it writes a data byte into INTERPROCESSOR REGISTER 212 with the eighth bit set to a logic one. The logic one generates an interrupt to the DSP who then reads the message. Messages from the DSP to the MICROPROCESSOR are transferred in the same manner. Some of the messages transfer between MICROPROCESSOR 203 (MP) and DSP (RA) are shown in TABLE 1.

TABLE 1 ______________________________________ Interprocessor Messages ______________________________________ MP to RA D7 . . . D0 Reset 1001 0000 Perform Self Check 1001 0001 Set Operating Mode 1001 0010 (i.e. read DIP switches) Set Interchange Circuit Outputs (0 . . . 15) 1110 xxxx Read Interchange Circuit Inputs 1100 0000 Connect to Line 1100 0001 Disconnect from Line 1100 0010 Report Operating State 1100 0100 Echo Back Command(s) 1010 1010 1101 0101 RA to MP Reset Complete (0 . . . 1) 1001 000x {0 = Fail, 1 = Success} Self Check Complete (0 . . . 1) 1001 001x {0 = Fail, 1 = Success} Accept 1001 0100 Reject 1001 0101 Interchange Circuit Leads Status (0 . . . 15) 1110 xxxx Operating State (1 . . . 9) 1100 xxxx Echo Back Command(s) 1010 1010 1101 0101 ______________________________________

A short description on the above messages:

RESET: This is a command by the MP for the RA to perform a complete reset. This routine will mask all interrupts and return with an indication to jump to the reset routine.

PERFORM SELF CHECK: This is similar to the above command.

SET OPERATING MODE: This is a command to read the DIP switches to determine the operating mode. If the mode changed, this may cause a reset.

SET INTERCHANGE CIRCUIT OUTPUT LEADS: This command informs the RA to take the information included in the message and set the appropriate interchange leads. A "0" corresponds to the ON condition and a "1" to the OFF condition. Which leads are set is dependent upon the DCE/DTE operating mode and shown below:

______________________________________ Interchange Circuit Outputs Bit # DCE Mode DTE Mode ______________________________________ 0 106 105 1 107 108.2 2 109 x 3 125 x ______________________________________

READ INTERCHANGE CIRCUIT INPUT LEADS: This command informs the RA to read the interchange lead inputs and report back with their state. This routine will read the particular leads shown below, enqueue a message back to the MP with the results, and set the C2P Message Flag. MP will monitor the flag for eventual transmission of the message.

______________________________________ Interchange Circuit Outputs Bit # DCE Mode DTE Mode ______________________________________ 0 105 106 1 108.2 107 2 x 109 3 x 125 ______________________________________

CONNECT TO LINE: This command instructs the RA to connect to the B-Channel. This routine will set the Local Connect Request Event flag which will be checked by MP.

DISCONNECT FROM LINE: This is the reverse of the above command.

REPORT OPERATING STATE: This command informs the RA to read the operating state and report back with the state.

ECHO BACK: These commands are used by the MP to check for stuck bits in the interprocessor registers. The MP will send one of the two commands, and the RA will respond with the identical bit pattern response message.

This list is not meant to be exhaustive: additional messages are needed to convey digit information, call progress messages, baud rate, etc. This type of information is generally application specific and can be implemented as required for each individual application.

Simultaneous Voice/Data

Referring to FIGS. 3 and 4, the simultaneous voice/data feature involves a line interface to the DA to allow the connection of a standard DTMF phone instrument to the DA. This phone is used for the voice connection as well as for tone dialing of voice calls. Because the appropriate voltage required for ringing are not available, the speaker on the DA itself is used for voice call alerting as well as data call alerting (separate ring frequencies are used to distinguish between the two types of calls).

To provide the voice connection, a separate Subscriber Line Interface Circuit (SLIC) 801 resides on the DA. The voice port of the DSC cannot be used due to limitations within the DSC chip with only one analog channel. These limitations would cause interference with a data call setup during the time when a voice call is in progress.

The implementation of SLIC 801 includes such items as the CODEC, filter, and control, and is taught in patent application Ser. No. 445,517, "A SOLID STATE TELEPHONE LINE CIRCUIT". Data from SLIC 801 is converted from the 1.536 Mbps to the 192 Kbps of the DSC by SERIAL-TO-SERIAL SHIFT REGISTER 803. Data in the opposite direction is converted by SERIAL-TO-SERIAL SHIFT REGISTER 804.

Because a standard DTMF phone is attached to the DA rather than just a handset, the phone itself is used for "dialing". Therefore, a DTMF receiver 805 is required to detect and decode the dialing tones.

FIG. 4 shows the SERIAL-TO-SERIAL REGISTERS as a chain of D-FFs with a common clock input. This arrangement allows data to be clocked into the chain where it is stored until it is clocked out. As a result, while data is being clocked into SERIAL-TO-SERIAL REGISTER 915-923, "DON'T CARE" data is being shifted out.

The control generator's (901-914) primary function is to generate signals CLK 2 and CLK 3 at the correct time and with the correct frequency. SLIC 801 has a bit rate of 1.536 MBPS and DSC has a bit rate of 192 Kbps. In other words, SLIC 801 has 24 time-slots each with a data rate of 64 Kbps and DSC has 3 time-slots each with a data rate of 64 Kbps. Time-slot #1 of SLIC 801 is mapped into time-slot #2 of DSC. That is, data is converted between SLIC 801 time-slot #1 and DSC time-slot #2.

At the start of a frame, signals DFS1 and DFS2 (Delayed Frame-Start) are logic low and will remain low for eight clock cycles of BCLK 2 (Bit rate Clock for DSC). The signal BCLK 2 is blocked from clocking the SERIAL-TO-SERIAL REGISTERS by GATES 911 and 912 while DFS1 and DFS2 signals are a logic low.

GATE 910 will pass BCLK 1 (Bit rate Clock for SLIC 801) only when the signal -TIME-SLOT is a logic low. Note: the -TIME-SLOT signal is generated by SLIC 801. Once the signal -TIME-SLOT becomes a logic low, GATE 913 and 914 generate signals CLK 2 and CLK 3 respectively. The signal -TIME-SLOT remains a logic low for exactly eight clock cycles of BCLK 1. During this time eight data bits are shifted into D-FFs 915-922 and eight data bits are shifted out of D-FFs 925-932.

When the signal -TIME-SLOT returns to a logic high, the output of D-FF 922 represents the first bit shifted in from PCMX and the output of D-FF 932 represents the last bit shifted out to PCMR. Also, CLK 2 and CLK 3 are forced to logic high and logic low respectively.

Some time after -TIME-SLOT has returned to a logic high, the signal FRAME-START (SFS, from DSC) will have propagated through D-FFs 901-909. At this time DFSI and DFS2 will change to a logic high allowing BCLK 2 to pass through GATES 911 and 912. Because -TIME-SLOT is a logic high, the output signals of GATES 911 and 912 will pass through GATES 913 and 914 to become CLK 2 and CLK 3 respectively. Signals DFSI and DFS2 re