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Description  |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an arithmetic unit used in e.g., a digital
still camera, a facsimile telegraph, a color copying machine, a visual
telephone, etc. and performing an orthogonal transformation such as a
discrete cosine transformation (called a DCT or a DCT-transformation in
the following description) and a discrete sine transformation (called a
DST or a DST-transformation in the following description) for compressing
and extending a color image.
2. Description of the Related Art
Various kinds of systems for coding a color still image are generally
searched and developed. The adoption of an adaptive discrete cosine
transformation (called an ADCT or simply a DCT in the following
description) was determined as an international standard of the above
coding systems by Joint Photographic Export Group (called JPEG in the
following description) in October, 1989. A processing of this adaptive
discrete cosine transformation will next be schematically described.
In DCT-processing and IDCT-processing, it is necessary to perform 64
multiplying operations with respect to all input data and DCT-processing
coefficients composed of an (8.times.8) matrix, and perform 56 adding
operations with respect to the multiplied results. Accordingly, a
processing time required to perform ADCT-processing including a memory
operation with respect to a memory is longer than a processing time from a
charge coupled device to one of page buffers. Therefore, it is necessary
to dispose a memory for temporarily storing color and brightness
information of one photographed image picture, circuit elements
corresponding to the respective page buffers, and a frame memory. For
example, in a still video camera, it is necessary to dispose a memory
having a capacity of 7.5M bits with respect to one picture. Accordingly,
there is a problem that the size of a circuit structure of the entire
orthogonal transformation arithmetic unit is increased.
When an image is generally coded and coded data are reproduced as an
original image, there is a case in which the size of an image obtained by
the coded data is reduced or enlarged in comparison with the original
image. In such reducing and enlarging processings, inverse orthogonal
transformation processing is performed with respect to orthogonally
transformed data and these data are reproduced as the original image.
Thereafter, the reducing and enlarging processings are performed with
respect to the reproduced data. When the image is reproduced and the
reducing and enlarging processings are further performed with respect to
the reproduced image, it is necessary to separately dispose a processing
unit for performing the reducing and enlarging processings. Further, there
is a problem that a processing time is further increased by separately
disposing such a processing unit for performing the reducing and enlarging
processings.
Further, the general orthogonal transformation arithmetic unit for
performing DCT-processing and inverse DCT-processing has a DCT-processing
section and an inverse DCT-processing section. Two main arithmetic
circuits similarly operated, etc. are disposed in the DCT-processing
section and the inverse DCT-processing section. An area for these main
arithmetic circuits amounts to about 90 percent of an area for a
semiconductor circuit chip constituting a DCT/inverse DCT processor.
Therefore, the size of a circuit structure is increased by these two main
arithmetic circuits.
Accordingly, the circuit structure is large-sized in the general orthogonal
transformation arithmetic unit for performing the DCT/inverse
DCT-processings.
To change data compressibility, it is sufficient to change the number of
nonzero values with respect to quantized image component data. Namely, it
is sufficient to move a zero boundary region having only quantized value
zero and change a quantizing coefficient .alpha..
When the quantizing coefficient .alpha. is set to a value close to zero,
the quality of a reproduced image is improved, but the amount of image
data is correspondingly increased, thereby reducing the data
compressibility. The reduction of the data compressibility means that the
data compressibility is bad and close to one. In contrast to this, when
the quantizing coefficient .alpha. is close to one, the quality of a
reproduced image is reduced, but the data compressibility is improved.
Thus, it is possible to determine superiority or inferiority of the
quality of the reproduced image by changing the quantizing coefficient
.alpha.. When the data compressibility is reduced, the number of sheets of
still images stored to one memory medium is reduced although the image
quality is improved. In contrast to this, when the data compressibility is
increased, the number of sheets of images stored to the memory medium can
be increased although the image quality is reduced.
The above description relates to one image block within one image. When the
above-mentioned processing is performed with respect to the one image, the
above-mentioned operations are performed with respect to 5400 image blocks
constituting the one image.
The above description relates to a process for storing a photographed image
to the memory medium. A reproduced image with respect to such a stored
image can be obtained by a process completely reverse to the image storing
process.
In a general apparatus for compressing and extending a color image by using
the DCT-processing, there is no orthogonal transformation arithmetic unit
having the relation between the quantizing coefficient .alpha., the image
quality and the number of sheets of stored images.
SUMMARY OF THE INVENTION
It is therefore a first object of the present invention to provide an
orthogonal transformation arithmetic unit having a small-sized circuit
structure.
A second object of the present invention is to provide an orthogonal
transformation arithmetic unit in which the reducing and enlarging
processings of an image are simultaneously executed in an inverse
orthogonal transformation circuit for reproducing orthogonally transformed
data as an original image instead of a separate unit for performing the
reducing and enlarging processings so that no unit for reduction and
enlargement is required and a processing time for reduction and
enlargement can be reduced.
A third object of the present invention is to provide an orthogonal
transformation arithmetic unit having a small-sized circuit structure and
performing DCT-processing or DCT/inverse DCT-processings.
A fourth object of the present invention is to provide an orthogonal
transformation arithmetic unit in which a quantizing coefficient .alpha.
can be changed by setting the number of sheets of images stored to a
recording medium so that the quality of an image stored to the memory
medium is changed.
In accordance with a first structure of the present invention, the above
objects can be achieved by an orthogonal transformation arithmetic unit
for performing a discrete cosine transformation with respect to a digital
signal and compressing discrete cosine transformed data by quantizing and
Huffman-coding processings thereof, the orthogonal transformation
arithmetic unit in Huffman-coding the compressed data and demodulating the
Huffman-decoded data to a digital signal by performing inverse
quantization and an inverse discrete cosine transformation with respect to
the Huffman-decoded data, the orthogonal transformation arithmetic unit
comprising a memory section for storing one line block of image data of
brightness and color signals converted to digital signals; and a section
for processing the discrete cosine transformation and having a
preprocessing circuit for performing adding and subtracting operations
with respect to the image data read out of the memory section such that
some values of discrete cosine transformation coefficients used in the
discrete cosine transformation are partially set to zero.
In such a first structure, the discrete cosine transformation processing
section performs the discrete cosine transformation with respect to data
obtained by performing the adding and subtracting operations about
digitally converted data of the brightness and color signals supplied from
the memory section. Thus, it is possible to partially set some values of
the discrete cosine transformation coefficient used in the discrete cosine
transformation to zero. Accordingly, the discrete cosine transformation
processing section can reduce the number of operations required to perform
the discrete cosine transformation, thereby reducing a time required to
perform the discrete cosine transformation.
Since the time required to process the discrete cosine transformation is
reduced, it is not necessary for the memory section to store all
information of one photographed image. Accordingly, with respect to the
photographed image composed of 60 blocks, it is sufficient for the memory
section to store image data constructed by a total of 180 blocks composed
of 90 blocks extending in a horizontal direction of the photographed image
with respect to two blocks in a vertical direction thereof. Namely, it is
sufficient to dispose two memory sections for storing one line block of
image data, thereby reducing the size of a circuit structure of the memory
section. Thus, the size of a circuit structure of the entire orthogonal
transformation arithmetic unit is reduced by the memory section and the
discrete cosine transformation processing section.
In accordance with a second structure of the present invention, the above
objects can be achieved by an orthogonal transformation arithmetic unit
for dividing one image into blocks including a plurality of picture
elements, the orthogonal transformation arithmetic unit comprising an
orthogonal transformation circuit for performing orthogonal transformation
processing with respect to each of the blocks; and an inverse orthogonal
transformation circuit for returning orthogonally transformed data to
original image data; the inverse orthogonal transformation circuit having
a processing block having a variable size and selecting an inverse
orthogonal transformation coefficient corresponding to a designated size
of the processing block, the inverse orthogonal transformation circuit
performing inverse orthogonal transformation processing with respect to
the designated size of the processing block.
In the second structure of the present invention, the reducing and
enlarging processings of an image are simultaneously executed in the
inverse orthogonal transformation circuit for reproducing orthogonally
transformed data as an original image instead of a separate unit for
performing the reducing and enlarging processings. Accordingly, no unit
for reduction and enlargement is required and a processing time for
reduction and enlargement can be reduced.
In accordance with a third structure of the present invention, the above
objects can be achieved by an orthogonal transformation arithmetic unit
for performing a discrete cosine transformation with respect to a digital
signal and compressing discrete cosine transformed data by quantizing and
Huffman-coding processings thereof, the orthogonal transformation
arithmetic unit Huffman-decoding the compressed data and demodulating the
Huffman-decoded data to a digital signal by performing inverse
quantization and an inverse discrete cosine transformation with respect to
the Huffman-decoded data, the orthogonal transformation arithmetic unit
having a discrete cosine transformation/inverse discrete cosine
transformation processing section for processing the discrete cosine
transformation and the inverse discrete cosine transformation; the
discrete cosine transformation/inverse discrete cosine transformation
processing section comprising a coefficient memory section for storing
coefficients required to perform the discrete cosine transformation and
the inverse discrete cosine transformation and transmitting one of the
coefficients selected in accordance with a control signal indicative of
the discrete cosine transformation or the inverse discrete cosine
transformation; a set of main arithmetic circuits for processing both the
discrete cosine transformation and the inverse discrete cosine
transformation by the transmitted coefficient and commonly used in both
the processings of the discrete cosine transformation and the inverse
discrete cosine transformation; and a section for selecting discrete
cosine transformed data or inverse discrete cosine transformed data in
accordance with the control signal.
In such a third structure, the DCT/inverse DCT-processing section can
commonly execute both the DCT-processing and the inverse DCT-processing by
one set of main processing circuits. The selecting section selects one of
the DCT-transformed data and the inverse DCT-transformed data in
accordance with the control signal transmitted thereto. Thus, a
DCT-processing circuit and an inverse DCT-processing circuit separately
disposed in the general orthogonal transformation arithmetic unit are
unified as the DCT/inverse DCT-processing section, thereby reducing the
size of a circuit structure of the entire orthogonal transformation
arithmetic unit.
In accordance with a fourth structure of the present invention, the above
objects can be achieved by an orthogonal transformation arithmetic unit of
an adaptive discrete cosine transformation coding system for performing an
orthogonal transformation with respect to information of a color still
image using a discrete cosine transformation, the orthogonal
transformation arithmetic unit comprising: a change-over switch for
setting the number of sheets of a photographed image storable to a memory
section having a constant memory capacity; a compressibility detecting
section for automatically setting a quantizing coefficient used to
compress an information amount of the photographed image until a
predetermined image information amount in accordance with a signal
indicative of the number of sheets of the photographed image transmitted
from the change-over switch, the compressibility detecting section
calculating a compressibility of the information amount and predicting a
quality level of the stored photographed image based on the
compressibility; and a display section for visually displaying a signal
indicative of the image quality level transmitted from the compressibility
detecting section.
In such a fourth structure, the compressibility detecting section
arbitrarily sets a quantizing coefficient .alpha. such that information of
the number of sheets of the photographed image manually set by the
change-over switch is stored to the memory section. The quantizing
coefficient .alpha. can be changed by the number of sheets of the
photographed image set by an operator. When the quantizing coefficient
.alpha. is changed, a zero boundary region is moved as mentioned above so
that a quality of the stored photographed image can be changed. The
compressibility detecting section calculates a compressibility based on
the quantizing coefficient .alpha. and predicts an image quality level
based on this compressibility. The display section visually displays this
predicted image quality level. Accordingly, the operator can confirm the
quality of the photographed image with respect to the set number of sheets
thereof.
As mentioned above, the change-over switch, the compressibility detecting
section and the display section indirectly change the quantizing
coefficient .alpha. by setting the number of sheets of the stored image so
as to set the quality of the stored photographed image.
Further objects and advantages of the present invention will be apparent
from the following description of the preferred embodiments of the present
invention as illustrated in the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing the construction of a general DCT/inverse
DCT processor;
FIG. 2 is a block diagram showing the construction of an orthogonal
transformation arithmetic unit in general DCT-processing;
FIG. 3 is a block diagram showing a circuit structure with respect to data
compression in an ADCT-processing section shown in FIG. 2;
FIG. 4 is a view showing one data block before the DCT-processing;
FIG. 5 is a view showing one data block after the DCT-processing;
FIG. 6 is a view showing blocks of one image;
FIG. 7 is a view showing a concrete example of image data after the
DCT-processing;
FIG. 8 is a view showing values of a quantizing coefficient .alpha. used in
quantization;
FIG. 9 is a view showing a concrete example of quantized image component
data;
FIG. 10 is a view showing a zigzag scanning direction in Huffman-coding
processing;
FIG. 11 is a block diagram showing the construction of an orthogonal
transformation arithmetic unit in DCT-processing in accordance with a
first embodiment of the present invention;
FIG. 12 is a block diagram showing one example of a circuit structure with
respect to data compression in an ADCT-processing section shown in FIG.
11;
FIG. 13 is a block diagram showing one example of a circuit structure with
respect to data extension in the ADCT-processing section shown in FIG. 11;
FIG. 14 is a block diagram showing an example of the construction of an
adder/subtractor shown in FIG. 12;
FIGS. 15a and 15b are block diagrams showing a data-compressing/extending
system in an orthogonal transformation arithmetic unit in accordance with
a second embodiment of the present invention;
FIGS. 16a and 16b are views respectively showing reduced and enlarged
images in the orthogonal transformation arithmetic unit in the second
embodiment;
FIG. 17 is a block diagram showing IDCT-processing in the second embodiment
of the present invention;
FIG. 18 is a block diagram showing one example of a one-dimensional
IDCT-processing circuit;
FIG. 19 is a block diagram showing the construction of an orthogonal
transformation arithmetic unit in accordance with a third embodiment of
the present invention;
FIG. 20 is a block diagram showing one example of the construction of a
DCT/inverse DCT-processing section shown in the orthogonal transformation
arithmetic unit shown in FIG. 19;
FIG. 21 is a block diagram showing the construction of a DCT-processing
section shown in FIG. 20;
FIG. 22 is a block diagram showing the construction of an inverse
DCT-processing section shown in FIG. 20;
FIG. 23 is a graph showing the relation between an area ratio of a circuit
chip and a price thereof;
FIG. 24 is a block diagram showing the construction of an orthogonal
transformation arithmetic unit in accordance with a fourth embodiment of
the present invention; and
FIG. 25 is a graph showing a function for determining superiority and
inferiority of the quality of a compressed image in the orthogonal
transformation arithmetic unit shown in FIG. 24.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
The preferred embodiments of an orthogonal transformation arithmetic unit
in the present invention will next be described in detail with reference
to the accompanying drawings.
As shown in FIG. 1, when a color photographed image is recorded as a still
image, information of the photographed image is converted to an electric
signal by e.g., a charge coupled device 1. The charge coupled device is
called a CCD in the following description. Thereafter, this electric
signal is converted to a digital signal by an A/D converter 2. Image data
of this digital signal are transmitted to a DCT-processing section 3
described later in detail. In this DCT-processing section 3, one image is
divided into a plurality of image blocks and discrete cosine
transformation (DCT) processing is performed every image block.
DCT-processed image data A.sub.ij are quantized by a quantization
processing section 4 in accordance with the following formula based on a
quantizing coefficient .alpha. and a quantizing transformation coefficient
Q.sub.ij prescribed by the Joint Photographic Export Group.
Quantization processing formula:Bij=Aij/.alpha./Qij
In this formula, reference numeral B.sub.ij designates image component data
after quantization.
The quantized image component data B.sub.ij are Huffman-coded by a
Huffman-coding processing section 5, thereby compressing the image
component data. The compressed image data are stored to a memory section
6. Thus, the photographed image information is compressed and stored to
the memory section 6.
The compressed image data stored to the memory section 6 are reproduced as
an original photographed image as follows. Namely, the compressed image
data read out of the memory section 6 are decoded by a Huffman-decoding
processing section 7 and are converted to image component data B.sub.ij.
These image component data are inversely quantized by an inverse
quantization processing section 8 and are converted to image data. These
converted image data are inversely DCT-processed by an inverse
DCT-processing section 9 described later in detail and are approximately
reproduced as information of the original photographed image.
The DCT-processing section 3, the quantization processing section 4, the
Huffman-coding processing section 5, the Huffman-decoding processing
section 7, the inverse quantization processing section 8 and the inverse
DCT-processing section 9 constitute an ADCT-processing section.
For example, with respect to a series of data compression and extension,
the quantization processing section 4, the Huffman-coding processing
section 5, the Huffman-decoding processing section 7 and the inverse
quantization processing section 8 are constructed as shown by "Journal of
Image Electronic Society of Japan" Vol. 18, No. 6, pp. 398 to 407 in 1989.
As shown in FIG. 2, when the color photographed image is concretely
recorded as a still image, the color photographed image is converted to an
electric signal by the charge coupled device 1 and is converted to a
brightness signal (Y) and color difference signals (R-Y, B-Y) by a signal
processing circuit 11 through an amplifier 10. These signals (Y), (R-Y),
(B-Y) are respectively converted to digital signals by the A/D converter
2. Thereafter, respective data of these converted signals are temporarily
stored to a Y-component page buffer 12, an (R-Y)-component page buffer 13
and a (B-Y)-component page buffer 14 corresponding to these converted
signals. For example, when one photographed image is constructed by only a
sheet of paper having size A4, the respective component data of the
signals (Y), (R-Y) and (B-Y) stored to these page buffers 12 to 14 are
constructed by information of all images drawn on this sheet. For example,
as shown in FIG. 6, one photographed image is constructed by a total of
5400 image blocks divided into 60 image blocks in a longitudinal direction
and 90 image blocks in a transversal direction. One image block is
constructed by a total of 64 picture elements composed of 8 picture
elements in each of the longitudinal and transversal directions. Data of
each of the picture elements every one image block mentioned above are
supplied to an ADCT-processing section 15. In the ADCT-processing section
15, the component data respectively transmitted from the Y-component page
buffer 12, the (R-Y)-component page buffer 13 and the (B-Y)-component page
buffer 14 are compressed to store these component data to the memory 6.
Conversely, the compressed data stored to the memory 6 are decoded to the
original component data in the ADCT-processing section 15.
The ADCT-processing section 15 is constructed as shown in FIG. 3. A
multiplier 80 (constructed by 64 multipliers) sequentially receives data
of the picture elements constituting one image block and a DCT-processing
coefficient every one image block respectively from the Y-component page
buffer 12, the (R-Y)-component page buffer 13 and the (B-Y)-component page
buffer 14. The multiplier 80 then performs a multiplying operation with
respect to the above picture element data and the DCT-processing
coefficient. The multiplier 80 outputs multiplied data to an adder 81
(constructed by 56 adders). The adder 81 performs an adding operation with
respect to the supplied data and the data of added results are transmitted
to a transposition RAM 82 which can store the added data into 8.times.8
memory blocks. Two-dimensional DCT-processing of the photographed image of
two-dimensional information is performed by one-dimensional
DCT-processings with respect to longitudinal and transversal data of the
image. Thus, the one-dimensional DCT-processing is first performed by the
multiplier 80 and the adder 81.
A formula for the two-dimensional DCT-processing is represented by the
following formula (1).
##EQU1##
In the formula (1), reference numeral f(i, j) designates data of a picture
element.
The data of the added results read out of the transposition RAM 82 are
transmitted to a multiplier 83 (constructed by 64 multipliers) to further
perform the one-dimensional DCT-processing. A multiplying operation of the
multiplier 83 is similar to that of the multiplier 80. The multiplier 83
performs a multiplying operation with respect to the date of the added
results read out of the transposition RAM 82. The data of multiplied
results are transmitted to an adder 84 (constructed by 56 adders) for
performing an adding operation, thereby executing the two-dimensional
DCT-processing. The two-dimensional ADCT-processing is then completed
through a quantizing circuit 85 and a coding circuit 86.
The above-mentioned operations will be further explained in detail in the
following description.
For example, it is assumed that the data of one block of a photographed
image stored to the Y-component page buffer 12 are provided as shown in
FIG. 4. Component data X.sub.00 to X.sub.70 are stored in a first column
of this image block and are sequentially supplied to the multiplier 80.
DCT-processing coefficients of the following (8.times.8) matrix are
supplied to the multiplier 80.
##STR1##
In this matrix, the DCT-processing coefficients designated by " - - - " are
omitted for brevity.
Accordingly, the multiplier 80 performs the multiplying operation with
respect to the above data X.sub.00 to X.sub.70 and the DCT-processing
coefficients A.sub.00 to A.sub.70. The data of multiplied results are set
to Z.sub.00 to Z.sub.70. For example, the data value Z.sub.00 is
represented by the following formula.
Z.sub.00 =A.sub.00 .multidot.X.sub.00 +A.sub.01 .multidot.X.sub.10
+A.sub.02 .multidot.X.sub.20 +A.sub.03 .multidot.X.sub.30 +A.sub.04
.multidot.X.sub.40 +A.sub.05 .multidot.X.sub.50 +A.sub.06
.multidot.X.sub.60 +A.sub.07 .multidot.X.sub.70 (2)
As can be seen from the above formula (2), adding values with respect to
the above calculated data values are added to each other by the adder 81
subsequent to the multiplier 80, thereby finally calculating the data
value Z.sub.00. Similarly, the data values Z.sub.10 to Z.sub.70 are
calculated. The following matrix (3) is obtained from the above-mentioned
calculated data values.
##STR2##
The calculated data Z.sub.00 to Z.sub.70 are transmitted to the
transposition RAM 82. Similarly, data X.sub.01 to X.sub.71 in a second
column of the image block shown in FIG. 4 are DCT-processed and obtained
as data Z.sub.01 to Z.sub.71. Similarly, data Z.sub.02 to Z.sub.77 are
sequentially calculated and transmitted to the transposition RAM 82,
thereby completing the one-dimensional DCT-processing.
As shown in FIG. 5, the respective data Z.sub.00 to Z.sub.77 are stored to
the transposition RAM 82 in an order from the first column to the eighth
column. When all one-dimensional DCT-processed data are thus stored to the
transposition RAM 82, the transposition RAM 82 reads data Z.sub.70 to
Z.sub.77 stored in a lowermost row I in FIG. 5 and transmits these read
data to the multiplier 83.
Multiplying and adding operations of the multiplier 83 and the adder 84 are
respectively similar to those of the multiplier 80 and the adder 81
mentioned above. Second one-dimensional DCT-processing is performed by the
multiplier 83 and the adder 84. Data Z.sub.60 to Z.sub.67 stored in the
next row II are transmitted from the transposition RAM 82 to the
multiplier 83. Similarly, data Z.sub.00 to Z.sub.07 stored in row VIII are
transmitted to the multiplier 83. Accordingly, a reading order of data Z
stored in the transposition RAM 82 is different from a writing order of
these data written to the transposition RAM 82. Therefore, it is
impossible to read data out of the transposition RAM 82 until the data of
one image block are completely written to the transposition RAM 82.
A predetermined quantizing operation with respect to the data Z transmitted
from the adder 84 is performed by the quantizing circuit 85, thereby
compressing these data. A predetermined coding operation with respect to
the quantized data is then performed by the coding circuit 86, thereby
providing coded data stored to the memory 6. The coded data are
transmitted from the coding circuit 86 to the memory 6 and are stored in
this memory 6.
The above operation of the orthogonal transformation arithmetic until
relates to the Y-component data, but the orthogonal transformation
arithmetic unit is similarly operated in the cases of the (R-Y)-component
data and the (B-Y)-component data. The above-mentioned ADCT-processing
operation is performed with respect to data compression for storing the
data of a photographed image to the memory. Conversely, when data of the
original photographed image are reproduced from the compressed data stored
into the memory, the data read out of the memory are decoded by a decoding
circuit and are inversely quantized by an inverse quantizing circuit. The
inversely quantized data are reproduced as the photographed image data
through a multiplier, an adder, a transposition RAM, a multiplier and an
adder.
A formula for an inverse DCT-processing (IDCT-processing) inverse to the
DCT-processing is represented by the following formula (4).
##EQU2##
As mentioned above, in the DCT-processing and the IDCT-processing, it is
necessary to perform 64 multiplying operations with respect to all input
data and the DCT-processing coefficients composed of the (8.times.8)
matrix, and perform 56 adding operations with respect to the multiplied
results. Accordingly, a processing time required to perform the
ADCT-processing including a memory operation with respect to the memory 6
as shown by line b in FIG. 2 is longer than a processing time from the
charge coupled device 1 to the Y-component page buffer 12, the
(R-Y)-component page buffer 13 or the (B-Y)-component page buffer 14 as
shown by line a in FIG. 2. Therefore, it is necessary to dispose a memory
for temporarily storing color and brightness information of one
photographed image picture, circuit elements corresponding to the
respective page buffers 12 to 14 shown in FIG. 2, and a frame memory. For
example, in a still video camera, it is necessary to dispose a memory
having a capacity of 7.5M bits with respect to one picture. Accordingly,
there is a problem that the size of a circuit structure of the entire
orthogonal transformation arithmetic unit is increased.
When an image is generally coded and coded data are reproduced as the
original image, there is a case in which the size of an image obtained by
the coded data is reduced or enlarged in comparison with the original
image. In such reducing and enlarging processings, inverse orthogonal
transformation processing is performed with respect to orthogonally
transformed data and these data are reproduced as the original image.
Thereafter, the reducing and enlarging processings are performed with
respect to the reproduced data. When the image is reproduced and the
reducing and enlarging processings are further performed with respect to
the reproduced image, it is necessary to separately dispose a processing
unit for performing the reducing and enlarging processings. Further, there
is a problem that a processing time is further increased by separately
disposing such a processing unit for performing the reducing and enlarging
processings.
As mentioned above, the general orthogonal transformation arithmetic unit
for performing the DCT-processing and the inverse DCT-processing has the
DCT-processing section 3 and the inverse DCT-processing section 9. Two
main arithmetic circuits similarly operated, etc. are disposed in the
DCT-processing section 3 and the inverse DCT-processing section 9. An area
for these main arithmetic circuits amounts to about 90 percent of an area
for a semiconductor circuit chip constituting a DCT/inverse DCT processor.
Therefore, the size of a circuit structure is increased by these two main
arithmetic circuits.
Accordingly, the circuit structure is large-sized in the general orthogonal
transformation arithmetic unit for performing the DCT/inverse
DCT-processings.
Further, the general orthogonal transformation arithmetic unit has the
following problems.
For example, the above two-dimensional DCT-processing is performed with
respect to data of each of picture elements in an image block shown by
reference numeral a in FIG. 6. A group of these DCT-processed data are
shown in FIG. 7. The DCT-processed image data are also constructed by 8
picture elements in each of longitudinal and transversal directions in
FIG. 7 so that the data group of one image block is constructed by a total
of 64 picture elements. Frequency components of the DCT-processed image
data are increased as the image data in the longitudinal direction are
located downward in FIG. 7. The | | |
