 |
Claims  |
|
|
What is claimed is:
1. A semiconductor memory device integrated on a semiconductor chip (500),
comprising;
a DRAM cell array (300) including a plurality of dynamic type memory cells
arranged in a matrix of rows and columns, said DRAM cell array including a
plurality of blocks (300') each having a group of columns,
an SRAM cell array (310) including a plurality of static type memory cells
(SMC) arranged in a matrix of rows and columns, said SRAM cell array
including a plurality of blocks (18) corresponding to said blocks of said
DRAM cell array,
transfer means (330; 17) for transferring data in a block between said DRAM
cell array and said SRAM cell array,
store/detect means (320; 340) for storing addresses of data stored in said
blocks of said SRAM cell array, and detecting match/mismatch between an
externally supplied first address signal and an address stored therein
(320; 340),
first means (20, 22, 23, 27, 29, 370, 380, 390) responsive to a match
detection signal from said store/detect means and an externally supplied
second address signal for selecting a corresponding memory cell from said
SRAM cell array and connecting said corresponding memory cell to an
internal data transmission line (I/O, I/O), and
second means (350, 360, 380, 20) responsive to a mismatch detection signal
from said store/detect means and said first and second addresses for
selecting a corresponding memory cell from said DRAM cell array and
connecting that memory cell to said internal data transmission line
through a column of said SRAM array.
2. A memory device according to claim 1, wherein said first means includes;
means (380) responsive to said second address signal for generating an SRAM
word line drive signal (SWL1-SWL4) for selecting a row in said SRAM cell
array, and
means (29) responsive to said match detection signal from said store/detect
means for directly transmitting said SRAM word line drive signal to an
SRAM word line connecting memory cells of one row of the SRAM cell array
for which a match is detected.
3. A memory device according to claim 1, wherein said first means includes;
means (340) responsive to said first address signal for generating an
internal row designating signal for designating a row in said DRAM cell
array, and applying at least a part of said internal row designating
signal to said store/detect means as an address for retrieval,
means (370) responsive to said second address signal for generating
internal column designating signal for designating a column in said DRAM
cell array, said first address signal and said second address signal being
externally applied at substantially the same timing,
column/block selecting means (380, 390) responsive to said internal column
designating signal for generating signals for selecting a column and a
block in said DRAM cell array, respectively, and
means (410) for causing said store/detect means and said column/block
selecting means to operate parallel to each other.
4. A memory device according to claim 1 wherein said store/detect means
includes;
a plurality of match detection lines (23-1 to 23-4) extending in one
direction,
a plurality of data input lines (X0-X11, X0-X11) extending in a direction
crossing said match detection lines for receiving respective bits
corresponding to said first address signal,
a plurality of content addressable memories (CAM11-CAM124) arranged at
respective crossings between said match detection lines and said data
input lines, content addressable memories on one row connected to a single
match detection line storing an address for data stored in said SRAM cell
array, and
a plurality of CAM word lines (CWL1-CWL4) extending in said one direction,
said content addressable memories on each respective row being connected
to a corresponding CAM word line,
said content addressable memories being arranged in rows and columns to
correspond to said rows and columns in said SRAM cell array, and
said match/mismatch detection signal being transmitted to said match
detection lines for application to said first means.
5. A memory device according to claim 1, wherein said store/detect means is
provided for each block in said SRAM cell array for detecting
match/mismatch of address in relation to each block in said SRAM cell
array.
6. A memory device according to claim 1, wherein said store/detect means
includes means (22) responsive to a potential of said second address
signal and a potential on a signal line connecting a row in said SRAM cell
array for transmitting said mismatch detection signal to said second
means.
7. A memory device according to claim 1, wherein said DRAM cell array
includes n columns (31, 32, 33, 34) for each column (40) in said SRAM cell
array, said SRAM cell array including SRAM cells arranged in n rows, n
being an integer.
8. A memory device according to claim 7, wherein said second means includes
means (380, 390, 330, 17) responsive to said mismatch detection signal for
connecting one of said n rows in said DRAM cell array block to a
corresponding column in said SRAM cell array block.
9. A memory device according to claim 1, wherein said second means
includes;
means (395) responsive to said externally applied second address signal for
generating a first column detecting signal for selecting a column in said
SRAM cell array, and
means (410, 350, 360, 29, 17) responsive to said mismatch detection signal
from said store/detect means for temporarily disregarding said external
applied first address signal, and responsive to said first column
selecting signal for reading from said store/detect means an address
corresponding to said SRAM cell array column designated by said first
column selecting signal, selecting a corresponding memory cell in said
DRAM cell array in response to thus read out address, reading memory cell
data in a designated column in said SRAM cell array in response to said
first column selecting signal, and writing the data read from the SRAM
cell to said selected corresponding, dynamic memory cell through said
transfer means.
10. A semiconductor memory device comprising;
a DRAM cell array (300) including a plurality of dynamic type memory cells
(DMC) arranged in a matrix of rows and columns, said DRAM cell array being
divided into a plurality of blocks (300,) each having a group of columns,
said DRAM cell array including a plurality of DRAM word lines (WL) each
having dynamic type memory cells on one row connected, and a plurality of
DRAM bit lines (BL, BL) each having dynamic type memory cells on one
column connected,
an SRAM cell array (310) including a plurality of static type memory cells
(SMC) arranged in a matrix of rows and columns, said SRAM cell array being
divided into a plurality of blocks (18) corresponding to said blocks of
said DRAM cell array, each of said blocks of said SRAM cell array
including a plurality of SRAM word lines (SWL) each having static type
memory cells of one row in said blocks connected, and a plurality of SRAM
bit lines (40) each having static type memory cells of one column
connected,
a CAM cell array (320) including a plurality of content addressable
memories (CMC) arranged in a matrix of rows and columns, said CAM cell
array having a plurality of blocks corresponding to said blocks of said
SRAM cell array, each of said CAM cell array blocks having a plurality of
CAM word lines (CWL) each having content addressable memory cells of one
row in the blocks connected, a plurality of data input lines (X0-X11, X11)
each having addressable memory cells of one column are connected, and a
plurality of local match lines each having content addressable memory
cells of one row in the blocks connected,
a plurality of drive means (29) each disposed between each respective said
SRAM cell array block and each respective said CAM cell array block, and
each for directly driving an SRAM word line in the associated block to
place the SRAM word line in a selected state in response to a signal
potential on the local match line in the associated block,
a plurality of cache hit/miss signal generating means (22) associated with
respective said SRAM cell array blocks, for generating a signal indicating
a cache hit/miss in response to a signal potential on the SRAM word line
in each respective associated block,
means (340) responsive to an externally applied first address signal for
generating a first internal address signal for designating a row in said
DRAM cell array, and applying at least a part of said first internal
address signal to said CAM cell array blocks as a retrieval data,
means (390) responsive to an externally applied second address signal for
generating a block selecting signal,
means (22) responsive to said block selecting signal for activating a
corresponding CAM cell array block,
means (380) responsive to said second address signal for generating a
signal for selecting a column in said DRAM cell array and in said SRAM
cell array,
means (Tr1, Tr2, 19, 420) responsive to the cache hit indicating signal and
said column selecting signal for connecting the selected column in said
SRAM cell array to circuitry external to said semiconductor memory device,
and
means (350, 360, 380, 395, 420) responsive to the cache miss indicating
signal, said column selecting signal and said first address signal for
connecting a memory cell in the selected row and column in said DRAM cell
array to circuitry external to said semiconductor memory device through
associated column in said SRAM cell array.
11. A method of operating a semiconductor memory device comprising a DRAM
cell array (300) including a plurality of dynamic type memory cells (DMC)
arranged in a matrix of rows and columns, an SRAM cell array (310)
including a plurality of static type memory cells (SMC) arranged in a
matrix of rows and columns, and a CAM cell array (320) including a
plurality of content addressable memories (CMC) arranged in a matrix of
rows and columns, all formed on a single semiconductor chip (500), said
method comprising the steps of;
generating a first internal address signal in response to an externally
applied first address signal, and applying at least a part of said first
internal address signal to said CAM cell array as a retrieval data,
directly driving a corresponding row in said SRAM cell array to place the
row in a selected state in response to a signal potential on a row in said
CAM cell array for which a match is found,
generating a second internal address signal for selecting a column in said
DRAM cell array and in said SRAM cell array in response to an externally
applied second address signal,
generating a signal indicating a cache hit/miss in response to signal
potentials on the rows in said SRAM cell array, and
connecting a corresponding column in said SRAM cell array to circuitry
external to said semiconductor memory device in response to a generated
cache hit indicating signal and said second internal address signal.
12. A method according to claim 11, wherein the step of generating said
second internal address signal is carried out in parallel with the
retrieval operation in said CAM cell array.
13. A method according to claim 11, further including the steps of
selecting a row and a column in said DRAM cell array,
selecting a column in said SRAM cell array, and
connecting a memory cell at a crossing between the selected row and column
in said DRAM cell array to circuitry external to said semiconductor memory
device through the selected column in said SRAM cell array in response to
said first and second internal address signals and said cache hit/miss
indicating signal.
14. A method according to claim 11 further comprising the steps of;
generating a third internal address signal for selecting a row in said SRAM
cell array in response to said second address signal,
generating a signal for selecting a row in said CAM cell array in response
to said cache hit/miss indicating signal and said second address signal,
reading contents of the selected row in said CAM cell array in response to
said cache hit/miss indicating signal and said CAM cell array row
selecting signal,
selecting a row in said DRAM cell array in response to the read out content
of said CAM cell array, and
writing the content of the selected row in said CAM cell array to memory
cells in said selected row in said DRAM cell array in response to said
third internal address signal.
15. A method according to claim 11, wherein said DRAM cell array, said SRAM
cell array and said CAM cell array each include a plurality of blocks,
said blocks in one array being in a one-to-one relationship with said
blocks in the other arrays, and wherein said method includes the steps of
generating a signal for selecting a block in response to said second
address signal, and executing all said mentioned steps for the block
selected by said block selecting signal. |
|
 |
|
 |
Claims |
|
|
|
Description |
|
|
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device,
particularly to a semiconductor memory device having a dynamic random
access memory (DRAM) and a static random access memory (SRAM) formed on
the same semiconductor chip, and to a method of driving the semiconductor
memory device. More particularly, the invention relates to a semiconductor
memory device containing cache with a main memory and a cache memory
formed on the same semiconductor chip, and to a method of driving the
semiconductor memory device.
2. Description of the Background Art
With progress of semiconductor technology, a central processing unit (CPU)
has become operable at high speed and so has a DRAM. However, a DRAM
cannot follow the development in the speed of CPU and the difference in
operating speed therebetween has increased. This is bottle-neck in
improvement of data processing speed of computer systems.
In a large-scale system such as a mainframe, a high-speed cache memory is
interposed between a main memory and a CPU to compensate for the operating
speed of the main memory, thereby to improve performance without a
significant increase in cost.
For a small-scale system, a construction has been proposed and put to
practical use, in which a cache memory is formed on the same semiconductor
chip as that on which a DRAM is formed, to realize equivalently a
high-speed operation of the main memory. In such DRAM containing cache,
data transfer between an SRAM acting as cache memory and a DRAM acting as
main memory is effected at high speed by using an internal data bus having
a large bit width.
FIG. 1 shows a conceptional construction of a system employing a
conventional DRAM containing cache.
Referring to FIG. 1, the processing system comprises a microprocessor 100
for carrying out various processes according to predetermined programs, a
cache controller 110 for controlling operation of the cache memory, a tag
120 operable in response to an address from outside of the cache for
determining a cache hit/miss and designating a corresponding "way", a DRAM
controller 130 for controlling operation of a DRAM section, and a DRAM 200
containing cache memory (cache DRAM).
The cache DRAM 200 includes a DRAM section 210 having, for example, a 1M
bit storage capacity, and an SRAM section 220 having, for example, an 8K
bit storage capacity. The DRAM section 210 includes 4 plates of 256K bit
DRAM, each DRAM plate being divided into 64 groups each having an 8-bit
width. The SRAM section 220 includes 2 plates of 2K bit SRAM, each SRAM
plate being divided into 64 blocks each having a 32-bit (8.times.4) size.
Each block of the SRAM is further divided into four 8-bit ways. This
construction provides a four-way set associative system. The input/output
data width is 4 bits (DQ1-DQ4).
Data transfer between DRAM section 210 and SRAM section 220 is performed in
a block through an internal data bus 230 having a 32-bit width.
The microprocessor 100 transfers 4-bit data DQ1-DQ4, outputs 18-bit
addresses A0-A17, and transmits necessary control signals to the DRAM
controller 130 and cache controller 110.
Though not expressly shown, the tag 120 includes a tag memory for storing
addresses (tag address A0-A8 and set address A9-A14) for data stored in
the SRAM section 220, a comparator for comparing the tag addresses stored
in the tag memory and an address received from the microprocessor 100, and
a tag replacement logic processor for generating a way address designating
a region of the SRAM section 220 for which data rewriting is to be carried
out in accordance with a result of comparison in the comparator.
The cache controller 110 is operable in response to a cache hit/miss
indicating signal from the tag 120 for generating a signal BT instructing
data transfer between SRAM section 220 and DRAM section 210.
The DRAM controller 130 generates a row address strobe signal RAS and a
column address strobe signal CAS for operating the DRAM section 210 on a
cache miss. A data reading operation of this cache DRAM will be described
briefly in the following.
The SRAM section 220 has a four-way, 64-set construction. One set
corresponds to one block in the DRAM section 210. Access is made to this
cache DRAM according to the 18-bit address signals A0-A17. Fifteen bits in
the 18-bit address A0-A17 are applied also to the tag 120. The tag address
and set address (address A0-A14) applied to the tag 120 are compared with
the addresses stored therein, and cache hit/miss is determined on the
result of the comparison.
In parallel with the cache hit/miss determination at the tag 120, access is
made to the SRAM section 220 in the cache DRAM 200. The address signals
A9-A14 designate one of the 64 sets in the SRAM section 220, and the
address signals A15-A17 designate which of the eight columns (One set has
8 bits.) in the designated set is addressed. The 16 bits present on the
designated column (4 bits per way) are transmitted to a stage just front
of an output.
When an address of data stored in the SRAM section (cache memory) 220
coincides with an address stored in the tag 120, the tag 120 further
decodes this address and outputs a 2-bit way address WA0, WA1. As a
result, one way is selected from the four ways read simultaneously, and
4-bit data DQ1-DQ4 is read out in parallel.
Data is read from the DRAM section 210 at a cache miss when the external
address does not coincide with every address stored in the tag 120. The
data reading is carried out in a way similar to access to an ordinary
DRAM. That is, data is read by using the address signals A0-A8 as a row
address signal and the address signals A9-A17 as a column address signal,
and in response to the control signals RAS and CAS from the DRAM
controller 130.
At a cache miss, the block (32 bits: corresponding to one way) in the DRAM
section 210 including the 4 bits to which access has been made is
transferred to the SRAM section 220 through the internal data bus 230.
Timing of this transfer is controlled by the control signal BT from the
cache controller 110. The replacement logic processor included in the tag
120 determines to which of the ways in the SRAM section 220 the
transferred block data should be written. That is, the tag 120 generates
the way address WA0, WA1 for selecting a way in the SRAM section 220.
In rewriting of data in the SRAM section (cache memory) 220, data of
corresponding memory cells in the DRAM section 210 are also rewritten
simultaneously (i.e. a write-through mode). Data writing to the DRAM
section 210 is carried out in the same way as access to an ordinary DRAM.
In this case, however, whether the written data is transferred also to the
SRAM section 220 or not is optionally determined, and the choice is made
through the transfer control signal BT.
FIG. 2 shows a specific construction of the cache DRAM. This cache RAM
construction shows circuitry relating to data reading, which is shown in
1989 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, pages 43-44,
for example.
Referring to FIG. 2, the DRAM section 210 includes a DRAM cell array 211
having a capacity of 1M (2.sup.20) bits, a row decoder 212 for selecting
one row in the DRAM cell array 211 in response to an externally applied
row address A0-A8, a column decoder 213 for selecting 32 columns in the
DRAM cell array 211 in response to 6-bit column address A9-A14 in an
externally applied column address A9-A17, a DRAM sense amplifier 214 for
detecting and amplifying data of memory cells in one row selected by the
row decoder 212, an I/O gate 215 for connecting the selected columns to
the internal data bus 230 in response to output of the column decoder 213,
and a 1/8 decoder 231 for selecting four data lines from the 32-bit data
lines in the internal data bus 230 in response to 3-bit column address
A15-A17 in the externally applied column address.
The SRAM section 220 includes a SRAM cell array 221 having an 8K bit
storage capacity, a set decoder 222 for receiving 6-bit set address A9-A14
among en externally applied cache address (the column address) A9-A17, and
selecting one set or one row from the 64 sets in the SRAM cell array 221,
a SRAM column decoder 213 for selecting 16 columns from the selected set
in response to 3-bit address A15-A17 among the cache address A9-A17, an
SRAM sense amplifier 294 for detecting and amplifying the data in the
columns selected by the SRAM column decoder 213, a first way decoder 216
for selecting 4-bit data of one way from the 16-bit data of the four ways
in response to an externally applied way address WA0, WA1, and a second
way decoder 294 for selecting a way in the SRAM cell array 221 to be
written with the 32-bit data transferred from the DRAM section 210 in
response to the way address WA0, WA1 at a cache miss, and writing the
32-bit data to a selected way.
A hit/miss buffer 232 is provided for selecting either the DRAM section 210
or the SRAM section 220 in response to a cache hit/miss indicating signal
H/M. This hit/miss buffer 232 not only buffers the cache hit/miss
indicating signal H/M to generate a control signal for controlling
operation of the first way decoder 216, but also maintains the output DQ0
to DQ4 at a high impedance until DRAM data is read and transmitted at a
cache miss. Further, the hit/miss buffer 232 selects either the 1/8
decoder or the first way decoder in response to the cache hit/miss
indicating signal H/M. Operations will be described next.
(i) At hit read
When a cache address A9-A17 is applied to the SRAM section 220, the SRAM
section 220 is activated regardless of a cache hit/miss. The set decoder
222 decodes the 6-bit set address A9-A14 in the cache address A9-A17, and
selects one set in the SRAM section 220. Since the selected set includes
four ways and each way has 8 bits, 32-bit memory cells in total are
selected simultaneously. Subsequently, the column decoder 223 decodes the
3-bit column address A15-A17, and selects one of the eight rows in one
set. As a result, 16-bit memory cells in total are selected, with 4 bits
selected from each way. The data of the 16-bit memory cells are amplified
by the sense amplifier 295 and are then transmitted to the first way
decoder 216.
At a time of cache hit, the way address WA0, WA1 is applied to the first
way decoder 216. Based on the way address WA0, WA1, the first way decoder
216 selects one of the four ways and applies 4-bit data of the selected
way to the hit/miss buffer 232. The hit/miss buffer 232, in response to a
hit signal H, selects the 4-bit data from the first way decoder 216, and
outputs the data as output data DQ1-DQ4.
(ii) At a hit write
When the column address A0-A8 and cache/column address A9-A17 are applied
to the cache DRAM, the DRAM section 210 and SRAM section 220 are
activated. In response to a hit indicating signal H and a write
instruction signal, the hit/miss buffer 232 applies external data DQ1-DQ4
to the first way decoder 216 and 1/8 decoder 231. In the SRAM section 220,
the first way decoder 216 selects four bus lines in the 16-bit wide data
bus in response to the way address WA0, WA1, and transmits the 4-bit data
to the SRAM cell array 221 through the sense amplifier 295. At a data
writing, the sense amplifier 295 does not operate and the data for writing
is simply transmitted to the SRAM cell array 221. The set decoder 222
selects one set in the SRAM cell array, while the SRAM column decoder 223
selects four columns in the selected set. At this time, the second way
decoder 294 also operates to select and activate only one of the four
ways. As a result, 4-bit data is written to the columns corresponding to
the selected way.
In parallel with the operation for the SRAM section 220, data is written to
the DRAM section 210. Though a data writing path to the DRAM section 210
is not expressly shown, the 1/8 decoder 231 selects four bus lines in the
32-bit internal data bus 230, and the data DQ1-DQ4 for writing is
transmitted through the four selected bus lines. The remaining bus lines
are maintained at a high impedance.
At a time of the data transfer for writing, 4-bit memory cells are already
selected in the DRAM section 210 by the row address A0-A8 and column
address A9-A17. The DRAM decoders 212 and 213 select 32 bits
simultaneously, and the data for writing appears on only 4 bits among the
32 bits. The remaining data bus lines are at the high impedance, and the
latching function of the DRAM sense amplifier 214 prevents adverse effect
on the non-selected bits.
The operation for writing data to the SRAM cell array 221 and writing data
to the corresponding memory cells (bits) in the DRAM cell array 211 at the
same time is called a write-through mode.
(iii) At a miss read
A reading operation in the SRAM section 220 based on the cache address
A9-A17 is the same as for hit read until the way address WA0, WA1 is
applied to the first way decoder 216.
At a cache miss, the way address WA0, WA1 is not applied to the first way
decoder 216 and the latter remains inoperative.
At this time, the external control signals RAS and CAS cause the DRAM
section 210 active to take the row and column addresses A0-A8 and A9-A17
therein. The DRAM row decoder 212 and DRAM column decoder 213 decode the
address A0-A17, and 32-bit data (one block) including the addressed 4-bit
data are read out for transmission to the internal data bus 230.
The 1/8 decoder 231, in response to the 3-bit address A15-A17, selects 4
bits from the 32-bit them to the hit/miss buffer 232. In response to a
cache miss signal M, the hit/miss buffer 232 selects the data received
from the 1/8 decoder 231, and sets the output data DQ1-DQ4, which have
been in the high impedance, to potential levels corresponding to the
received data.
In parallel with this data reading, the way address WA0, WA1 is applied to
the second way decoder 4 at a cache miss, after a fall of the signal RAS,
i.e. after an operation of the DRAM section 210. The second way decoder
294 also receives the 32-bit data from the internal data bus 230. The
second way decoder 294 is activated by the transfer control signal BT to
decode the way address WA0, WA1 and select a way. 32-bit data transferred
from the DRAM section 210 is written to one of the four ways selected by
the set decoder 222 and SRAM column decoder 223. As a result, data in the
corresponding memory cells in the SRAM cell array are renewed.
(iv) At a miss write
The cache miss signal M is applied along with a write instruction signal
(not shown) to the cache DRAM. At a cache miss, the signals RAS and CAS
activate the DRAM section 210 to select memory cells in the DRAM section
210 in accordance with the row address A0-A8 and column address A9-A17.
The hit/miss buffer 232 does not select the SRAM section 220 but selects
the DRAM section 210, or selects only the 1/8 decoder 231. As a result,
input data. DQ1-DQ4 is written to the 4-bit DRAM memory cells
corresponding to the external address A0-A17.
At this time, the SRAM section 220 engages only in a memory cell selecting
operation by means of the set decoder 222 and SRAM column decoder 223. At
the miss write, whether the 4-bit data written to the DRAM section 210 is
to be transferred to the SRAM section 220 or not is optional, and the
choice is made through the transfer control signal BT.
The basic concept of the conventional cache DRAM is such that a part of the
data in the DRAM cell array 211 are stored in the SRAM cell array 221 and,
upon an access request from an external processor, (i) the SRAM cell array
221 is accessed for data reading or writing if corresponding data is
stored in the SRAM cell array 221, and (ii) if corresponding data is not
found in the SRAM cell array 221, access is made to the DRAM cell array
211 in response to the cache miss signal for reading or writing the data
to/from the DRAM cell array 211.
Generally, access time of the SRAM is 10 to 20 ns which is faster than that
of the DRAM. However, the memory cells in the SRAM have a flip-flop type
construction, and at least four transistors are required for each cell.
The SRAM is inferior in the degree of integration and cost per bit to the
DRAM which requires one transistor for each cell. However, the DRAM
generally has an access time of 50 to 100 ns, which is slower than the
SRAM.
The cache DRAM has been devised to compensate for the drawbacks of the DRAM
and SRAM while retaining the advantages of the two. According to this
construction, an average access time may virtually be reduced to the same
level as that of the SRAM if the data to which access is requested from an
external processor is present in the SRAM section with a very high
probability. In this way, a large-capacity, high-speed memory device may
be realized which has a degree of integration comparable to the DRAM and
an access time comparable to the SRAM.
However, the conventional cache DRAM requires a tag that compares the
address of the memory cell requested by an external processor and the
address of each data block stored in the SRAM section, and determines from
the result of this comparison whether or not the requested data (or data
block) is present in the SRAM section. This poses a problem of enlarging
the device scale.
There is a mode called a write-back mode which is an improvement in system
efficiency to the write-through mode noted hereinbefore which writes data
to the DRAM section each time the data is written to the SRAM section.
According to the write-back mode as employed in a processing system having
main memory and cache memory, generally, data are written only to the
cache memory and the newly written data are transferred in a batch to the
main memory later on. Since the main memory is slower than the cache
memory and requires a long time for data writing, the write-back mode for
writing data in a batch from the cache memory to the main memory provides
a shorter total cycle time than the write-through mode does.
However, the write-back mode requires a buffer for storing the addresses
for the cache memory to which data have been rewritten, and a control
circuit for maintaining consistency in operation (writing timing,
operating speed and others) between cache memory and main memory. In the
cache DRAM, the DRAM corresponds to the main memory in an ordinary system,
and the SRAM to the cache memory. To effectuate the write-back mode in the
conventional cache DRAM, therefore, it is necessary to add, as external
components, a buffer for storing the addresses of the memory cells in the
SRAM section having the data renewed, and a control circuit for
controlling the batch transfer of the renewed data from the SRAM section
to the DRAM section. This results in an enlarged device and complicated
setting of the control timing. Thus, it is difficult to realize the
write-back mode in the conventional cache DRAM by means of a simple
construction.
Further, the tag must include, in addition to the tag memory for storing
the addresses of data stored in the SRAM section, the replacement logic
processor for selecting a way to which a new data is written at a cache
miss, and the comparator for determining a cache hit/miss. Consequently,
it is difficult to realize a tag with a simple construction.
SUMMARY OF THE INVENTION
An object of this invention is to provide an improved semiconductor memory
device containing cache which eliminates the drawbacks of the conventional
semiconductor memory device containing cache.
Another object of this invention is to provide a semiconductor memory
device containing cache which does not require a tag as an external
component for determining a cache hit/miss.
Yet another object of this invention is to provide a semiconductor memory
device containing cache which can support the write-back mode with ease.
A further object of this invention is to provide an improved operating
method for a semiconductor memory device containing cache.
A still further object of this invention is to provide an operating method
for a semiconductor memory device containing cache, which increases the
data read/write speed at a cache hit.
A still further object of this invention is to provide an operating method
for a semiconductor memory device containing cache, which carries out the
write-back mode with ease.
A semiconductor memory device containing cache according to this invention
comprises a DRAM cell array including a plurality of dynamic memory cells
arranged in a matrix of rows and columns, an SRAM cell array including a
plurality of static memory cells arranged in a matrix of rows and columns,
a transfer device for carrying out data transfer between the DRAM cell
array and SRAM cell array, and a match/mismatch detecting device for
addresses of data stored in the SRAM cell array, comparing an externally
applied address and the addresses stored therein, and generating a signal
indicative of a comparison result.
The semiconductor memory device according to this invention further
includes a first device responsive to a match detection signal from the
match/mismatch detecting device for connecting the memory cells in the
SRAM cell array corresponding to the external address to an internal data
transmission line, and a second device responsive to a mismatch detection
signal from the match/mismatch detecting device for making access to the
DRAM cells to select the memory cells corresponding to the external
address and connect the selected memory cells to the internal data
transmission lines.
The first device includes a device responsive to the match detection signal
from the match/mismatch detecting device for directly driving the rows in
the SRAM cell array. This direct drive device includes a device for
transmitting a signal for driving a row in the SRAM cell array generated
in response to an external address, to the row in the SRAM cell array in
response to the match detection signal.
The semiconductor device containing cache according to this invention
further includes an internal row address generating device responsive to
an externally applied row addresses for generating an internal row address
and applying at least a part thereof to the match/mismatch detecting
device, and a column selecting signal generating device responsive to
column address externally applied at substantially the same timing as the
external row address for generating a signal for selecting a column in the
DRAM cell array. The column selecting device and match/mismatch detecting
device are operable in parallel. The column selecting device includes a
device for generating a row drive signal for selecting a row in the SRAM
cell array.
The match/mismatch detecting device includes a CAM cell array having match
detection lines extending in a row direction, data input lines extending
in a column direction, a plurality of content addressable memories
arranged at respective crossings between the match detection lines and
data input lines, and a plurality of CAM word lines extending in the row
direction for selecting one row of the content addressable memories. The
rows and columns of this CAM cell array are provided corresponding to
those of the SRAM cell array. The content addressable memories in one row
store an address of data stored in the SRAM cell array.
The match/mismatch detecting device applies the match detection signal to
the first device to drive a corresponding row in the SRAM cell array, and
includes a device for generating a signal indicative of a cache hit/miss
in response to a signal potential on the rows in the SRAM cell array.
The second device includes a device responsive to the mismatch detection
signal from the detecting device for temporarily disregarding the internal
address applied to the detecting device, reading from the detecting device
address corresponding to the external address, selecting corresponding
dynamic memory cells in the DRAM cell array and corresponding static
memory cells in the SRAM cell array in response to the address thus read
out, and writing the data read from the selected static memory cells to
the selected dynamic memory cells through the transfer device.
The second device includes a device for activating the external address
again after the data transfer from the SRAM cell array to the DRAM cell
array, storing the external address in a memory of the detecting device,
selecting memory cells in the DRAM cell array corresponding to the
external address and connecting the selected memory cells to the internal
data transmission line.
The DRAM cell array is divided into a plurality of blocks one for each
plurality of the columns. The SRAM cell array and CAM cell array are also
divided into a plurality of blocks corresponding to the blocks of the DRAM
cell array. The match/mismatch detecting operation is carried out on the
block by block basis.
In the memory device according to this invention, the addresses of data
stored in the SRAM cell array as cache memory are stored in the detecting
device. The detecting device detects a match/mismatch between the stored
addresses and an external address. Thus, a cache hit/miss is determined
within the semiconductor memory device.
Where the address memory of the detecting device comprises content
addressable memory cells, a match/mismatch between the stored data address
and external address may be detected without an additional dedicated
comparator. With the match detection lines arranged in a one-to-one
relationship with the rows in the SRAM cell array, the rows in the SRAM
cell array may be driven at high speed at a cache hit.
The application of the row and column addresses to the semiconductor memory
device substantially at the same timing allows the detecting operation by
the detecting device and the operation for selecting the column and row in
the DRAM cell array or SRAM cell array to be carried out in parallel. This
will further expedite determination of a cache hit/miss, and realize
access time and cycle time comparable, despite the detecting operation of
the detecting device, to those of a cache DRAM including no such detecting
device.
Further, a hierarchical structure is employed for paths for transmission of
cache hit/miss signal, i.e. a path for applying the signal from the
detecting device to the first device, and a path for generating the signal
determining a cache hit/miss in response to word line (row) potentials of
the SRAM cell array. This simplifies the entire device and facilitates
layout of the detecting device. At a cache hit determination, the memory
cell selecting operation for the SRAM cell array is substantially
completed, which increases the access time of this semiconductor memory
device.
At a cache miss, the data are always transferred for writing from the SRAM
cell array to the DRAM cell array. At this time, the addresses stored in
the detecting device are used for selection of the SRAM cell array and
DRAM cell array. This realizes a write-back operation for transferring
data from the SRAM cell array to the DRAM cell array easily without
necessitating an extra memory circuit for the write-back and a complicated
timing control circuit.
The foregoing and other objects, features, aspects and advantages of the
present invention will become more apparent from the following detailed
description of the present invention when taken in conjunction with the
accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram showing a conceptual construction of a processing
system using a conventional semiconductor memory device containing cache,
FIG. 2 is a diagram showing an overall construction of the conventional
semiconductor memory device containing cache,
FIG. 3 is a diagram showing an overall construction of a semiconductor
memory device containing cache according to one embodiment of this
invention,
FIG. 4A is a diagram showing a construction of a cache element including a
SRAM cache and a CAM matrix according to one embodiment of this invention,
FIG. 4B is a diagram showing a relationship between a DRAM cell array and
cache elements,
FIG. 5 is a diagram showing a construction of a principal portion of the
semiconductor memory device containing cache according to one embodiment
of this invention,
FIG. 6 shows details of a DRAM cell section shown in FIG. 5,
FIG. 7 is a diagram showing a specific construction of an interface driver
shown in FIG. 5,
FIG. 8 is a diagram showing a specific construction of a CAM cell shown in
FIG. 5,
FIG. 9 is a flowchart showing a data reading operation of the semiconductor
memory device containing cache according to this invention,
FIG. 10 shows a relationship in time between a decoding operation and a tag
match/mismatch detecting operation of a Y-decoder in the semiconductor
memory device containing cache according to this invention,
FIG. 11 is a diagram showing waveforms of signals, through simulation,
occurring on a hit read in the semiconductor memory device containing
cache according to this invention,
FIG. 12 is a diagram showing waveforms of signals occurring on a miss read
in the semiconductor memory device containing cache according to this
invention,
FIG. 13 is a diagram schematically showing an architecture of a
semiconductor memory device containing cache according to another
embodiment of this invention, and
FIG. 14 is a diagram schematically showing a memory architecture of a
semiconductor memory device containing cache according to a further
embodiment of this invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 3 schematically shows an overall construction of a semiconductor
memory device according to one embodiment of this invention. Referring to
FIG. 3, the semiconductor memory device containing cache according to this
invention includes a DRAM cell array 300 as main memory, an SRAM cell
array 310 as cache memory, and a CAM (content addressable memory) matrix
320 as cache tag.
The DRAM cell array 300 includes a plurality of dynamic memory cells
arranged in a matrix of rows and columns, and is divided into blocks each
plurality of the columns.
The SRAM cell array 310 includes a plurality of static memory cells
| | |
