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Claims  |
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What is claimed is:
1. A semiconductor memory device with a built-in cache memory capable of a
first operation mode in which a normal access is made and a second
operation mode in which a high speed access is made, comprising:
a memory cell array (1) having a plurality of memory cells (MC) arranged to
have a plurality of rows and a plurality of columns,
said memory cell array (1) being divided into a plurality of blocks (B1 to
B16), said each block being divided into a plurality of sub blocks each
having a plurality of columns;
signal receiving means (5, 8; 5a, 5b, 5c) which, at a time of said first
operation mode, in a time-sharing manner or simultaneously, receives a row
address signal (RA) and a column address signal (CA) applied externally,
while, at a time of said second operation mode, simultaneously receiving
block selecting signals (B0, B1) and a column address signal (CA) applied
externally;
a first selecting means (19) responsive to a part of said row address
signals (FA8, RA9) for selecting any of said plurality of blocks (B1 to
B16) at the time of said first operation mode, and responsive to said
block selecting signals (B0, B1) for selecting any of said plurality of
blocks (B1 to B16) at the time of said second operation mode;
a second selecting means (2) responsive to the remaining of said row
address signals (RA0 to RA7) for selecting any row in said selected block
at the time of said first operation mode;
a plurality of sense amplifier means (14a) associated with said plurality
of columns in said each block for amplifying and holding the information
read out from said selected row;
a plurality of information holding means (16a)provided in response to
associated with said plurality of columns in said each block for holding
information;
a third selecting means (18) responsive to a part of said column address
signals (CA5 to CA9) for selecting any of said plurality of sub blocks in
said selected block at the time of said first operation mode;
an information transferring means (15) for transferring information between
the row selected by said second selecting means (2) and a corresponding
information holding means (16a) in said selected sub block at the time of
said first operation mode; and
a fourth selecting means (19) responsive to said column address signal (CA)
for selecting any of the plurality of sense amplifier means (14a) in said
selected block at the time of said first operation mode, and responsive to
said column address signal (CA) for selecting any of the plurality of
information holding means (16a) corresponding to said selected block at
the time of said second operation mode,
said first selecting means (19) and said fourth selecting means (19) being
controlled to operate simultaneously at the time of said second operation
mode.
2. A semiconductor memory device according to claim 1, wherein
said first fourth selecting means comprise a column decoder (19),
said second selecting means comprises a row decoder (2), and
said third selecting means comprises a block decoder (18).
3. A semiconductor memory device according to claim 1, wherein
said signal receiving means comprises:
an address buffer (5) for receiving a column address signal (CA) and a row
address signal (RA) in a time-sharing manner; and
a block selecting signal buffer (8) for receiving block selecting signals
(B0, B1).
4. A semiconductor memory device according to claim 1, wherein
said signal receiving means comprises:
a first row address buffer (5b) for receiving a part of the row address
signals (RA8, RA9);
a second row address buffer (5a) for receiving the remaining of the row
address signals; and
a column address buffer (5c) for receiving a column address signal CA),
the part of said row address signals (RA8, RA9) being used as said block
selecting signals (B0, B1) at the time of said second operation mode.
5. A semiconductor memory device according to claim 1, wherein
said first operation mode corresponds to a cache miss, and
said second operation mode corresponds to a cache hit.
6. A semiconductor memory device according to claim 5 further comprising:
a cache hit buffer (13) for receiving a cache hit signal at the time of a
cache hit,
said information transferring means (15) being responsive to said cache hit
signal to be enabled, and
said third selecting means (18) being responsive to said cache hit signal
to be disabled.
7. A semiconductor memory device according to claim 1, wherein
said memory cell array (1), said signal receiving means (5, 8; 5a, 5b, 5c),
said first selecting means (19), said second selecting means (2), said
plurality of sense amplifier means (14a), said third selecting means (18),
said information transferring means (15), and said fourth selecting means
(19) are formed on one chip.
8. A cache memory system comprising:
decision means (25, 26) for deciding when a cache hit and a cache miss
occur;
address generating means (22, 23) for generating a row address signal (RA)
and a column address signal (CA) at a time of a cache miss, and for
generating block selecting signals (B0, B1) and a column address signal
(CA) at a time of a cache hit;
a semiconductor memory device including
a memory cell array (1) having a plurality of memory cells (MC) arranged to
have a plurality of rows and a plurality of columns,
said memory cell array (1) being divided into a plurality of blocks (B1 to
B16), and said each block being divided into a plurality of sub blocks
each having a plurality of columns,
signal receiving means (5, 8; 5a, 5b, 5c) which, at the time of a cache
miss, in a time-sharing manner or simultaneously, receive a row address
signal (RA) and a column address signal (CA) applied externally, while, at
the time of said cache hit, simultaneously receiving block selecting
signals (B0, B1) and a column address signal (CA) applied externally,
a first selecting means (19) responsive to a part of said row address
signals (RA8, RA9) for selecting any of said plurality of blocks (B1 to
B16) at the time of a cache miss while being responsive to said block
selecting signals (B0, B10) for selecting any of said plurality of blocks
(B1 to B16) at the time of a cache hit,
a second selecting means (2) responsive to the remaining of said row
address signals (RA0 to RA7) for selecting any row in said selected block
at the time of a cache miss,
a plurality of sense amplifier means (14a) associated with said plurality
of columns in said each block for amplifying and holding the information
read out from said selected row,
a plurality of information holding means (16a) associated with said
plurality of columns in said each block for holding information,
a third selecting means (18) responsive to apart of said column address
signals (CA5 to CA9) for selecting any of said plurality of sub blocks in
said selected block at the time of a cache miss,
an information transferring means (15) for transferring information between
the row selected by said second selecting means (2) and a corresponding
information holding means (16a) in said selected sub block at the time of
a cache miss,
a fourth selecting means (19) responsive to said column address signal (CA)
for selecting any of the plurality of sense amplifier means (14a) in said
selected block at the time of a cache miss, and responsive to said column
address signal (CA) for selecting any of the plurality of information
holding means (16a) corresponding to said selected block at the time of a
cache hit,
said first selecting means (19) and said fourth selecting means (19) being
controlled to operate simultaneously at the time of a cache hit.
9. An operation method of a semiconductor memory device with a built-in
cache memory, said semiconductor memory device comprising a memory cell
array (1) having a plurality of memory cells (MC) arranged to have a
plurality of rows and a plurality of columns, said memory cell array (1)
being divided into a plurality of blocks (B1 to B16), and said each block
being divided into a plurality of sub blocks each having a plurality of
columns; a plurality of sense amplifier means (14a) provided in response
to said plurality of columns in said each block for amplifying and holding
the information read out from a corresponding column; and a plurality of
information holding means (16a) provided in response to said plurality of
columns in said each block for holding the information,
said method comprising the steps of:
receiving, in a time-sharing manner or simultaneously, a row address signal
(RA) and a column address signal (CA) applied externally, at a time of
said first operation mode, and simultaneously receiving block selecting
signals (B0, B1) and a column address signal (CA) applied externally, at a
time of said second operation mode;
selecting any of said plurality of blocks (B1 to B16) in response to a part
of said row address signals (RA0, RA9) at the time of said first operation
mode;
selecting any row in said selected block in response to the remaining of
said row address signals (RA0 to RA7) at the time of said first operation
mode;
selecting any of said plurality of sub blocks in said selected block in
response to a part of said column address signals (CA5 to CA9) at the time
of said first operation mode;
selecting any of the plurality of sense amplifier means in said selected
block in response to said column address signal (CA) at the time of said
first operation mode;
transferring information between the selected row and a corresponding
information holding means (16a) in said selected sub block at the time of
said first operation mode;
selecting any of said plurality of blocks (B1 to B16) in response to said
block selecting signals (B0, B1), and at the same time, selecting any of
the plurality of information holding means (16a) corresponding to said
selected block in response to said column address signal (CA) at the time
of said second operation mode.
10. An operation method of a cache memory system using a semiconductor
memory device with a built-in cache memory, said semiconductor memory
device comprising a memory cell array (1) having a plurality of memory
cells (MC) arranged to having a plurality of rows and a plurality of
columns, said memory cell array (1) being divided into a plurality of
blocks (B1 to B16), and said each block being divided into a plurality of
sub blocks each having a plurality of column; a plurality of sense
amplifier means (14a) provided in response to said plurality of columns in
said each block for amplifying and holding the information read out from
said selected row; and a plurality of information holding means (16a)
associated with said plurality of columns in said each block for holding
information,
said method comprising the steps of:
dividing when a cache hit and a cache miss occur;
generating a row address signal (RA) and a column address signal (CA) at a
time of a cache miss while generating block selecting signals (B0, B1) and
a column address signal (CA) at a time of a cache hit;
receiving, in a time-sharing manner or simultaneously, a row address signal
(RA) and a column address signal (CA) applied externally, at the time of a
cache miss while simultaneously receiving block selecting signals (B0, B1)
and a column address signal applied externally, at the time of a cache
hit;
selecting any of said plurality of blocks (B1 to B16) in response to a part
of said row address signals (RA8, RA9) at the time of a cache miss;
selecting any row in said selected block in response to the remaining of
said row address signals (RA0 to RA7) at the time of a cache miss;
selecting any of said plurality of sub blocks in said selected block in
response to a part of said column address signals (CA5 to CA() at the tie
of a cache miss;
selecting any of the plurality of sense amplifier means (16a) in said
selected block in response to said column address signal (CA) at the time
of a cache miss;
transferring information between the selected row and a corresponding
information holding means (16a) in said selected sub block at the time of
a cache miss;
selecting any of said plurality of blocks (B1 to B16) in response to said
block selecting signals (B0, B1), and at the same time, selecting any of
the plurality of information holding means (16a) corresponding to said
selected block in response to said column address signal (CA) at the time
of a cache hit.
11. A semiconductor memory device with a built-in cache memory capable of a
first operation mode in which a normal access in made and a second
operation mode in which a high-speed access is made, comprising:
a memory cell array (1) having a plurality of memory cells (MD) arranged to
have a plurality of rows and a plurality of columns,
said memory cell array (1) being divided into a plurality of blocks (B1 to
B16);
signal receiving means (5, 8; 5a, 5b, 5c) which, at a time of said first
operation mode, in a time-sharing manner or simultaneously, receive a row
address signal (RA) and a column address signal (CA) applied externally
while, at a time of said second operation mode, simultaneously receiving
block selecting signals (B0, B1) and a column address signal (CA) applied
externally;
a first selecting means (19) responsive to a part of said row address
signals (RA8, RA9)for selecting any of said plurality of blocks (B1 to
B16) at the time of said first operation mode while being responsive to
said block selecting signals (B0, B1) for selecting any of said plurality
of blocks (B1 to B16) at the time of said second operation mode;
a second selecting means (2) responsive to the remaining of said row
address signals (RA0 to RA7) for selecting any row in said selected block
at the time of said first operation mode;
a plurality of information holding means (14a) associated with said
plurality of columns in said each block for holding the information read
out from said selected row; and
a third selecting means (19) responsive to said column address signal (CA)
for selecting any of the plurality of information holding means (14a) in
said selected block at the time of said first and second operation modes,
said first selecting means (19) and said third selecting means (19) being
controlled to operate simultaneously at the time of said second operation
mode.
12. A semiconductor memory device according to claim 11, wherein
said first and second selecting circuits comprise a column decoder (19),
and
said second selecting means comprises a row decoder (2).
13. A semiconductor memory device according to claim 11, wherein
said signal receiving means comprises:
an address buffer (5) for receiving a column address signal (CA) and a row
address signal (RA) in a time-sharing manner; and
a block selecting signal buffer (8) for receiving block selecting signals
(B0, B1).
14. A semiconductor memory device according to claim 11, wherein
said signal receiving means comprises:
a first row address buffer (5b) for receiving a part of the row address
signals (RA8, RA9);
a second row address buffer (5a) for receiving the remaining of the row
address signals (RA0 to RA7); and
a column address buffer (5c) for receiving a column address signal (CA),
the part of said row address signals (RA8, RA9) being used as said block
selecting signals (B0, B10at the time of said second operation mode.
15. A semiconductor memory device according to claim 11, wherein
said first operation mode corresponds to a cache miss, and
said second operation mode corresponds to a cache hit.
16. A semiconductor memory device according to claim 11, wherein
said memory cell array (1), said signal receiving means (5, 8; 5a, 5b, 5c),
said first selecting means (19), said second selecting means (2), said
plurality of information holding means (14a), said third selecting means
(18), said information transferring means (15), and said fourth selecting
means (19) are formed on one chip.
17. A semiconductor memory device according to claim 11, wherein
said plurality of information holding means comprises a plurality of sense
amplifier means (14a) associated with said plurality of columns in said
each block for amplifying and holding the information read out from said
selected row;
18. A cache memory system comprising:
decision means (25, 26) for deciding when a cache hit and a cache miss
occur;
address generating means (22, 23) for generating a row address signal (RA)
and a column address signal (VA) at a time of a cache miss while
generating block selecting signals (B0, B1) and a column address signal
(CA) at a time of a cache hit; and
semiconductor memory devices (2b, 2c) including:
a memory cell array (1) having a plurality of memory cells (MC) arranged to
have a plurality of rows and a plurality of columns,
said memory cell array (1) being divided into a plurality of blocks (B1 to
B16);
signal receiving means (5, 8; 5a, 5b, 5c) which, at the time of a cache
miss, in a time-sharing manner or simultaneously, receive a row address
signal (RA) and a column address signal (CA) applied externally while, at
the time of a cache hit, simultaneously receiving block selecting signals
(B0, B1) and a column address signal applied externally;
a first selecting means (19) responsive to a part of said row address
signals (RA8, RA9) for selecting any of said plurality of blocks (B1 to
B16) at the time of a cache miss while being responsive to said block
selecting signals (B0, B1) for selecting any of said plurality of blocks
(B1 to B16) at the time of a cache hit;
a second selecting means (2) responsive to the remaining of said row
address signals (RA0 RA7) for selecting any row in said selected block at
the time of said cache miss;
a plurality of sense amplifier means (14a) associated with said plurality
of columns in said each block for amplifying and holding information read
out from said selected row; and
a third selecting means (19) responsive to said column address signal (CA)
for selecting any of the plurality of sense amplifier means (14a) in said
selected block at the time of said cache miss and cache hit,
said first selecting means (19) and said third selecting means (19) being
controlled to operate simultaneously at the time of said cache hit.
19. An operation method of a semiconductor memory device with a built-in
cache memory, said semiconductor memory device comprising a memory cell
array (1) having a plurality of memory cells (MC) arranged to have a
plurality of rows and a plurality of columns, said memory cell array being
divided into a plurality of blocks (B1 to B16); and a plurality of sense
amplifier means (14a) associated with said plurality of columns in said
each block for amplifying and holding the information read out from a
corresponding column,
said method comprising the steps of:
receiving, in a time-sharing manner or simultaneously, a row address signal
(RA) and a column address signal (CA) applied externally at time of a
first operation mode while simultaneously receiving block selecting
signals (B0, B1) and a column address signal (CA) applied externally at a
time of a second operation mode;
selecting any of said plurality of blocks (B1 to B16) in response to a part
of said row address signals (RA8, RA9) at the time of said first operation
mode;
selecting any row in said selected block in response to the remaining of
said row address signals (RA0 to RA7) at the time of said first operation
mode;
selecting any of the plurality of sense amplifier means (14a) in said
selected block in response to said column address signal (CA) at the time
of said first operation mode;
selecting any of said plurality of blocks (B1 to B16) in response to said
block selecting signals (B0, B1), and at the same time, selecting any of
the plurality of sense amplifier means (14a) in said selected block in
response to said column address signal (CA) at the time of said second
operation mode.
20. An operation method of a cache memory system using a semiconductor
memory device with a built-in cache memory, said semiconductor memory
device comprising a memory cell array (1) having a plurality of memory
cells (MC) arranged to have a plurality of rows and a plurality of
columns,
said memory cell array (1) being divided into a plurality of blocks (B1 to
B16); and a plurality of sense amplifier means (14a) associated with said
plurality of columns in said each block for amplifying and holding the
information read out from said selected row,
said method comprising the steps of:
deciding when a cache hit and a cache miss occurs;
generating a row address signal (RA) and a column address signal (CA) at a
time of a cache miss while generating block selecting signal (B0, B1) and
a column address signal (CA) at a time of a cache hit;
receiving, in a time-sharing manner or simultaneously, said row address
signal (RA) and a column address signal (CA) at the time of a cache miss;
selecting any of said plurality of blocks (B1 to B16) in response to a part
of said row address signals (RA8, RA9) at the time of a cache miss;
selecting any row in said selected block in response to the remaining of
said row address signals (RA0 to RA7) at the time of said cache miss;
selecting any of the plurality of sense amplifier means (14a) in said
selected block in response to said column address signal (CA) at the time
of a cache miss;
simultaneously receiving said block selecting signals B0, B1) and a column
address signal (CA) at the time of a cache hit;
selecting any of said plurality of blocks (B1 to B16) in response to said
block selecting signals (B0, B1), and at the same time, selecting any of
the plurality of sense amplifier means (14a) in said selected bock in
response to said column address signal (CA) at the time of a cache hit.
21. A semiconductor memory device operable in response to an externally
applied cache hit/miss signal, comprising:
a memory cell array (1) including a plurality of memory cells arranged in a
plurality of rows and columns, said memory cell array comprising a
plurality of blocks (B1-B16) of columns, each block being divided into a
plurality of sub blocks each comprising a plurality of said columns;
a plurality of sense amplifier circuit means (14a) activatable for
providing signals representing data stored in a memory cell in each of
said columns;
a plurality of information holding circuit means (16a) for holding
information corresponding to the signals provided by said sense amplifier
circuit means;
first selecting circuit means (19) for selecting one of said plurality of
blocks of columns;
second selecting circuit means (2) for selecting one row in a selected
block;
third selecting circuit means (18) for selecting one sub block in a
selected block;
control means responsive to said row address signal and said cache miss
signal to activate said first, second and third selecting circuit means,
said control means further comprising means responsive to the activation
of said first, second and third selecting circuit means for connecting
sense amplifier circuit means, associated with the columns of the selected
sub block, with corresponding information holding circuit means to
transfer thereto information represented by the sense amplifier signals;
and
fourth selecting circuit means (19) for immediately selecting one block to
access information held in a corresponding information holding means in
response to a column address signal, an externally applied block selecting
signal and said cache hit signal.
22. A semiconductor memory device comprising:
a plurality of memory array blocks (B1-B16) each having a plurality of
memory cells arranged in a plurality of rows and columns,
a plurality of row decoder means (2) each corresponding to a respective one
of said memory array blocks, each row decoder receiving row address
signals for selecting one of said rows in the corresponding memory array
block,
a plurality of sense amplifier group means (14) each corresponding to a
respective one of said memory array blocks, each sense amplifier group
means comprising a plurality of sense amplifiers arranged in respective
columns of the corresponding memory array block,
a plurality of information holding group means (16) each corresponding to a
respective one of said memory array blocks, each information holding group
means comprising a plurality of information holding means arranged in
respective columns of the corresponding memory array block,
a plurality of transfer group means (15) comprising a plurality of transfer
means arranged in respective columns and each connected between
corresponding sense amplifier group means and corresponding information
holding group means and divided into a plurality of sub blocks,
and selecting means (18) for selecting and activating one sub bock of said
transfer group means in response to a cache miss signal, a portion of said
row address signals and a portion of column address signals. |
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Claims |
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Description |
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CROSS-REFERENCE TO RELATED APPLICATIONS
This application is related to copending applications Ser. Nos. 228,589
filed Aug. 5, 1988, 248,712 filed Sep. 26, 1988, 254,233 filed Oct. 6,
1988, 266,060 filed Nov. 2, 1988, 266,601 filed Nov. 3, 1988 commonly
assigned with the present invention.
BACKGROUND OF THE INVENTION
1. Filed of the Invention
The invention relates generally to semiconductor memory devices, and, more
particularly, semiconductor memory devices with cache memories integrated
on the same chip.
2. Description of the Background Art
A main memory contained in a computer system comprises a dynamic random
access memory (hereinafter referred to as DRAM) of low speed and large
capacity, therefore of low cost. In order to improve the cost performance
of a computer system, a high speed memory of small capacity is often
provided as a high speed buffer between a main memory and a central
processing unit (hereinafter referred to as CPU). This high speed buffer
is referred to as cache memory. In this cache memory, the blocks of data
which CPU is most likely to require is copied and stored from the main
memory. In the DRAM, the state in which the data stored in the address,
which the CPU was to access to, also exists in the cache memory is called
a "cache hit". In this case the CPU accesses a high speed cache memory,
and reads out the required data from the cache memory. In the DRAM, the
state in which the data stored in the address, which the CPU was to access
to, does not exist in the cache memory is called a "cache miss". In this
case, the CPU accesses a low speed main memory, and transfers the block,
which the data belongs to, from the DRAM to the cache memory at the same
time when it reads out the required data from the main memory.
However, such a cache memory system requires an expensive high speed
memory, so that it can not be used in a small size computer system in
which cost is valued highly. Therefore, conventionally, a simplified cash
system was constituted, utilizing a page mode or a static column mode
contained in a general purpose DRAM.
FIG. 10 is a block diagram showing a fundamental configuration of a
conventional DRAM device capable of operating in a page mode or in a
static column mode.
In FIG. 10, in a memory cell array 50, a plurality of word lines and a
plurality of bit line pairs are arranged to intersect each other with a
memory cell provided at each of their intersections. In FIG. 10, one word
line WL, one bit line pair BL, BL, and one memory cell MC provided at the
intersection of the word line WL and the bit line BL are only
representatively shown.
The word line in the memory cell array 50 is connected to a row decoder 53
through a word driver 52. The bit line pair in the memory cell array is
connected to a column decoder 56 through a sense amplifier portion 54 and
an I/O switch 55. A row address buffer 57 and a column address buffer 58
are provided with multiplexed signals MPXA which are a row address signal
RA and a column address signal CA multiplexed. The row address buffer 57
supplies the row address signal RA to the row decoder 53, and the column
address buffer 53 supplies the column address signal CA to the column
decoder 56. An output buffer 59 and an input buffer 60 are connected to
the I/O switch 55.
FIGS. 11A, 11B and 11C respectively show operation waveform diagrams of a
normal read cycle, a page mode cycle and a static column mode cycle of the
DRAM device.
In the normal read cycle shown in FIG. 11A, the row address buffer 57
initially accepts the multiplexed address signal MPXA at the fall edge of
a row address strove signal RAS, and supplies the same as a row address
signal RA to the row decoder 53. The row decoder 53 selects one of a
plurality of word lines in response to the row address signal RA. The
selected word line is activated by the word driver 52. As a result,
information stored in the plurality of memory cells connected to the word
line is each read out on a corresponding bit line, and the information is
detected and amplified by the sense amplifier portion 54. At this time, a
row of information of the memory cell is latched in the sense amplifier
portion 54.
Subsequently, the column address buffer 58 accepts a multiplexed address
signal MPXA at the fall edge of a column address strobe signal CAS, and
supplies the same as a column address signal CA to the column decoder 56.
The column decoder 56 selects one bit out of one row of information
latched in the sense amplifier portion 54 in response to the column
address signal CA. This selected information is supplied to the outside as
an output data Dout through the I/O switch 55 and the output buffer 59.
In this case, the access time (RAS access time) t.sub.RAC corresponds to
the time period from the fall edge of the row address strobe signal RAS to
the time when the output data Dout becomes valid. In this case, the cycle
time t.sub.c is the sum of the time during which the device is in an
active state and the RAS precharge time t.sub.RP. As a standard value, in
the case in which t.sub.RAC =100 ns, t.sub.c is about 200 ns.
In the page mode cycle and the static column mode cycle shown in FIGS. 11B
and 11C, a memory cell on the same row may be accessed by changing the
column address signal CA. In the page mode cycle, the column address
signal CA is latched at the fall edge of the column address strobe signal
CAS. In the static column mode cycle, an access is made only by the change
of the column address signal CA as in the static RAM (SRAM).
The CAS access time t.sub.CAC of the page mode cycle and the address access
time t.sub.AA of the static column mode cycle attain a value of about 1/2
of the RAS access time t.sub.RAC, and when t.sub.RAC =100 ns, they are
about 50 ns. In this case, the cycle time, which depends on the CAS
precharge time t.sub.CP with regards to the page mode cycle, is shortened
to be a value of about 50 ns, which is similar to the static column mode
cycle.
FIG. 12 is a diagram showing a fundamental configuration of a 4M bit DRAM
device of a conventional 1M .times.4 bits structure capable of operating
in a page mode or in a static column mode.
In FIG. 12, the DRAM device 20 is formed on one chip. A memory cell array 1
is divided into 16 array blocks B1 to B16. As shown in FIG. 13, a sub
memory cell array 101 comprises blocks B1, B5, B9, B13, and corresponds to
an input and output data DQ1. Similarly, a sub memory cell array 102
corresponds to an input and output data DQ2, a sub memory cell array 103
corresponds to an input and output data DQ3, and a sub memory cell array
104 corresponds to an input and output data DQ4.
The address buffer 5 accepts externally applied address signals A0 to A9 at
the fall edge of the row address strobe signal RAS supplied from an RAS
buffer 6, and supplies the same as a row address signal RA to a row
decoder 2. The row address signal RA comprises row address signals RA0 to
RA9 of 10 bits. The address buffer accepts externally applied address
signals A0 to A9 at the fall edge of the column address strobe signal CAS
supplied from a CAS buffer 7, and supplies it as a column address signal
CA to a column decoder 3. The column address signal CA comprises column
address signals CA0 to CA9 of 10 bits. A sense control circuit 9 is
responsive to row address signals RA8, RA9 of 2 bits among the row address
signals RA to cause a sense amplifier portion 4 corresponding to four of
the 16 array blocks B1 to B16 to operate.
A data output buffer 11 is responsive to an externally applied output
enable signal OE to supply the information of 4 bits read out from the
memory cell array 1 as output data DQ1 to DQ4 to the outside. A write
buffer 10 is responsive to an externally applied write enable signal WE to
supply a write signal W to a data input buffer 12. The data input buffer
12 is responsive to the write signal W to supply externally applied input
data DQ1 to DQ4 of 4 bits to the memory cell array 1.
FIG. 14 is a block diagram fully showing the configuration of the sub
memory cell array 101 corresponding to the input and output data DQ1. As
shown in FIG. 14, the sub memory cell array 101 of 1M bits corresponding
to one input and output bit is divided into four array blocks B1, B5, B9,
B13 of 1K.times.256 bits respectively. Each array block is provided with a
sense amplifier group 14 comprising a plurality of sense amplifiers, an
I/O switch 17 and a column decoder 19. One of four array blocks B1, B5,
B9, B13 is selectively driven in response to 2 bit row address signals
RA8, RA9. In the configuration shown in FIG. 14, the number of sense
amplifiers is increased, and the length of each bit line is shortened. As
a result, the read voltage which is read out from the memory cell to the
sense amplifier may be increased. In addition, by means of a dividing
operation, it becomes possible to reduce power consumption.
In the array block selected by the row address signals RA8, RA9, one word
line (not shown) is selected by the row decoder 2. The information stored
in a plurality of memory cells (not shown) connected to the word line is
supplied to the each corresponding sense amplifier through the each
corresponding bit line (not shown). The information is sensed and
amplified by the sense amplifiers.
In the example of FIG. 14, the sense amplifier group 14 corresponding to
each array block comprises 1K (1024) sense amplifiers. In this case, one
of four sense amplifier groups 14 provided corresponding to four array
blocks B1, B5, B9, B13 is selectively driven in response to the row
address signals RA8, RA9 of 2 bits. When the sense amplifier is activated,
a row (1K.times.4 bits) of information is latched in the four sense
amplifier groups 14. Accordingly, the page mode and the static column mode
shown in FIGS. 11B and 11C are made possible by selecting a sense
amplifier through the column decoder 19 by way of the column address
signal CA.
FIG. 15 is a block diagram showing a configuration of a simplified cache
system utilizing a page mode or a static column mode of the DRAM devices
in FIGS. 12 to 14. FIG. 16 is a operation waveform diagram of the
simplified cache system of FIG. 15.
In FIG. 15, a main memory 21 is formed to have capacity of 4M bytes by 8
DRAM devices 20 of 1M.times.4 bit structure. In this case, 20 (2.sup.20
=1048576=1M) address lines are required before a row address signal and a
column address signal are multiplexed. However, the row address signal RA
and the column address signal CA are multiplexed by an address multiplexer
22, so that 10 address lines are in fact connected to each DRAM device 20.
The operation of the simplified cache system of FIG. 15 will now be
described with reference to the operation waveform diagram of FIG. 16.
An address generator 23 generates an address signal AD of 20 bits
corresponding to the data required by a CPU 24. A latch (tag) 25 holds the
row address signal corresponding to the data selected in the previous
cycle. A comparator 26 compares the 10 bit row address signal RA among 20
bit address signals AD with the row address signal held in the latch 25.
If those coincide with each other, it means the same row as that in the
previous cycle has been accessed in the present cycle. This is called a
"cache hit". In this case the comparator 26 generates a cache hit signal
CH.
A state machine 27 is responsive to the cache hit signal CH to perform a
page mode control in which the column address strobe signal CAS is toggled
while maintaining the row address strobe signal RAS at a low level. At
this time, the address multiplexer 22 applies a column address signal CA
to each DRAM device 20 (see FIG. 16). As a result, data corresponding to
the column address signal CA is outputted by way of the data group latched
in the sense amplifier portion of each DRAM device 20. Thus, at the time
of a cache hit, an output data, at a high speed, may be obtained from each
DRAM device 20 at the access time t.sub.CAC.
If the row address signal RA generated from the address generator 23 and
the row address signal held in the latch 25 do not coincide with each
other, it means a row different from that of the previous cycle has been
accessed in the present cycle. This is called a "cache miss".
In this case, the comparator 25 does not generate a cache hit signal CH.
The state machine 27 performs an RAS/CAS control of the normal read cycle,
and the address multiplexer 22 in turn applies the row address signal RA
and the column address signal CA to each DRAM device 20 (see FIG. 16).
Thus, at the time of a cache miss, a normal read cycle, which starts with
a precharge by the row address strobe signal RAS, is initiated, and an
output data, at a low speed, is obtained at the access time t.sub.RAC.
Therefore, the state machine 27 generates a wait signal Wait to set the
CPU 24 in a stand-by state. At the time of a cache miss, a new row address
signal RA is held in the latch 25.
In the simplified cache system of FIG. 15, the data of one row of each
array block in each DRAM device 20 (1024 bits in the case of 1M.times.4
bit DRAM device) is latched as one data block in the sense amplifier
group. Accordingly, the size of one data block is unnecessarily large, so
that the data blocks (the number of entries) held in the latch (tag) 25
become insufficient. For example, in the simplified cache system of FIG.
15, the number of entries is 1. Accordingly, there is a problem that the
rate in which a cache hit occurs (cache hit rate) is low.
SUMMARY OF THE INVENTION
One object of the invention is to obtain a semiconductor memory device with
a built-in cache memory having a data block of appropriate size, which is
capable of constituting a simplified cache system in which a cache hit
rate is improved by the increased number of entries, and the cost
performance thereof is high.
Another object of the present invention is to expand the operational margin
of the semiconductor memory device with a built-in cache memory to
implement a simplified cache system in which power consumption is reduced.
The semiconductor memory device with a built-in cache memory in accordance
with a first aspect of the present invention is direct | | |
