A method and system for processing multiple requests for data residing at the same memory address. The multiple requests are associated with an individual duplicate bit flag that indicates whether the request can be processed. Thus, manipulation of the duplicate bit flag controls the order of processing for each of the received requests, thereby maintaining data coherency and integrity.

An Invalidation Queue (IQ) arrangement in a computer system having Main Memory and, Cache-Memory, with a pair of intermediate main-buses this IQ arrangement comprising: a pair of split IQ ASIC Arrays disposed between each Cache-Memory and the main-buses and being adapted to assure identical data in all identical memory addresses in different caches, and to "remember" write-operations along the buses and to execute invalidation sequences for any Cache-Memory unit as dictated by that Cache-Memory unit.

A multiprocessor computer architecture containing processor caches that are kept coherent, and in particular, a duplicate cache tag subsystem and method for maintaining duplicate cache tags, are disclosed. The tag width of duplicate cache tags for a processor cache is tailored to available integrated circuit surface area, or to device pin count, without significantly sacrificing system performance. Such partial duplicate tag width may also be reduced at any time during the integrated circuit design phase, should the available integrated circuit surface area or pin-availability decrease. The method disclosed involves requesting data from memory; reading a partial duplicate cache tag list to determine if there is a partial hit; taking the data from the memory if there is no match between a requested address and the partial duplicate cache tag list; holding the data in memory or a requestor module if there is a match between the requested address and the partial duplicate cache tag list; and interrupting processor operation to confirm that the partial duplicate cache tag corresponds to an actual cache tag. The data are taken from the cache if the partial duplicate cache tag matches the actual cache tag and cache status indicates that the data have been modified. The data are taken from memory if the partial duplicate cache tag does not match the actual cache tag or cache status indicates that the data have not been modified.

A cache tag memory device having a memory array comprising a first single-port memory array, a second single-port memory array, and a dual-port memory array. A first port, accessed by a local processor, may read from and write to its corresponding single-port memory array and the dual-port memory array. A second port, accessed through a global system bus, may also read from and write to its corresponding second single-port memory array and the dual-port memory array. Both ports operate asynchronously relative to each other. Status bits indicating the status of the entries in the first and second single-port memory arrays are stored in the dual-port memory array and may be altered by the global system while the local processor is performing its operations.

A duplicate cache tag store, accessible to a graphics processor and to devices connected to the I/O bus without creating traffic on the system bus. Any entry into, or displacement from, the CPU cache tag store is also entered into, or displaced from, the second cache tag store. The disclosure further describes a computer graphics system, having a graphics processor capable of reading from or writing to main memory, including virtual memory, without any action by the CPU; having a FIFO command buffer in main memory for temporary storage of graphics commands; having a residue buffer for the temporary storage of memory transmissions not immediately usable by the graphics processor; having a "short circuit" feature for routing graphics commands to the command processor in the minimum number of steps; having a cursor control system capable of storing cursor pattern information in, and retrieving cursor pattern information from, main memory; having a cursor bus that is reconfigurable to carry information other than cursor information; and having a frame buffer module that contains no timing or cursor control circuitry.