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What is claimed is:
1. A semiconductor memory device containing a cache memory, comprising, on
a single chip:
a first memory cell array comprising a plurality of word lines, a plurality
of bit line pairs perpendicular to said plurality of word lines and a
plurality of memory cells arranged in a matrix of a plurality of rows
corresponding to said word lines and columns corresponding to said bit
line pairs, said first memory cell array being divided into a plurality of
blocks each comprising a plurality of columns,
a cache memory including a second memory cell array comprising a plurality
of static type memory cells arranged in a plurality of rows and a
plurality of columns corresponding to said plurality of columns in said
first memory cell array, said second memory cell array being divided into
a plurality of blocks each comprising a plurality of columns, each said
static type memory cell being aligned with and connected to one of said
plurality of bit line pairs,
first access means responsive to a cache miss indicating signal for
accessing data at a memory cell of said first memory cell array selected
by a first row address signal and a column address signal, said first
access means comprising block selecting means responsive to a block
selecting signal for selecting any of said plurality of blocks in said
first memory cell array,
second access means responsive to a cache hit indicating signal for
accessing data at a static type memory cell selected by a second row
address signal and a column address signal, and
data transfer means for transferring data between a column in said first
memory cell array and a respective column in said second memory cell
array.
2. The semiconductor memory device according to claim 1, which further
comprises:
switching means responsive to said cache miss indicating signal for
activating said data transfer means.
3. The semiconductor memory device according to claim 1, wherein
said block selecting signal comprises a part of a column address signal.
4. The semiconductor memory device according to claim 1, wherein
said first access means comprises
first row selecting means responsive to said first row address signal for
selecting any of said plurality of rows in said first memory cell array,
and
column selecting means responsive to said column address signal for
selecting any of said plurality of columns in said first memory cell
array, and
said second access means comprises
second row selecting means responsive to said second row address signal for
selecting any of plurality of rows in said second cache memory cell array.
5. The semiconductor memory device according to claim 4, which further
comprises:
data input/output means for inputting/outputting data to/from a memory cell
selected by said first row selecting means and said column selecting means
or a static type memory cell selected by said second row selecting means
and said column selecting means.
6. The semiconductor memory device according to claim 4, which further
comprises:
a plurality of sense amplifiers for detecting and holding data on the row
selected by said first row selecting means.
7. The semiconductor memory device according to claim 4, wherein
said second row selecting means further comprises means for inactivating
all the static type memory cells included in said second cache memory cell
array.
8. The semiconductor memory device according to claim 1, wherein
each of said plurality of memory cells included in said first memory cell
array comprises a dynamic type memory cell.
9. A semiconductor memory device containing a cache memory as recited in
claim 1, wherein said first access means is responsive to a row activating
signal, said row activating signal being in an activated state during
occurrence of said cache hit indicating signal.
10. The semiconductor device according to claim 1, wherein each of said
blocks have a predetermined equal number of bit line pairs and each of
said blocks of said cache memory include said predetermined equal number
of columns.
11. The semiconductor device according to claim 10, wherein said first and
second memory cell arrays are divided into equal numbers of blocks.
12. A semiconductor memory device containing a cache memory, comprising, on
a single chip:
a dynamic random access memory comprising a plurality of word lines, a
plurality of bit line pairs arranged so as to intersect with said
plurality of word lines and a plurality of memory cells at intersections
of said plurality of word lines and said plurality of bit line pairs, and
a cache memory comprising a plurality of stages of storage means groups,
each storage means group having a plurality of storage means, each storage
means being physically aligned with and connected to one of said plurality
of bit line pairs.
13. A semiconductor memory device containing a cache memory, comprising, on
a single chip:
a dynamic random access memory comprising a plurality of word lines, a
plurality of bit line pairs arranged so as to intersect with said
plurality of word lines and a plurality of memory cells at intersection of
said plurality of word lines and said plurality of bit line pairs,
a cache memory comprising a plurality of storage means arranged in rows and
columns, each of said cache memory storage means being physically aligned
with a respective bit line pair, and
a plurality of transfer gates, one transfer gate for each column of said
storage means of cache memory and connectable to one of said bit line
pairs of dynamic random access memory.
14. A semiconductor memory device containing a cache memory, comprising, on
a single chip:
a first memory cell array comprising a plurality of word lines, a plurality
of bit line pairs perpendicular to said plurality of word lines and a
plurality of memory cells arranged in a matrix of a plurality of rows
corresponding to said word lines and columns corresponding to said bit
line pairs, said first memory cell array being divided into a plurality of
blocks each comprising a plurality of columns,
a cache memory including a second memory cell array comprising a plurality
of blocks, each block having a plurality of static type memory cells
arranged in one or more rows and a plurality of columns corresponding to
said plurality of columns included in each of said blocks of said first
memory cell array, each said static type memory cells being aligned with
one of said bit line pairs,
first access means responsive to a cache miss indicating signal for
accessing data at a memory cell of said first memory cell array selected
by a first row address signal and a column address signal, said first
access means comprising block selecting means responsive to a block
selecting signal for selecting any of said plurality of blocks in said
first memory cell array,
second access means responsive to a cache hit indicating signal for
accessing data at a static type memory cell selected by a second row
address signal and a column address signal, and
data transfer means for transferring data from memory cells in a row of
block of said first memory cell array selected by said block selecting
means to memory cells in a row of a selected block of said second memory
cell array.
15. The semiconductor memory device according to claim 14, wherein each
memory cell of said first memory cell array is a dynamic type memory cell.
16. The semiconductor memory device according to claim 14, wherein said
static type memory cells of said blocks of said second memory cell array
are arranged in at least two rows.
17. A semiconductor memory device containing a cache memory, comprising, on
a single chip:
a dynamic random access memory comprising a plurality of bit lines, a
plurality of first blocks each having a plurality of dynamic type memory
cells arranged in a matrix of a plurality of rows and a plurality of
columns corresponding to said bit lines, a number of columns in each first
block being equal,
a cache memory comprising a plurality of second blocks each having a
plurality of static type memory cells arranged in one or more rows and a
plurality of columns, a number of columns in each of said second blocks
being equal to the number of columns in said first blocks, each of said
static type memory cells being aligned with one of said bit lines, and
data transfer means for transferring data from dynamic type memory cells in
a row of one of said first blocks of said dynamic random access memory to
static type memory cells in a row of one of said second blocks of said
cache memory.
18. The semiconductor memory device according to claim 17, wherein said
static type memory cells of said second blocks are arranged in at least
two rows.
19. A semiconductor memory device containing a cache memory, comprising, on
a single chip:
a first memory cell array comprising a plurality of word lines, a plurality
of bit line pairs of perpendicular to said plurality of word lines and a
plurality of memory cells arranged in a matrix of a plurality of rows
corresponding to said word lines and columns corresponding to said bit
line pairs
a cache memory including a second memory cell array comprising a plurality
of static type memory cells arranged in a plurality of rows and a
plurality of columns corresponding to said plurality of columns in said
first memory cell array each said static type memory cell being aligned
with and connected to one of said plurality of bit line pairs,
first access means responsive to a cache miss indicating signal for
accessing data at a memory cell of said first memory cell array selected
by a first row address signal and a column address signal,
second access means responsive to a cache hit indicating signal for
accessing data at a static type memory cell selected by a second row
address signal and a column address signal, and
data transfer means for transferring data between a column in said first
memory cell array and a respective column in said second memory cell
array. |
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Claims |
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Description |
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Related, copending application of particular interest to the instant
application is U.S. Ser. No. 07/266,060 entitled "Cache Contained Type
Semiconductor Memory Device and Operating Method Therefor" filed Nov. 2,
1988 and assigned to the same assignee of the instant application. The
application issued as U.S. Pat. No. 5,111,386.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices for
a simple cache system, and more particularly, to semiconductor memory
devices having a cache memory integrated on a chip on which the
semiconductor memory device is formed.
2. Description of the Prior Art
Conventionally, in order to improve cost performance of a computer system,
a small capacity and high-speed memory has been frequently provided as a
high-speed buffer between a main memory structured by a low-speed but
large capacity and low-cost dynamic random access memory (DRAM) and a
central processing unit (CPU). The high-speed buffer is referred to as a
cache memory. A block of data which the CPU may request is copied from the
main memory and stored in the high-speed buffer. The state in which data
stored in an address, in the DRAM, which the CPU attempts to access exist
in the cache memory is referred to as "hit". In this case, the CPU makes
access to the high-speed cache memory, and acquires the requested data
from the cache memory. On the other hand, the state in which data stored
in an address which the CPU attempts to access does not exist in the cache
memory is referred to as "cache miss". In this case, the CPU makes access
to the low-speed main memory, acquires the requested data from the main
memory and at the same time, transfers to the cache memory a data block to
which the data belongs.
However, such a cache memory system could not be employed in a small-sized
computer system attaching important to the cost because it requires a
high-cost and a high-speed memory. Conventionally, a simple cache system
has been configured utilizing a high-speed access function of a
general-purpose DRAM, such as a page mode and a static column mode.
FIG. 1 is a block diagram showing a basic structure of a conventional DRAM
device having a function of a page mode or a static column mode.
In FIG. 1, a memory cell array 1 has a plurality of word lines and a
plurality of bit line pairs arranged intersecting with each other, memory
cells being provided at intersections thereof, respectively. In FIG. 1,
there are typically shown only a single word line WL, a single bit line
pair BL and BL and a single memory cell MC provided at an intersection of
the word line WL and the bit line BL. The word lines in the memory cell
array 1 are connected to a row decoder portion 3 through a word driver 2.
In addition, the bit line pairs in the memory cell array 1 are connected
to a column decoder portion 6 through a sense amplifier portion 4 and an
I/O switching portion 5. A row address buffer 7 is connected to the row
decoder portion 3, and a column address buffer 8 is connected to the
column decoder portion 6. A multiplex address signal MPXA obtained by
multiplexing a row address signal RA and a column address signal CA is
applied to the row address buffer 7 and the column address buffer 8. An
output buffer 9 and an input buffer 10 are connected to the I/O switching
portion 5.
FIGS. 2A, 2B and 2C are waveform diagrams showing operations in an ordinary
read cycle, a page mode cycle and a static column mode cycle of the DRAM,
respectively.
In the ordinary read cycle shown in FIG. 2A, the row address buffer 7 first
acquires the multiplex address signal MPXA at the falling edge of a row
address strobe signal RAS and applies the same to the row decoder portion
3 as a row address signal RA. The row decoder portion 3 is responsive to
the row address signal RA for selecting one of the plurality of word
lines. The selected word line is activated by the word driver 2.
Consequently, information stored in the plurality of memory cells
connected to the selected word lines are read out onto the corresponding
bit lines, respectively. The information are detected and amplified by the
sense amplifier portion 4. At this time point, information stored in the
memory cells corresponding to one row are latched in the sense amplifier
portion 4. Then, the column address buffer 8 acquires the multiplex
address signal MPXA at the falling edge of a column address strobe signal
CAS and applies the same to the column decoder portion 6 as a column
address signal CA. The column decoder portion 6 is responsive to the
column address signal CA for selecting one of information corresponding to
one row latched in the sense amplifier portion 4. This selected
information is extracted to the exterior through the I/O switching portion
5 and the output buffer 9 as output data D.sub.OUT. An access time (RAS
access time) t.sub.RAC in this case is the time period elapsed from the
falling edge of the row address strobe signal RAS until the output data
D.sub.OUT becomes valid. In addition, a cycle time t.sub.c in this case is
the sum of the time period during which the device is in an active state
and an RAS precharge time t.sub.RP. As a standard value, t.sub.c is
approximately 200 ns when t.sub.RAC is 100 ns.
In the page mode cycle and the static column mode cycle shown in FIGS. 2B
and 2C, memory cells on the same row address are accessed by changing the
column address signal CA. In the page mode cycle, the column address
signal CA is latched at the falling edge of the column address strobe
signal CAS. Thus, the access time is a time period t.sub.CAC (CAS access
time) elapsed from the falling edge of the column address strobe signal
CAS until the output data D.sub.OUT becomes valid, which becomes a time
period of approximately one-half of the access time t.sub.RAC in the
ordinary cycle, i.e., approximately 50 ns, where t.sub.CP denotes a
precharge time of the column address strobe signal CAS, and t.sub.PC
denotes a cycle time.
In the static column mode, access is made in response to only the change in
the column address signal CA, as in a static RAM (SRAM). Thus, the access
time is a time period t.sub.AA (address access time) from the time when
the column address signal CA is changed to the time when the output data
D.sub.OUT becomes valid, which becomes approximately one-half of the
access time t.sub.RAC in the ordinary cycle similarly to t.sub.CAC, i.e.,
generally about 50 ns.
More specifically, in the page mode cycle, when the falling edge of the
column address strobe signal CAS is inputted to the column address buffer
8, the column address signal CA is sent to the column decoder. Therefore,
any of the data corresponding to one row latched in the sense amplifier
portion 4 is made valid, so that the output data D.sub.OUT is obtained
through the output buffer 9. Also in the static column mode cycle, the
same operation as that in the page mode cycle is performed except a
reading operation is initiated in response to the change in address
signal.
FIG. 3 is a block diagram showing a structure of a simple cache system
utilizing the page mode or the static column mode of the DRAM device shown
in FIG. 1. In addition, FIG. 4 is a waveform diagram showing an operation
of the simple cache system shown in FIG. 3.
In FIG. 3, a main memory 20 comprises 1M byte which comprises 8 DRAM
devices 21 each having 1M.times.1 organization. In this case, the row
address signal RA and the column address signal CA having a total of 20
bits (2.sup.20 =1048576=1M) are required. An address multiplexer 22, which
applies 10-bit row address signal RA and the 10-bit column address signal
CA to the main memory 20 two times, has 20 address lines A.sub.0 to
A.sub.19 receiving a 20-bit address signal and 10 address lines A.sub.0 to
A.sub.9 applying a 10-bit address signal as multiplexed (multiplex address
signal MPXA) to the DRAM devices 21.
It is assumed here that data corresponding to one row selected by a row
address RAL has been already latched in the sense amplifier portion 4 in
each of the DRAM devices 21. An address generator 23 generates a 20-bit
address signal corresponding to data which the CPU requests. The latch
TAG) 25 holds the row address RAL corresponding to data selected in the
preceding cycle. A comparator 26 compares the 10-bit row address RA out of
the 20-bit address signal with the row address RAL held in the TAG 25.
When both coincide with each other, which means that the same row as that
accessed in the preceding cycle is accessed ("hit"), the comparator 26
generates an "H" level cache hit signal CH. A state machine 27 is
responsive to the cache hit signal CH for performing page mode control in
which a column address strobe signal CAS is toggled (raised and then,
lowered) with a row address strobe signal RAS being kept at a low level.
In response thereto, the address multiplexer 22 applies the column address
signal CA to the DRAM devices 21 (see FIG. 4). Thus, data corresponding to
the column address signal CA is extracted from a group of data latched in
the sense amplifier portion in each of the DRAM devices 21. In the case of
such "hit", output data is obtained from the DRAM devices 21 at high speed
in an access time t.sub.CAC.
On the other hand, when the row address signal RA generated from the
address generator 23 and the row address RAL held in the TAG 25 do not
coincide with each other, which means that a different row from the row
accessed in the preceding cycle is accessed ("cache miss"), the comparator
26 does not generate the "H" level cache hit signal CH. In this case, the
state machine 27 performs ordinary RAS and CAS control in the ordinary
read cycle, and the address multiplexer 22 sequentially applies the row
address signal RA and the column address signal CA to the DRAM devices 21
(see FIG. 4). In the case of such "cache miss", the ordinary read cycle
beginning with precharging of the row address strobe signal RAS occurs, so
that output data is obtained at low speed in the access time t.sub.RAC.
Therefore, the state machine 27 generates a wait signal Wait, to bring a
CPU 24 into a Wait state. In the case of "cache miss", a new row address
signal RA is held in the TAG 25.
As described in the foregoing, in the simple cache system shown in FIG. 3,
data corresponding to one row of the memory cell array in each of the DRAM
devices (1024 bits in the case of a 1M bit device) is latched in a sense
amplifier portion as one block. Therefore, the block size is unnecessarily
large and the blocks (entries) held in the TAG 25 are insufficient in
number. For example, in the system shown in FIG. 3, the number of entries
becomes 1. Thus, only when access is continuously made to the same row
address, cache hit occurs. Consequently, for example, when a program
routine bridged over continuous two row addresses is repeatedly
implemented, cache miss necessarily occurs, so that a cache hit rate is
low.
Meanwhile, as another conventionally example, a simple cache system has
been proposed, which is disclosed in U.S. Pat. No. 4,577,293. In this
simple cache system, a register holding data corresponding to one row is
provided outside a memory cell array. In the case of "hit", the data is
directly extracted from this register, so that accessing is speeded up.
However, in the simple cache system disclosed in the U.S. Patent, the
external register holds data corresponding to one row in the memory cell
array, so that the block size is unnecessarily large and the cache hit
rate is low as in the conventional example shown in FIG. 1 and 3.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a semiconductor memory
device which can configure a high-speed simple cache system having a high
cache hit rate.
Another object of the present invention is to provide a semiconductor
memory device which can configure a simple cache system having an
increased number of entries.
Still another object of the present invention is to provide a semiconductor
memory device containing a cache memory in which an access time at the
time of cache hit can be shortened.
Still another object of the present invention is to provide a semiconductor
memory device containing a cache memory in which the number of entries of
data can be increased without unnecessarily increasing the data block
size.
A further object of the present invention is to provide an operating method
for a semiconductor memory device which can configure a high-speed simple
cache system having a high cache hit rate.
A still further object of the present invention is to provide an operating
method for a semiconductor memory device containing a cache memory in
which an access time at the time of cache hit can be shorten.
The semiconductor memory device according to the present invention is a
semiconductor memory device containing a cache memory employed in a simple
cache system including a generator for generating a cache hit/miss
indicating signal, which comprises a first memory cell array, a second
memory cell array, first access means, second access means, and data
transfer means.
The first memory cell array comprises a plurality of memory cells arranged
in a plurality of rows and columns. The second memory cell array comprises
a plurality of static type memory cells arranged in a plurality of rows
and a plurality of columns corresponding to the plurality of columns in
the first memory cell array. The first access means is responsive to a
cache miss indicating signal for accessing data to a memory cell selected
by a first row address signal externally applied and a column address
signal externally applied in the first memory cell array. The second
access means is responsive to a cache hit indicating signal for accessing
data to a static type memory cell selected by a second row address signal
externally applied and the column address signal externally applied in the
second memory cell array. The data transfer means transfers data between a
row selected by the first row address signal externally applied in the
first memory cell array and a row selected by the second row address
signal externally applied in the second memory cell array.
In the semiconductor memory device according to the present invention,
since the second memory cell array comprises a plurality of static type
memory cells in a plurality of rows, data blocks on different rows in the
first memory cell array can be held in the second memory cell array. Thus,
the semiconductor memory device can configure a simple cache system in
which the number of entries is increased so that a cache hit rate is
improved.
In accordance with another aspect of the present invention, a semiconductor
memory device for a simple cache system having a cache memory integrated
on a chip on which the semiconductor memory device is formed comprises a
first memory cell array, a second memory cell array, first access means,
second access means, block selecting means, region selecting means, data
transfer means and data selecting means.
The first memory cell array comprises a plurality of memory cells arranged
in a plurality of rows and columns. The first memory cell array is divided
into a plurality of blocks each comprising a plurality of columns. The
second memory cell array comprises a plurality of static type memory cells
arranged in a plurality of rows and columns. The second memory cell array
is divided into a plurality of regions each comprising the same number of
a plurality of rows as the plurality of columns included in each of the
plurality of blocks in the first memory cell array. The first access means
accesses data to a memory cell selected by a first row address signal
externally applied and a column address signal externally applied in the
first memory cell array. The second access means accesses data to a static
type memory cell selected by a cache address signal externally applied in
the plurality of regions in the second memory cell array.
The block selecting means is responsive to a block selecting signal
externally applied for selecting any of the plurality of blocks in the
first memory cell array. The region selecting means is responsive to a
region selecting signal externally applied for selecting any of the
plurality of regions in the second memory cell array. The data transfer
means transfers data between the a block, in the first memory cell array,
selected by the block selecting means and the region, in the second memory
cell array, selected by the region selecting means. Data selecting means
is responsive to the region selecting signal for selecting any of data
to/from the plurality of static type memory cells accessed by the second
access means in the plurality of regions.
In this semiconductor memory device containing a cache memory, data blocks
on the plurality of rows in the first memory cell array can be held on the
second memory cell array. In addition, a plurality of data blocks
respectively on a plurality of different rows in the same block in the
first memory cell array can be simultaneously held in different regions in
the second memory cell array. Furthermore, the data blocks respectively on
the plurality of different rows in the same block in the first memory cell
array can be arranged on one row in the second memory cell array.
Thus, if the second memory cell array is utilized as a cache memory, the
number of entries of data can be efficiently increased, so that the cache
hit rate can be improved. Additionally, access can be made to the second
memory cell array before determination of cache hit/cache miss. In this
case, data are extracted from the plurality of regions in the second
memory cell array. Thereafter, when it is determined that cache hit
occurs, any of the data extracted from the plurality of regions is
selected. When it is determined that cache miss occurs, the data extracted
from the second memory cell array is ignored. Thus, an access time at the
time of cache hit can be shorten. As a result, semiconductor memory device
can configure a high-speed simple set associative cache system having a
high cache hit rate.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing a structure of a conventional DRAM
device;
FIG. 2A is a waveform diagram showing an operation in an ordinary read
cycle of the conventional DRAM device;
FIG. 2B is a waveform diagram showing an operation in a page mode cycle of
the conventional DRAM device;
FIG. 2C is a waveform diagram showing an operation in a static column mode
cycle of the conventional DRAM device;
FIG. 3 is a block diagram showing a structure of a simple cache system
utilizing the DRAM device shown in FIG. 1;
FIG. 4 is a waveform diagram showing an operation of a simple cache system
shown in FIG. 3;
FIG. 5 is a block diagram showing a structure of a DRAM device containing a
cache memory according to one embodiment of the present invention;
FIG. 6 is a block diagram showing specifically a structure of a part of the
DRAM device shown in FIG. 5;
FIG. 7 is a block diagram showing a structure of a simple cache system
utilizing the DRAM device shown in FIG. 5;
FIG. 8 is a waveform diagram showing an operation of the simple cache
system shown in FIG. 7;
FIG. 9 is a block diagram showing a structure of a semiconductor memory
device according to another embodiment of the present invention;
FIG. 10 is a block diagram showing specifically a structure of a part of
the semiconductor memory device shown in FIG. 9;
FIG. 11 is a block diagram showing a structure of a simple set associative
cache system utilizing the semiconductor memory device shown in FIG. 9;
and
FIG. 12 is a waveform diagram showing an operation of the simple cache
system shown in FIG. 11.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to the drawings, embodiments of the present invention will be
described in detail.
FIG. 5 is a block diagram showing a structure of a DRAM device containing a
cache memory according to one embodiment of the present invention.
This DRAM device is the same as the conventional DRAM device shown in FIG.
1 except for the following. More specifically, a DRAM memory cell array 1
is divided into a plurality of blocks each comprising DRAM memory cells
(dynamic type memory cells) in a plurality of rows on the address space.
In FIG. 5, the DRAM memory cell array 1 is divided into four blocks B1 to
B4. In addition, a transfer gate portion 11 and a static random access
memory type memory cell array (referred to as SRAM memory cell array
hereinafter) are provided between a sense amplifier portion 4 and an I/O
switching portion 5. Furthermore, block decoders 13a to d and a way
decoder 14 are provided. The SRAM memory cell array 12 is divided into
four blocks a to d corresponding to the four blocks B1 to B4 in the DRAM
memory cell array 1. Activation of each of the block decoders 13a to 13d
is controlled by an AND gate G.sub.1 to which more significant two bits of
a column address signal CA from a column address buffer 8 and an inverted
signal of a cache hit signal CH are inputted. More specifically, when the
cache hit signal CH is at an "L" level, a block decoder corresponding to a
block selected by more significant two bits of the column address signal
CA is activated. On the other hand, when the cache hit signal CH is at an
"H" level, no block decoder is activated. In addition, a way address
signal WA is applied to the way decoder 14 through a way address buffer
15. The way decoder 14 is responsive to the way address signal WA for
selecting and driving word lines in the SRAM memory cell array 12. Circuit
blocks shown in FIG. 5 are all formed on the same semiconductor chip.
FIG. 6 is a diagram showing specifically a structure of a part of the DRAM
device shown in FIG. 5.
In FIG. 6, a sense amplifier portion 4, a transfer gate portion 11, an I/O
switching portion 5 and a column decoder portion 6 comprise a plurality of
sense amplifiers 40, a plurality of transfer gates 110, a plurality of I/O
switches 50 and a plurality of column decoders 60, respectively,
corresponding to a plurality of bit line pairs BL and BL in the DRAM
memory cell array 1. Each of the sense amplifiers 40 is connected between
each of the bit line pairs BL and BL. Each of the transfer gates 60
comprises N channel MOSFETs Q1 and Q2. Each of the I/O switches 50
comprises N channel MOSFETs Q3 and Q4. In the SRAM memory cell array 12, a
plurality of bit line pairs SBL and SBL are arranged corresponding to the
plurality of bit line pairs BL and BL in the DRAM memory cell array 1.
Four word lines W1 to W4, for example, are arranged intersecting with the
plurality of bit line pairs SBL and SBL, static type memory cells
(referred to as SRAM memory cells hereinafter) 120 being provided at
intersections thereof.
Each of the bit line pairs BL and BL is connected to the corresponding bit
line pair SBL and SBL in the SRAM memory cell array 12 through the MOSFETs
Q1 and Q2 in the corresponding transfer gate 110. The bit line pairs SBL
and SBL in the SRAM memory cell array 12 is connected to I/O buses I/O and
I/O through the MOSFETs Q3 and Q4 in the corresponding I/O switch 50,
respectively.
Additionally, block decoders 13a to 13d are arranged corresponding to the
blocks B1 to B4 in the DRAM memory cell array 1. The block decoders 13a to
13d apply common transfer signals to gates of the MOSFETs and Q2 in the
transfer gate 110 belonging to the corresponding blocks, respectively. In
addition, each of the column decoders 60 applies a column selecting signal
to gates of MOSFETs Q3 and Q4 in the corresponding I/O switch 50.
In this DRAM device, when any of the block decoders 13a to 13d applies a
transfer signal to the transfer gates 110 belonging to the corresponding
block in response to the cache hit signal CH, data on one row in the
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