A system and method for controlling access to data in storage which is shared by a plurality of processors are disclosed. The shared storage is located outside of main storage of each of the processors and stores a lock file. The lock file comprises a plurality of control fields containing access administration information (ZVI) authorizing the processors to access the data when not currently being accessed by another processor and a status identification code (SKC) to indicate the status of the access administration information. In response to a data access request from one of the processors, the status identification code provided by the processor is compared to the stored status identification code. If the comparison indicates that the requesting processor is authorized to update the access administration information, the access administration information associated with the requesting processor for the type of data access request is written from the requesting processor to the shared storage without first reading the stored access administration information from the lock file. The status identification code in the storage is updated to indicate that the processor has updated the access administration information.

In order to reduce load at a resource managing node for exclusive control of a shared resource, each node has a group of lock state registers each corresponding to one of the nodes. Before one node issues a lock request to a resource managing node, the node checks the register group to see if the resource managing node is unlocked. With the target node found to be accessible, the access requesting node sends to a broadcast message exchange circuit a broadcast request message including a lock request regarding the resource managing node. The broadcast message exchange circuit receives such broadcast request messages from access requesting nodes, and changes them serially into broadcast messages for broadcast to all nodes. Of these broadcast messages, the first message received by each node is processed by its lock control circuit so that the lock request in that message is allowed to lock the resource managing node. The lock control circuit writes the number of the access requesting node into the register corresponding to the resource managing node. The access requesting node checks the register contents to see if the lock request it issued has been successfully accepted.

A directory system directs cache line access requests from processors in a multi-processor system with a shared memory system through a cache line states directory. The cache line states directory stores a state value that identifies a cache line shared states word. The cache line shared states word identifies the processor that owns the cache line and the state of access of each processor that shares access to the cache line. A state value encoder encodes a cache line shared state word into a state value and loads the state value into the cache line states directory. A state value decoder decodes the state value into a cache line shared state word for use by the cache line directory system in retrieving the cache line. A plurality of cache line tables are used with each cache line assigned to one of the tables. The cache line table stores a state value for each cache line shared states word stored in the table. The encoder and decoder perform a table look-up to convert between a cache line shared state word and a state value. Each of said cache line tables stores an ordered list of cache line shared state words and their corresponding state values. The ordered list is a list of cache line shared state words that have the most significance to the multi-processor system.

A computer system including a plurality of processing nodes, at least one resource provided for use by any of the processing nodes and a plurality of register sets. Each register set is provided in each of the processing nodes for storing in parallel use status information indicating whether the resource is in exclusive use status or not. The computer system can also include a plurality of request issue circuits, each being provided in each of the processing nodes, for issuing individually requests for exclusive use of the resource, a message exchanging circuit for serializing requests issued by the request issue circuits into a serialized order and broadcasting the request to all of the processing nodes in the serialized order and a plurality of status control circuits. Each status control circuit is provided in each of the processing nodes corresponding to each of the register sets to update individually a corresponding register set depending on use status information stored in the corresponding register set and each of the requests for exclusive use of the resource received at a corresponding node.

A data processor is adapted, in particular with respect to the microcode, in such a way that the execution of standard commands of the processor which are loaded in a user memory area and request reading or writing access to the content of memory cells is inhibited. In the operating system memory area there is a memory area access table, in which there is stored the address area authorized per user memory area for the commands there. Finally, there is an additional program routine which is called up by a command loaded in a user memory area and requesting reading or writing access to a memory cell, and checks by means of the memory area access table (before execution) whether the requested access to a memory cell lies in the authorized address area. If it does not lie in the authorized address area, the additional program routine inhibits the execution of the command. The invention has the advantage that the "radius of action" of one or more application programs in the user program memory area can be restricted in a simple way.