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Description  |
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BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus for inventory control, in
general, and, more particularly, to a system for the maintenance,
management and control of inventory. The invention allows inventory
control by manufacturers, distributors, users and/or dealers for the
purposes of optimized distribution; close control of and efficient
collection for sold units; and generation of current sales data in order
to project future sales strategy, marketing analysis, production planning,
shipping and distribution planning.
2. Prior Art
Presently, the best-known automated inventory control systems are generally
based on a coded pattern consisting of vertical bars known as a bar code
pattern. This pattern is imprinted somewhere on the controlled item or its
container. This system is used primarily with mass produced, low cost,
consumable products. Each bar code pattern identifies a unique item.
Point-of-sale control is implemented with laser beam scanners which
interface with a computer system to interpret the code pattern. Pricing
and internal inventory maintenance can be established at the discretion of
the individual user, controlled by the applicable software. Inventory
control may be maintained with portable equipment consisting of a bar
pattern scanner and a suitable storage device which can interface with the
computer system. This results in a system which has a response time which
can be significantly poorer than desired and errors by the human operator
limit data integrity.
Often these known systems are used to monitor or control massive numbers of
relatively inexpensive, consumable products with a single code to identify
each item. The most familiar example to most persons is the supermarket
checkout scanner and the UPC product codes. Characteristics of that
application are rapid inventory turnover and sales of random combinations
of such items in moderate quantities (e.g. 20-50) at frequent intervals.
Sales and/or transactions take place at a checkstand attended by a cashier
with immediate billing by distributors with short term payment by
retailers and individual examination of each item with direct
line-of-sight between the bar code pattern and the scanning device.
Most other existing inventory control methods involve direct (or actual)
count of individual items. The resulting data may be further processed by
computer. If computer processing is desired, the hand-counted information
must be manually input into the computer. In retailing of durable goods,
this category includes products sold in large numbers (10-20 million
annually) with an immense economical impact to the inventory owner.
Currently, this market incurs a large expense to control inventory and
protect investments.
These types of products are relatively high cost, major purchase items
(with individual serial numbers) that have extended floor time at the
dealer's location and usually require financing of the dealer's inventory.
Each unit must be identified and tracked from manufacturer to distributer
and into the dealer network until the time of sale. The procedure of
inspection and identification by serial number is a labor-intensive,
hands-on technique that is expensive for several reasons. In addition to
the expense incurred in collection, the data is often flawed resulting in
a faulty database for decision making. For example, warehouse control is
imperfect. Thus, the distributor may have units which are not exposed for
sale at the optimum time, resulting in a situation where many units remain
unsold at the end of the model year. This frequently results in a
requirement to shift models to other warehouse locations. Expenses are
incurred for shipping, accounting, distribution and warehouse in/out
charges. Unsold units in warehouses can accumulate storage fees and create
a backlog of non-current models. In reasonable economic circumstances,
these units must be discounted to encourage sales at the cost of lost
profits. In difficult economic times, disposal of an excessive supply of
non-current models is more difficult. In addition, serious problems in the
introduction of new models to maintain competitive positions are created.
Moreover, correction of errors is often necessary and creates handling and
accounting expenses.
Control at dealer's locations is even more difficult. Floor check fees
based on unit count make it difficult to count the inventory more than
once a month. When the inventory is financed, a substantial amount of the
money is tied up with attendant "cost-of-money expense" and collection
activities depending on the inventory data. Thus, the system with
infrequent checking suffers from errors and associated costs, but more
frequent checking inserts errors made in the course of an inventory more
frequently and imposes other expenses; it is thus not a solution.
The system has a number of significant error sources. Serial numbers may be
misread, misunderstood, or transposed initially or in a subsequent
tabulation. Similarly, units may be missed or missing during the counting
process. Correction of these errors requires manpower expense by the
dealer, checker and/or distributor. Furthermore, all of the data (good or
bad) collected by the checkers must be processed for inputting into a
computer system. The human factor inherently includes some errors and,
thus, more expense to resolve them.
Units not truly part of the inventory may be included in the count. For
example, units in for service; units owned by the dealer; units mistakenly
paid for while unsold; or units missed in one check and counted
subsequently. To check the checker is an additional expense.
Accounting data from the inventory count can be, of course, related to
sales data. In many industries using this type of control system, there is
considerable delay in receiving and assimilating the sales statistics.
There are several ways to acquire this information: direct polling of
dealers; tabulation of warranty registrations; and summary reports by
commercial marketing statistics companies. The latter are typically one to
two months out of date. Dealers are usually heavily involved with daily
operations and not enthusiastic about gathering accurate sales figures.
Dealers and customers are lax about completing and submitting warranty
registrations. Distributors may update warranty reports only monthly. All
of these information sources are off line, time consuming, expensive and
inaccurate.
Lack of timely sales data can be costly. With outdated data, plus ensuing
time to discover the problem and to plan and implement corrective action,
plus delays receiving feedback data related to the results of the action
taken, a sales campaign may totally founder. Likewise, shifting of various
models to other locations may result in great expense with little return.
Advertising effectiveness is diminished when dated information is used to
control and monitor the resulting sales statistics.
In some industries there is little effective correlation between sales,
production, shipping, warehousing and the like, based on up-to-date data.
Hence, the problems of left-over models, stock in the wrong warehouse and
the like are, to a great extent, built into the system. The economic
consequences have been discussed previously.
It is clearly desirable to provide an inventory control and maintenance
system which eliminates or reduces these problems in a cost effective
fashion.
SUMMARY OF THE INSTANT INVENTION
The invention described herein comprises a system which utilizes
microelectronic circuitry in combination with computer devices which can
be integrated and operated together to provide a degree of automation
heretofore unavailable in the control of inventory. The system includes a
small, radio frequency transponder which is attached to the unit of
inventory to be tracked. Contained in solid state memory within the
transponder is the item serial number, the transponder serial number, or
other suitable unique identification code. The device also contains the
logic circuitry to process data received on its radio frequency data link
including such identification codes. When a received code is matched to
the internally contained code by the device logic (and any other protocol
requirements are met), the transponder emits a short verification signal
to the system interrogation transceivers. A data link can be established
through commercial telephone line systems, allowing data received by the
interrogation transceiver to be transmitted to a remote computer. The
computer can be in a location within the storage complex or thousands of
miles away. If necessary, the data can be transmitted to a computer
anywhere in the world. Coding and decoding of the computer signals may be
accomplished through the use of a modem. A plurality of transceivers, if
required, can be employed to provide full coverage of diverse physical
facilities for inventory.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of the transponder system of the instant
invention.
FIG. 2 is a schematic diagram of the transponder energy manager portion of
the instant invention.
FIG. 3 is a schematic diagram of the transponder processor portion of the
instant invention.
FIGS. 4A and 4B are schematic diagrams of the transponder transmitter and
receiver portions of the instant invention.
FIG. 5 is a schematic diagram of the transceiver diode switch portion of
the instant invention.
FIG. 6 is a schematic diagram of the voltage regulator portion of the
instant invention.
FIG. 7 is a block diagram of a preferred embodiment of the interrogation
transceiver of the instant invention.
DESCRIPTION OF A PREFERRED EMBODIMENT
Referring now to FIG. 1, there is shown a block diagram of the transponder
of the instant invention. In particular, the RF section 100 comprises a
transceiver which includes a transmitter and a receiver. The base-band
processor and controller section 200 comprises a microprocessor that
provides the overall control and logic function of the system. While not
limited thereto, a Motorola 68HC705C8 unit is used in the preferred
embodiment.
The energy manager section 300 includes the batteries which are used to
power the transponder system. Though the other sections are involved, the
energy manager section 300 addresses the biggest challenge in the
transponder design, i.e., performing its rather sophisticated electronics
task over a period of many years using only the energy supplied by one set
of small batteries. In the preferred embodiment, design life is eight
years with extensive use contemplated during those years.
Typically, the system uses lithium batteries in order to take advantage of
their high energy density. This results in a small battery with long life
and reasonable cost. The microprocessor is a CMOS type which is operated
at the lowest possible clock rate in order to achieve low power
consumption. Similarly, CMOS circuitry is used in the receiver. The
transmitter is not so critical in the area of energy usage but must be
designed for low cost and reliability. The transmitter uses a great deal
of power when it is ON, but it is ON very little during the transponder's
operating life whereby actual energy consumption is small.
High sensitivity RF receivers cannot be as energy efficient as the most
energy efficient microprocessors and logic circuitry because some active
components in receivers operate in a linear rather than switching mode in
order to amplify signals of very low power levels. In order to obtain long
lifetime under these constraints, the receiver is turned on for as small a
portion of the transponder duty cycle as possible while retaining
functional utility. The energy manager section 300 is, thus, a key
component to the successful operation of the transponder. The energy
manager includes a voltage regulator with an ultra-low parasitic current
to reduce voltage to levels that are both safe and energy efficient for
the proper operation of the transponder circuitry.
The CMOS microprocessor in section 200 also operates for as little of the
transponder's duty cycle as possible. Even in the wait mode (when only its
clock and timer circuitry are switching) the current consumption thereof
is still sufficiently high to be unacceptable for the long lifetimes
required in this system. Thus, the only circuitry that operates
continuously in a dynamic mode comprises certain parts of the energy
manager.
Referring now to FIG. 2, there is shown a schematic diagram of the energy
manager 300. The energy manager circuit 300 consists of two major parts:
1. The ultra-low parasitic current voltage regulator, noted previously,
which is the MC14007 IC (sometimes referred to as a 4007 IC) U2 and its
related components. The MC14007 IC is a CMOS integrated circuit device and
includes a collection of ultra-small geometry, ultra-low current, CMOS
transistors. In this embodiment, the circuits are connected and used more
as discrete circuit components than as an integrated circuit. A
representative schematic diagram is shown in FIG. 6 and described infra.
2. The remainder of the energy manager 300 relates to the IC U1 which is a
4047 multivibrator device, used here in a monostable or one-shot mode. The
one-shot is powered by voltage Vreg which is a stable low-voltage source
which provides minimum power consumption for the multivibrator U1. Of
course, the multivibrator will operate on higher and variable voltages. In
this embodiment, the one-shot is designed to time-out over a period of
about 10 seconds. The resistor R2 and capacitor C3 values are chosen for
timing and for ultra-low current consumption. Most of the time, these two
parts (i.e. multivibrator U1 and voltage regulator U2) of the transponder
are the only components that are in dynamic operation, and they consume
only a fraction of a microampere. This is the key to achieving the long
life goal.
The timer U1 is triggered to perform each 10 second timing cycle by the
microprocessor which is shown in FIG. 3. After the microprocessor triggers
the timer, the microprocessor firmware places the microprocessor in the
stop mode, which stops the microprocessor clock and all other switching in
the microprocessor. Operating the microprocessor U3 with stopped-clock and
low-voltage power furnished by the Vreg voltage source permits it to
retain its memory while using, typically, a very small fraction of a
microamphere of current.
The U2 portion of the circuit (including transistor Q1 and the associated
capacitors C1, C2 and resistors R3, R4) is an ultra-low parasitic current
low-voltage regulator which regulates the voltage at Vreg.
The energy manager 300 has been arbitrarily defined as consisting of the
voltage regulator U2, the multivibrator U1 and the battery BT1. The energy
manager, as a unit, provides the power to the rest of the circuitry; this
power is raw battery or regulated, as is appropriate. It furnishes the
timing function at ultra-low power to reactivate the microprocessor
approximately ten seconds after the microprocessor has turned off.
Referring now to FIG. 3, there is shown microprocessor U3. The
microprocessor module port Al is connected to I/O pin 5 of the
microprocessor which is used here as an output. When the firmware that is
resident in the microprocessor commands, the microprocessor causes a
transition signal on pin 5 that triggers multivibrator U1 and begins a
timing cycle as noted above. The microprocessor firmware next places the
microprocessor in the stop mode, causing the microprocessor internal clock
to stop. Operation of the microprocessor U3 is thereby suspended with only
Vreg applied to retain memory. The microprocessor U3 will remain in that
condition until some external reactivation event such as a reset or an
interrupt signal occurs.
When the multivibrator U2 completes its timing cycle (i.e., about ten
seconds), the Q output at pin 10 makes a transition. That transition
signal is coupled, through module port A4 (See FIG. 2) to pin 2, the
interrupt request pin, of the microprocessor U3. That transition causes
the microprocessor U3 to begin executing instructions again.
The purpose of the multivibrator U1 is to permit the microprocessor U3 to
remain inoperative and to have a means of activating it periodically. That
is, the microprocessor U3 triggers the multivibrator U1, starting a timing
cycle, and then stops its own clock. At the end of the 10 second timing
cycle, the microprocessor is restored to operation by the timer. This
provides a low-power "sleep" mode for the entire transponder, with a
period (usually very brief) of wakefulness every 10 seconds so that the
transponder can ascertain if any activity is occurring which requires its
participation. This permits transponder operation wherever required
combined with extremely low energy consumption over the transponder
lifetime.
Thus, the overall function of the transponder is to serve as a tag on an
inventory item as indicated in U.S. Pat. No. 4,637,950, to Caswell. The
transponder is normally placed on the inventory item. In general, a large
number of these transponders are found in a storage area which is equipped
with interrogation transceivers with which the transponder operates. There
can also be interrogation transceivers with limited range antennae
arranged in gateway configurations to detect these tagged
(transponder-equipped) items passing through, in addition to, or in lieu
of, interrogation transceivers arranged to monitor the controlled area in
the warehouse or other storage area.
The transponder must be operational and ready to receive and respond to
interrogations at any time. At the same time, energy budget goals must be
met in order to have a suitable lifetime. However, the receiver cannot
remain ON and monitoring constantly and still meet the energy consumption
goals. Thus, the microprocessor U3 serves as the overall controller and
turns the receiver ON when the receiver needs to be turned ON and turns
the transmitter ON when the transmitter needs to be ON. The purpose of
this ten-second timing cycle is to permit the receiver to come ON
periodically, but briefly, to check for transmitted signals.
To perform this check for transmitted signals, the microprocessor U3
(functioning in its overall transponder controller role) turns the
receiver ON and monitors the receiver output. The microprocessor U3 also
performs the baseband signal processing function for the receiver. The
microprocessor monitors the receiver output and determines whether or not
interrogations are, in fact, occurring. Since the receiver output is
binary, i.e. either a high or low state, this determination is done by
looking at the timing of transitions. If data is being received by the
receiver, the transitions will occur nominally at bit times and not at
other times. Of course, at any given bit time, a transition may or may not
occur, depending on the data being transmitted.
The receiver IC used in the transponder is designed to receive and
demodulate a frequency modulated (FM) radio frequency (RF) carrier and
produce an analog output by demodulation of the FM signal with a product
detector. If the RF carrier is FM modulated with a sine wave, the analog
output of the receiver will replicate the sine wave. In the preferred
embodiment, the transmission of binary information is desired, and the
binary data waveform is used to frequency modulate the RF signal
transmitted to the transponder by the interrogation transceiver. This is
commonly referred to as FSK data transmission. To provide a clean binary
output waveform with the correct levels for input to the microprocessor
U3, a voltage comparator circuit (included in the receiver IC) is used. It
compares the analog voltage levels from the product detector to a
reference voltage. When the analog voltage output from the product
detector (which is the input to the comparator) exceeds the preset
reference level, the comparator switches to one of two discrete output
voltage levels. When the analog voltage falls below the preset reference
voltage, the comparator switches to the other discrete voltage level. The
voltage levels that the comparator switches between are compatible with
the input levels required by microprocessor U3, so that the data
demodulated by the receiver IC can now be directly processed by the
microprocessor in the transponder. Referring now to FIGS. 4A and 4B, there
are shown schematic diagrams of the receiver and transmitter portions,
respectively, of the system. The circuits of FIGS. 4A and 4B are
interconnected at the respective terminals Y1, Y2, Y3 and Y4. These
circuit portions are related to each other and to the microprocessor U3
shown in FIG. 3. For example, the output to the processor U3 is from pin
15 of U4 which is the receiver IC (FIG. 4B). That output goes to module
port A5 which is connected to module port A5 in FIG. 3, where is it
connected to the input pins 12 and 14 of the microprocessor U3.
The microprocessor U3 samples the received data many times per bit time; as
an example consider eight samples per bit period where a bit period is one
millisecond. This is an eight kilohertz sample rate at the input to the
microprocessor. The receiver does not recognize any signals but simply
processes the RF carrier and recovers the baseband information which it
passes on to the microprocessor U3. If a spurious signal is received at
the appropriate frequency, the receiver produces an output that is
thresholded by the comparator and supplied to the microprocessor. The
microprocessor then determines that this signal is invalid in this system
and produces no response.
Thus, decision making and similar processes are performed in the
microprocessor U3 while the receiver U4 functions as an interface between
the microprocessor and the RF environment. As such the receiver is a
conventional CMOS FM receiver with low current requirements. However,
filtering (including capacitors C26 and C28) on the output is more severe
than would normally apply for an audio receiver.
The combination of the lack of DC stability of the demodulator and
subsequent gain stages and the high postdetection gain makes DC coupling
of the postdetection states not feasible. On the other hand, AC coupling
allows the DC level at the input to the comparator (U4 pin 14) t o drift
in response to the balance between 1's and 0's in the data being received,
as well as in response to circuit bias drift and leakages. This results in
displacing the comparator threshold voltage from the "midway between 0 and
1 level" that is desired; it causes noise in the thresholded output
waveform to the microprocessor. The solution is the clamping diodes D4 and
D5. They are hot-carrier schottky diodes, selected for their convenient
forward voltage drop (at low current) of about 0.3 volts. At one end, they
are connected to the voltage comparator input, U4 pin 14, which is the
point that needs to be maintained at a voltage of about 0.3 volts above
the comparator threshold voltage if the current data bit is a 1, and about
0.3 volts below the comparator threshold voltage if the current data bit
is a zero. The other end of the diodes is connected to U4 pin 17, which is
the IC U4's internally regulated voltage which is the comparator threshold
voltage. Thus, if the voltage at the comparator input begins to drift too
far positive, current will flow through the diode D4 on a 1 data bit to
restore the proper DC balance. Similarly, if the voltage at the comparator
input starts to drift too far negative, current flows through diode D5
during a 0 data bit to restore the proper DC level. The only additional
requirement is that the duration of uninterrupted strings of 1's and of
0's be limited. This is done by introducing "clamping bits", which have no
data significance, but are assigned 0 or 1 values as required to be
different than the following data bit. The first bit sent in each
interrogation sequence is a clamping bit, as is each fifth bit thereafter.
Clamping bits are added by the microprocessor in the interrogation
transceiver and ignored by the microprocessor in the transponder; they
transmit no data. Manchester coding could be used, but would require more
transitions in the course of each interrogation, and thus would introduce
more noise in the transponder environment of relatively simple signal
processing.
The effect of noise on system operation is minimized by use of the
narrowest bandwidth possible. In the RF domain this is addressed with
intermediate frequency filters of restricted bandwidth. After the received
intelligence has been transformed to a baseband signal, low pass RC
filters can be used to reduce the signal bandwidth even further. In the
preferred embodiment, low cost, readily available intermediate frequency
filters with bandwidth suitable for audio applications are used, and a
postdetection RC filter then limits the bandwidth appropriately for this
application. The data comes in at a bit rate of one kilohertz and anything
at higher frequencies is likely to be noise or an interfering signal which
should be rejected. The output filter includes resistor R13 and capacitor
C9.
As described above, the receiver output is supplied to the microprocessor
U3 where it is sampled by the firmware which determines if the frequency
of transitions is such that it could be data intended for the system. If
it does not appear to be data intended for the system, then the
microprocessor immediately, without further operation of the receiver or
itself (further operation of either or both would waste energy) turns off
the receiver; starts the multivibrator timing cycle for another ten
seconds; then stops its own clock and enters the sleep mode.
When the batteries are first connected to the transponder, the power on
reset to the microprocessor U3 pin 1 goes high which starts the
microprocessor clock. The clock frequency is controlled by crystal X3 in
FIG. 3. (The multivibrator U1 starts a timing cycle, too, because its
timing capacitor is discharged.) After the microprocessor starts, further
operation is under control of the firmware. After the battery has been
mounted onto the circuit board, the system has power and remains powered
forever until the battery discharges to a point where it can no longer
supply a useful terminal voltage whereupon the transponder is replaced. A
power ON/OFF switch is not utilized in this embodiment of the circuit.
Such a switch could be included in the circuit if so desired.
For the useful life of the transponder, the microprocessor U3 checks the
battery BT1 each time the transmitter is operated. When the transmitter is
keyed ON by the microprocessor, a heavy current draw exists. If the
battery is nearing the end of its useful life, the voltage Vbat will drop
sharply. The microprocessor U3 monitors the voltage when the transmitter
is turned ON. If the drops in the voltage Vbat exceed a threshold, the
microprocessor U3 sets a flag in its memory that the battery is low. This
information can be supplied to the system controller when the transponder
is interrogated and directed to respond with battery condition
information.
In the overall system operation, there will be interrogations looking for
transponders with low batteries. If a transponder has a low battery and
has identified itself as such (as described above), it will respond to
such an interrogation. A maintenance order will then be initiated to
replace the transponder on that item.
If the received data from the receiver appears to be noise or, in general,
does not have the characteristics of data from the interrogation
transceiver, the complete system will be shut down for another ten second
cycle. This total check occurs in a time that is of the order of two or
three milliseconds duration. The microprocessor U3 (which draws less
current than the receiver) will be ON for only a little longer than the
receiver. This operation results in an actual ON time of some two
milliseconds out of each ten seconds or about 0.02% duty cycle. Thus,
while the receiver draws a milliampere or two of current when it is ON,
its impact on the energy budget is reduced by a factor of almost 10,000.
The time-average-current draw for monitoring the RF environment when
interrogations are not occurring is, therefore, far less than a
microampere, which meets the operational life objectives of this system.
When the receiver is receiving signals that may be data from one of the
interrogation transceivers, the microprocessor has access to a
binary-coded version of the unique identification code that is assigned to
each transponder. In the present embodiment, that code is stored in a
one-time programmable memory as part of the microprocessor U3. It could,
in more general terms, be done with jumpers on the circuit board or it
could be entered into the microprocessor RAM and retained by the battery
voltage, in addition to the option of using PROM. Any of the above options
can also be combined with ROM storage of part of the bits.
If it appears that valid data is being transmitted, the microprocessor U3
keeps the receiver operating and continues operating while searching for a
distinctive sequence of data which, in the preferred embodiment, occurs at
the end of the data transmission.
This distinctive sequence is called a sync character. The sync character
includes bits of time duration incompatible with the normal data. In the
preferred embodiment, it is a chirp sequence of three one-zero pulse pairs
in which the durations of each pair are 5/8, 1/2 and 3/8 of the normal
duration of a data pulse pair. These special data are illegal characters
which do not occur at other times. The distinctive pattern is used to
identify the sync time at the end of the message. Thus, if the
microprocessor U3 monitors data that appears to be data from the system
but which lasts longer than a complete message without a sync character,
it shuts down the receiver and initiates a ten second timing sequence.
This is an alternate to the usual shutdown which occurs when the data is
found to be not valid.
When the microprocessor U3 receives a sync signal (or what appears to be a
sync signal), the position in the transceiver interrogation timing
sequence is established. Thus, the microprocessor is informed that the
next interrogation is about to occur and when it will start. The
microprocessor now shuts off its receiver (because the receiver is not
needed until the next interrogation begins) and proceeds to time the
duration until the next interrogation sequence should begin. The
microprocessor does not time this receiver shutdown with the multivibrator
U1 (which is fixed at approximately ten seconds). Rather, it uses a timer
included within the microprocessor which shuts down all microprocessor
functions except the clock oscillator, the circuit used to count the clock
cycles, the circuit which monitors the count, and the circuit which
restores program control when a selected count has been reached. This is
the precision timing mode of the microprocessor U3 and performs with a
high degree of accuracy due to the excellent accuracy and stability of the
crystal oscillator used to generate the microprocessor clock.
The precision timing is used for the timing which is associated with the
shutdowns during the interrogation sequence. At the end of the timing
cycle, the firmware of the microprocessor U3 regains control and proceeds
to perform the next operation required.
The basic energy conservation rules are that the receiver is turned off as
soon as it is established that it has no work to do, and, similarly, the
microprocessor U3 inactivates as soon as it is established that its
services are not presently required.
TRANSPONDER TIMING
The microprocessor turns on the receiver and monitors the receiver output.
If the receiver output appears to be noise or a spurious signal and not
valid data, the transponder shuts down for ten seconds. If it appears that
data has begun where it was expected, the microprocessor continues to
maintain the receiver powered-up and continues monitoring the data. As the
data is received, it is compared with the sequence of data in the
microprocessor memory which determines if the transponder should respond
or not. That sequence of data includes the unique identification code of
the transponder. It also includes the low battery bit noted supra, as well
as one or more mute bits. It also includes a removed status bit and one or
more spare bits to permit expansion without changing overall timing, or
introducing incompatibilities between new transponders and older ones.
The sequence in which these bits are placed in the interrogation
transceiver message which is being received by the transponder is also
important. The bits are sequenced so that the earliest bits have the
highest probability of establishing that the interrogation transceiver
message is not for this transponder. The bit that has the highest
probability of conveying that information is the first bit. The bit with
the second highest probability is the second bit, and so forth. Generally,
the low order bit of the transponder identification code is the first bit.
The next-to-low order bit is the second bit, and so forth. Then the
condition code bits begin to be worked in. The sequence of bits appears to
be random but it is not. It is a sequence of bits designed to accomplish
the desired result of minimizing energy consumption.
The microprocessor U3 monitors the received data stream. When it receives a
data item which indicates that this transponder will not need to respond
to this message, the receiver is turned off at once. It initiates
precision timing until the beginning of the next interrogator message and
is inactivated during its precision timing mode. When it is reactivated in
its precision timing mode, it repeats the operation.
All of the routine operations that occur when the microprocessor is not
receiving a message to which it is supposed to respond have been
described.
TRANSPONDER WAKEUP AND SYNCHRONIZATION
It should be noted that when the interrogation transceiver first sends a
message, most of the transponders are inactive and, therefore,
unresponsive. Even if the specific transponder to which the message is
directed happens to be activated at the beginning of the message, it will
not know that this was the beginning of the message and will not be able
to interpret the message. That is, the transponder must receive the sync
code and establish frame synchronization with the interrogation sequences.
Only after that has been done can it interpret an interrogation data
message.
Since most of the message time is spent representing data, a transponder
will, typically, be activated while the transceiver is sending data. At
the end of the data sequence, it receives the sync code and establishes
frame sync. Thus, on the next interrogation sequence it can actually
process the data. In a typical application, e.g. with a warehouse full of
transponder-equipped inventory items, the interrogation transceiver simply
starts with an interrogation that it needs to make and continues to repeat
that interrogation for a period of time in excess of ten seconds or until
it receives a response, whichever comes first. Over a period of time, all
of the transponders activate and become synchronized. Then communication
with the transponders can and does take place efficiently. When a
transponder receives a message that is meant for it alone (or as one of
the ambiguous messages, described infra, that are meant for many
transponders) and to which it is supposed to respond, it waits until the
appointed time space and then turns on its transmitter. It sends an
amplitude-modulated, chirped pulse sequence consisting of the data 010 | | |
