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Claims  |
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What is claimed is:
1. A configurable logic array, comprising:
(a) configuration storage means for storing program data specifying a user
defined data processing function;
(b) a plurality of logic means, CL.sub.1,1 to CL.sub.C,R arranged in an
array consisting of C columns and R rows, each of said logic means being
designated by CL.sub.c,r where c designates a column in the range 1 to C,
and r designates a row in the range 1 to R,
each logic means CL.sub.c,r being provided with a plurality of inputs for
receiving cell input signals and a plurality of outputs for generating
cell output signals in response to the received cell input signals;
(c) a plurality of input/output pads;
(d) a plurality of configurable input/output means, each being coupled to
an input/output pad, each having an I/O input and an I/O output, and each
being further coupled to the configuration storage means, for providing
configurable interfaces between the respective input/output pads and
respective I/O inputs and outputs in response to program data in the
configuration storage means,
wherein the plurality of configurable input/output means includes a first
subset without storage elements and a second subset with storage elements;
(e) configurable interconnect means, coupled to the plurality of logic
means, the plurality of configurable input/output means and the
configuration storage means, for programmably connecting respective inputs
and outputs of the logic means and of the configurable input/output means
to thereby form logical networks in response to program data in the
configuration storage means.
2. The configurable logic array of claim 1, wherein each of the
configurable input/output means includes:
tristate output means, coupled to the corresponding I/O output, for
supplying an output signal or presenting a high impedance state at the
corresponding I/O output in response to a supplied tristate control
signal; and
configurable control supply means for supplying the tristate control
signal, said control supply means being configurable in response to
program data stored in the configuration storage means.
3. The configurable logic array of claim 1, wherein the configurable
interconnect means includes:
a plurality of horizontal buses extending along the rows in the array, and
a plurality of vertical buses extending along the columns of the array and
wherein at least one bus of the plurality of horizontal buses extends
adjacent to at least one of said input/output means and includes an
uncommitted long line extending across the array;
a first plurality of programmable interconnect points, connected to the
uncommitted long line, for interconnecting respective outputs of logic
means and input/output means adjacent to the one bus with the uncommitted
long line in response to program data in the configuration storage means;
and
a second plurality of programmable interconnect points, connected to the
uncommitted long line, for interconnecting the uncommitted long line with
one of the plurality of vertical buses in response to program data in the
configuration storage means.
4. The configurable logic array of claim 1, wherein the configurable
interconnect means includes:
a plurality of horizontal buses extending along the rows in the array, and
a plurality of vertical vbuses extending along the columns of the array
and wherein at least one bus of the plurality of vertical buses extends
adjacent to at least one of said input/output means and includes an
uncommitted long line extending across the array;
a first plurality of programmable interconnect points, connected to the
uncommitted long line, for interconnecting respective outputs of logic
means and input/output means adjacent to the one bus with the uncommitted
long line in response to program data in the configuration storage means;
and
a second plurality of programmable interconnect points, connected to the
uncommitted long line, for interconnecting the uncommitted long line with
one of the plurality of horizontal buses in response to program data in
the configuration storage means.
5. The configurable logic array of claim 1, wherein the configurable
interconnect means includes double-wind direct-connect means for directly
connecting one output of logic means CL.sub.c,r to one input of logic
means CL.sub.3+2,r.
6. The configurable logic array of claim 1, wherein the configurable
interconnect means includes double-wind direct-connect means for directly
connecting one output of logic means CL.sub.c,r to one input o logic means
CL.sub.c,r+2.
7. The configurable logic array of claim 1, wherein the configurable
interconnect means includes a plurality of horizontal buses HB.sub.i, for
i equal to 1 to R+1, extending along the rows in the array, and a
plurality of vertical buses VB.sub.j, for j equal to 1 to C+1, extending
along the columns of the array, and further includes:
a plurality of switching matrices at respective intersections of the
horizontal and vertical buses, each having a plurality o horizontal bus
terminals and a plurality of vertical bus terminals, and each further
having configurable matrix switch means, coupled to the configuration
storage means, for interconnecting respective ones of the horizontal or
vertical bus terminals in response to program data in the configuration
storage means;
the plurality of horizontal buses each including a plurality of conductive
horizontal segments, at least one of the plurality of horizontal segments
having a first end connected to a horizontal bus terminal of a switching
matrix at the intersection of its respective horizontal bus with a
corresponding vertical bus VB.sub.j, for j equal to 1 through C-1, and a
second end connected to a horizontal bus terminal of a switching matrix at
the intersection of its respective horizontal bus with a corresponding
vertical bus VB.sub.j+2, each horizontal segment being connected to a
plurality of programmable interconnect points for interconnecting
respective inputs or outputs of logic means and input/output means with
the respective horizontal segment in response to program data in the
configuration storage means;
the plurality of vertical buses each including a plurality of conductive
vertical segments, at least one of plurality of vertical segments having a
first end connected to a vertical bus terminal of a switching matrix at
the intersection of its respective vertical bus with a corresponding
horizontal bus HB.sub.i, for i equal to 1 through R-1, and a second end
connected to a vertical bus terminal of a switching matrix at the
intersection of its respective vertical bus with a corresponding
horizontal bus HB.sub.i+2, each vertical segment being connected to a
plurality of programmable interconnect points for interconnecting
respective inputs or outputs of logic means and input/output means with
the respective vertical segment in response to program data in the
configuration storage means.
8. The configurable logic array of claim 1, wherein the configurable
interconnect means includes a plurality of horizontal buses HB.sub.i, for
i equal to 1 to R+1, extending along the rows in the array, and a
plurality of vertical buses VB.sub.j, for j equal to 1 to C+1, extending
along the columns of the array, so that each of the plurality of logic
means has four adjacent buses in the configurable interconnect means, and
wherein each of the plurality of logic means has at least four outputs
each coupled to a respective one of the four adjacent buses.
9. The configurable logic array of claim 1, wherein the configurable
interconnect means includes:
direct connect means for directly connecting a subset of the plurality of
outputs of a given logic means to the inputs of eight other logic means in
the array.
10. The configurable logic array of claim 1, wherein the configurable
interconnect means includes a plurality of horizontal buses HB.sub.i, for
i equal to 1 to R+1, extending along the rows in the array, and a
plurality of vertical buses VB.sub.j, for j equal to 1 to C+1, extending
along the columns of the array, and further includes:
a plurality of switching matrices at respective intersections of the
horizontal and vertical buses, each having a plurality of horizontal bus
terminals and a plurality of vertical bus terminals, and each further
having configurable matrix switch means, coupled to the configuration
storage means, for interconnecting respective ones of the horizontal or
vertical bus terminals in response to program data in the configuration
storage means;
the plurality of horizontal buses each including a plurality of conductive
horizontal segments, at least one of the plurality of horizontal segments
having a first end connected to a horizontal bus terminal of a switching
matrix at the intersection of its respective horizontal bus with a
corresponding vertical bus VB.sub.j, for j equal to 1 through C-1, and a
second end connected to a horizontal bus terminal of a switching matrix at
the intersection of its respective horizontal bus with a corresponding
vertical bus VB.sub.j+2, each horizontal segment being connected to a
plurality of programmable interconnect points for interconnecting
respective inputs or outputs of logic means and input/output means with
the respective horizontal segment in response to program data in the
configuration storage means;
the plurality of vertical buses each including a plurality of conductive
vertical segments, at least one of plurality of vertical segments having a
first end connected to a vertical bus terminal of a switching matrix at
the intersection of its respective vertical bus with a corresponding
horizontal bus HB.sub.i, for i equal to 1 through R-1, and a second end
connected to a vertical bus terminal of a switching matrix at the
intersection of its respective vertical bus with a corresponding
horizontal bus HB.sub.i+2, each vertical segment being connected to a
plurality of programmable interconnect points for interconnecting
respective inputs or outputs of logic means and input/output means with
the respective vertical segment in response to program data in the
configuration storage means; and
configurable recovering means, coupled to at least one horizontal segment,
said recovering means being configurable for recovering signals on the one
horizontal segment propagating in a first direction, for repowering
signals on the one horizontal segment propagating in a second direction,
or for passing signals propagating in either the first direction or the
second direction, in response to program data in the configuration storage
means.
11. The configurable logic array of claim 1, wherein the configurable
interconnect means includes:
a plurality of horizontal buses HB.sub.i, extending along the rows in the
array, and a plurality of vertical buses VB.sub.j, extending along the
columns of the array, each bus including a control line extending across
the array for carrying a control signal to or from an adjacent logic means
or input/output means;
a first plurality of programmable interconnect points, each connected to
the control line in a given horizontal or vertical bus, for
interconnecting respective outputs of logic means and input/output means
adjacent to the given bus with the control line of the given bus in
response to program data in the configuration storage means;
a second plurality of interconnect points, each connected to the control
line in a respective horizontal or vertical bus, for interconnecting
respective inputs of logic means and input/output means adjacent to the
control line of the respective bus;
conducting line means for conducting a control signal between control
lines;
drive means for driving a control signal onto said conducting line means;
and
a plurality of configurable control line driving means, each coupled to the
control line in a respective bus and to the conducting line means, for
driving a signal from the control line in the respective bus to the
conducting line means, or for driving a signal from the conducting line
means to the control line in the respective bus, in response to program
data in the configuration storage means.
12. The configurable logic array of claim 1, wherein the configurable
interconnect means includes:
double-wide direct-connect means for directly connecting an output of a
configurable input/output means in the second subset adjacent to column 1
to an input of a logic means in column 2.
13. The configurable logic array of claim 1, wherein the configurable
interconnect means includes:
double-wide direct-connect means for directly connecting an output of a
configurable input/output means in the second subset adjacent to column C
to an input of a logic means in column C-1.
14. The configurable logic array of claim 1, wherein the configurable
interconnect means includes:
double-wide direct-connect means for directly connecting an output of a
configurable input/output means in the second subset adjacent to row 1 to
an input of a logic means in row 2.
15. The configurable logic array of claim 1, wherein the configurable
interconnect means includes:
double-wide direct-connect means for directly connecting an output of a
configurable input/output means in the second subset adjacent to row R to
an input of a logic means in row R-1.
16. The configurable logic array of claim 1, wherein the storage elements
in the second subset of configurable input/output means each have a
register input and a register output, and further including:
selective connecting means, coupled to the storage elements i the second
subset of configurable input/output means and to the configuration storage
means, for selectively connecting the register output of a first selected
storage element in a first configurable input/output means in the second
subset to the register input of a second selected storage element in a
second reconfigurable input/output means in the second subset.
17. The configurable logic array of claim 1, wherein the storage elements
in the second subset of configurable input/output means each have a
register input and a register output, and further including:
programmable connecting means, coupled to the storage elements in the
second subset of configurable input/output means and to the configuration
storage means, for connecting the register input of the storage element in
a selected configurable input/output means in he second subset to the
configurable interconnect means, and for connecting the register output of
the storage element in a selected configurable input/output means in the
second subset to the configurable interconnect means, in response to
program data in the configuration storage means.
18. The configurable logic array of claim 1, wherein the storage elements
in the second subset of configurable input/output means each have a
register input and a register output, and further including:
programmable connecting means, coupled to the storage elements in the
second subset of configurable input/output means and to the configuration
storage means, for connecting the register input of the storage element in
a selected configurable input/output means in the second subset to the
respective input/output pad, and for connecting the register output of the
storage element in a selected configurable input/output means in the
second subset to the configurable interconnect means, in response to
program data in the configuration storage means.
19. The configurable logic array of claim 1, wherein at least one of the
configurable input/output means in the second subset includes:
a first storage element, having an input and an output and receiving a
first clock signal, for storing data presented to its input in response to
the first clock signal and for supplying stored data to its output;
a second storage element, having an input and an output and receiving a
second clock signal, for storing data presented to its input in response
to the second clock signal and for supplying stored data to its output;
and
intra-cell connection means, coupled to the first and second storage
elements, to the respective input/output pad and to the configurable
interconnect means, for connecting the respective input/output pad to the
input of the first storage element, for connecting the output of the first
storage element to the input of the second storage element, and for
connecting the output of the second storage element to the configurable
interconnect means.
20. A plurality of configurable input/output cells IO.sub.i, for i equal to
1 through Z, providing configurable interconnection between input/output
pads and internal portions of a configurable logic array, the configurable
logic array including a configuration memory for storing program data, an
array of configurable logic cells and a programmable interconnect, each
input/output cell IO.sub.i, comprising:
(a) first storage means, having a first-storage input and a first-storage
output, for storing a signal supplied to the first-storage input and
supplying the stored signal to the first-storage output;
(b) second storage means, having a second-storage input and a
second-storage output, for storing a signal supplied to the second-storage
input and supplying the stored signal to the second-storage output;
(c) first selecting means, having a first-select output coupled to the
first-storage input and having a plurality of first-select inputs, the
first selecting means being coupled to the configuration memory, for
connecting one of its first-select inputs to its first-select output in
response to program data in the configuration memory;
(d) second selecting means, having a second-select output coupled to the
second-storage input and having a plurality of second-select inputs, the
second selecting means being coupled to the configuration memory, for
connecting one of its second-select inputs to its second-select output in
response to program data in the configuration memory;
(e) third selecting means, having a third-select output coupled to a
corresponding input/output pad and having a plurality of third-select
inputs, the third selecting means being coupled to the configuration
memory, for connecting one of its third-select inputs to its third-select
output in response to program data in the configuration memory; and
(f) fourth selecting means, having a fourth-select output coupled to the
programmable interconnect and having a plurality of fourth-select inputs,
the fourth selecting means being coupled to the configuration memory, for
connecting one of its fourth-select inputs to its fourth-select output in
response to program data in the configuration memory; and wherein
the plurality of first-select inputs belonging to the first selecting means
includes a first input connected to the input/output pad, a second input
connected to the first-storage output of the first storage means in
input/output cell IO.sub.i-1, and a third input connected to the
second-storage output of the second storage means in input/output cell
IO.sub.i+1 ; and
the plurality of second-select inputs belonging to the second selecting
means includes a first input connected to the programmable interconnect, a
second input connected to the first-storage output of the first storage
means in input/output cell IO.sub.i-1, and a third input connected to the
second-storage output of the second storage means in input/output cell
IO.sub.i+1, and a fourth input connected to the first-storage output of
the first storage means in the present input/output cell IO.sub.i ;
the plurality of third-select inputs belonging to the third selecting means
includes a first input connected to the first-storage output of the first
storage means, a second input connected to the second-storage output of
the second storage means, and a third input connected to the programmable
interconnect; and
the plurality of fourth-select inputs belonging to the fourth selecting
means includes a first input connected to the first-storage output of the
first storage means, a second input connected to the second-storage output
of the second storage means, and a third input connected to the
input/output pad.
21. A configurable logic array, comprising:
(a) configuration storage means for storing program data specifying a user
defined data processing function;
(b) a plurality of logic means, CL.sub.1,1 to CL.sub.C,R arranged in an
array consisting of C columns and R rows, each of said logic means being
designated by CL.sub.c,r where c designates a column in the range 1 to C,
and r designates a row in the range 1 to R,
each logic means CL.sub.c,r being provided with a plurality of inputs for
receiving cell input signals and a plurality of outputs for generating
cell output signals in response to the received cell input signals;
(c) a plurality of input/output pads;
(d) a plurality of configurable input/output means, each being coupled to
an input/output pad, each having a plurality of I/O inputs and a plurality
of I/O outputs, and each being further coupled to the configuration
storage means, for providing configurable interfaces between the
respective input/output pads and respective I/O inputs and outputs in
response to program data in the configuration storage means,
wherein the plurality of configurable input/output means includes a first
subset without storage elements and a second subset with storage elements,
each storage element of the second subset having a register input and a
register output;
(e) configurable interconnect means, coupled to the plurality of logic
means, the plurality of configurable input/output means and the
configuration storage means, for programmably connecting respective inputs
and outputs of the logic means and of the configurable input/output means
to thereby form logical networks in response to program data in the
configuration storage means; and
(f) storage-chaining means, coupled to the storage elements in the second
subset of configurable input/output means and to the configuration storage
means, for selectively connecting the register output of a storage element
in a first selected configurable input/output means in the second subset
to the register input of a storage element in a second selected
configurable input/output means in the second subset.
22. The configurable logic array of claim 21, wherein each configurable
input/output means of the second subset includes:
configurable storage-connecting means, coupled to the respective storage
elements in the configurable input/output means in the second subset and
to the configuration storage means, for connecting the register input of
the respective storage element to a first part of the configurable
interconnect means, and for connecting the register output of the
respective storage element to a second part of the configurable
interconnect means, in response to program data in the configuration
storage means.
23. The configurable logic array of claim 21, wherein each configurable
input/output means of the second subset includes:
configurable storage-connecting means, coupled to the respective storage
elements in the configurable input/output means in the second subset and
to the configuration storage means, for selectively connecting one or both
of the register input and the register output of a storage element in a
selected configurable input/output means in the second subset to the
respective input/output pad, in response t program data in the
configuration storage means.
24. The configurable logic array of claim 21, wherein each of the
configurable input/output means of the second subset includes as its
storage elements:
a first storage element, having an input and an output and receiving a
first clock signal, for storing data presented to its input in response to
the first clock signal and for supplying stored data to its output;
a second storage element, having an input and an output and receiving a
second clock signal, for storing data presented to its input in response
to the second clock signal and for supplying stored data to its output;
and wherein each of the configurable input/output means of the second
subset further includes:
intra-cell connection means, coupled to the first and second storage
elements, to the respective input/output pad and to the configurable
interconnect means, for connecting the respective input/output pad to the
input of the first storage element, for connecting the output of the first
storage element to the input of the second storage element, and for
connecting the output of the second storage element to the configurable
interconnect means.
25. The configurable logic array of claim 21, wherein each of the
configurable input/output means includes:
tristate output means, coupled to a corresponding one of the I/O outputs,
for supplying an output signal or presenting a high impedance state at the
corresponding I/O output in response to a supplied tristate control
signal; and
configurable control supply means for supplying the tristate control
signal, said control supply means being configurable in response to
program data stored in the configuration storage means.
26. A configurable logic array, comprising:
(a) configuration storage means for storing program data specifying a user
defined data processing function;
(b) a plurality of logic means, CL.sub.1,1 to CL.sub.C,R arranged in an
array consisting of C columns and R rows, each of said logic means being
designated by CL.sub.c,r where c designates a column in the range 1 to C,
and r designates a row in the range 1 to R,
each logic means CL.sub.c,r being provided with a plurality of inputs for
receiving cell input signals and a plurality of outputs for generating
cell output signals in response to the received cell input signals;
(c) a plurality of input/output pads;
(d) a plurality of configurable input/output means, each being coupled to
an input/output pad, each having a plurality of I/O inputs and a plurality
of I/O outputs, and each being further coupled to the configuration
storage means, for providing configurable interfaces between the
respective input/output pads and respective I/O inputs and outputs in
response to program data in the configuration storage means,
wherein the plurality of configurable input/output means includes a first
subset without storage elements and a second subset with storage elements,
each storage element of the second subset having a register input and a
register output;
(e) configurable interconnect means, coupled to the plurality of logic
means, the plurality of configurable input/output means and the
configuration storage means, for programmably connecting respective inputs
and outputs of the logic means and of the configurable input/output means
to thereby form logical networks in response to program data in the
configuration storage means; and
wherein each configurable input/output means of the second subset includes:
configurable storage-connecting means, coupled to the respective storage
elements in the second subset of configurable input/output means and to
the configuration storage means, for connecting the register input of the
respective storage element to a first part of the configurable
interconnect means, and for connecting the register output of the
respective storage element to a second part of the configurable
interconnect means, in response to program data in the configuration
storage means.
27. The configurable logic array of claim 26, wherein said configurable
input/output means are distributed around a peripheral portion of the
logic array and wherein the logic array further includes:
periphery-chaining means, coupled to the storage elements n the second
subset of configurable input/output means and to the configuration storage
means, for selectively connecting the output of the storage element in a
first selected configurable input/output means in the second subset to the
input of the storage element in an adjacent second selected configurable
input/output means in the second subset.
28. The configurable logic array of claim 26, wherein selectable ones of
the configurable input/output means of the second subset each includes:
configurable storage-connecting means, coupled to the respective storage
elements in the configurable input/output means of the second subset and
to the configuration storage means, for selectively connecting one or both
of the register input and the register output of a storage element in a
selected configurable input/output means in the second subset to the
respective input/output pad of the selected configurable input/output
means, in response to program data in the configuration storage means.
29. The configurable logic array of claim 26, wherein each of the
configurable input/output means of the second subset includes as its
storage elements:
a first storage element, having an input and an output and receiving a
first clock signal, for storing data presented to its input in response to
the first clock signal and for supplying stored data to its output;
a second storage element, having an input and an output and receiving a
second clock signal, for storing data presented to its input in response
to the second clock signal and for supplying stored data to its output;
and
wherein each of the configurable input/output means of the second subset
further includes:
configurable intra-cell connection means, responsive to program data in the
configuration storage means and coupled to the first and second storage
elements, to the respective input/output pad and to the configurable
interconnect means, for selectively connecting the respective input/output
pad to the input of the first storage element to the input of the second
storage element, and for selectively connecting the output of the second
storage element to the configurable interconnect means, in response to
said program data.
30. The configurable logic array of claim 26, wherein each of the
configurable input/output means includes:
tristate output means, coupled to a corresponding one of the I/O outputs,
for supplying an output signal or presenting a high impedance state at the
corresponding I/O output in response to a supplied tristate control
signal; and
configurable control supply means for supplying the tristate control
signal, said control supply means being configurable in response to
program data stored in the configuration storage means to supply a
preselected one of plural control signals.
31. A configurable logic array, comprising:
configuration storage means for storing program data specifying a user
defined data processing function;
a plurality of configurable logic means CL.sub.c,r, arranged in an array
consisting of C columns and R rows, where c designates a column in the
range 1 to C, and r designates a row in the range 1 to R, each of the
configurable logic means CL.sub.c,r having a plurality of inputs and
outputs, and coupled to the configuration storage means, for generating
cell output signals at the respective plurality of outputs in response to
cell input signals supplied to the respective plurality of inputs and in
response to program data in the configuration storage means;
a plurality of configurable input/output means, each coupled to an
input/output pad and having an input and an output, and coupled to the
configuration storage means, for providing configurable interface between
the respective input/output pads and the respective inputs and outputs in
response to program data in the configuration storage means; and
configurable interconnect means, coupled to the plurality of configurable
logic means, the plurality of configurable input/output means and the
configuration storage means, and connecting inputs and outputs of
configurable logic means and configurable input/output means into logical
networks in response to program data in the configuration storage means;
wherein each configurable input/output means in a subset of the plurality
of configurable input/output means includes a storage element having an
input and an output, and further including
means, coupled to the storage elements in the subset of configurable
input/output means and to the configuration storage means, for connecting
the input of the storage element in a selected configurable input/output
means in the subset to the respective input/output pad, and for connecting
the output of the storage element in the selected configurable
input/output means in the subset to the respective input/output pad, in
response to program data in the configuration storage means.
32. The configurable logic array of claim 31, further including
means, coupled to the storage elements in the subset of configurable
input/output means and to the configuration storage means, for selectively
connecting the output of the storage element in a first selected
configurable input/output means in the subset to the input of the storage
element in a second selected configurable input/output means in the
subset.
33. The configurable logic array of claim 31, further including:
means, coupled to the storage elements in the configurable input/output
means in the subset and to the configuration storage means, for connecting
the input of the storage element in a first selected configurable
input/output means in the subset to the configurable interconnect means,
and for connecting the output of the storage element in the first selected
configurable input/output means in the subset to the configurable
interconnect means, in response to program data in the configuration
storage means.
34. The configurable logic array of claim 31, wherein at least one of the
configurable input/output means includes:
a first storage element, having an input and an output and receiving a
first clock signal, for storing data from its input in response to the
first clock signal for supply to its output;
a second storage element, having an input and an output and receiving a
second clock signal, for storing data from its input in response to the
second clock signal for supply to its output; and
means, coupled to the first and second storage elements, to the respective
input/output pad and to the configurable interconnect means, for
connecting the respective input/output pad to the input of the first
storage element, the output of the first storage element to the input of
the second storage element, and the output of the second storage element
to the configurable interconnect means.
35. The configurable logic array of claim 31, wherein each of the
configurable input/output means includes:
a tristate output means supplying an output signal or presenting a high
impedance state in response to a tristate control signal; and
means for supplying the tristate control signal in response to program data
in the configuration storage means.
36. A configurable logic array, comprising:
configuration storage means for storing program data specifying a user
defined data processing function;
a plurality of configurable logic means CL.sub.c,r, arranged in an array
consisting of C columns and R rows, where c designates a column in the
range 1 to C, and r designates a row in the range 1 to R, each of the
configurable logic means CL.sub.c,r having a plurality of inputs and
outputs, and coupled to the configuration storage means, for generating
cell output signals at the respective plurality of outputs in response to
cell input signals supplied to the respective plurality of inputs and in
response to program data in the configuration storage means;
a plurality of configurable input/output means, each coupled to an
input/output pad and having an input and an output, and coupled to the
configuration storage means, for providing configurable interfaces between
the respective input/output pads and the respective inputs and outputs in
response to program data in the configuration storage means; and
configurable interconnect means, coupled to the plurality of configurable
logic means, the plurality of configurable input/output means and the
configuration storage means, for connecting inputs and outputs of
configurable logic means and configurable input/output means into logical
networks in response to program data in the configuration storage means;
wherein at least one of the configurable input/output means includes:
a first storage element, having an input and an output and receiving a
first clock signal, for storing data from its input in response to the
first clock signal for supply to its output;
a second storage element, having an input and an output and receiving a
second clock signal, for storing data from its input in response to the
second clock signal for supply to its output; and
means, coupled to the first and second storage elements, to the respective
input/output pad and to the configurable interconnect means, for
connecting the respective input/output pad to the input of the first
storage element, the output of the first storage element to the input of
the second storage element, and the output of the second storage element
to the configurable interconnect means.
37. The configurable logic array of claim 36, wherein each configurable
input/output means in a subset of the plurality of configurable
input/output means includes a storage element having an input and an
output, and further including:
means, coupled to the storage elements in the subset of configurable
input/output means and to the configuration storage means, for selectively
connecting the output of the storage element in a first selected
configurable input/output means in the subset to the input of the storage
element in a second selected configurable input/output means in the
subset.
38. The configurable logic array of claim 36, wherein each configurable
input/output means in a subset of the plurality of configurable
input/output means includes a storage element having an input and an
output, and further including:
means, coupled to the storage elements in the configurable input/output
means in the subset and to the configuration storage means, for connecting
the input of the storage element in a | | |
