A memory security device within a chip which employs a power source coupled to the memory. The power source produces a signal having a level sufficient to erase or destroy the memory when the chip is exposed to acid. The power source includes an electrolytic cell for producing a direct voltage output, and an electrolytic signal amplification circuit coupled between the electrolytic cell and the memory.
A chip cover for complete or partial covering of electrical, electronic, optoelectronic and/or electromechanical components includes an activator capable of fully or partially destroying the electrical, electronic, optoelectronic and/or electromechanical components of the chip when activated. The activator can be activated by an attempt to remove the chip cover from the chip. In this way it is possible to reliably prevent reverse engineering and/or manipulation of the chip.
